i965: add a new virtual opcode: SHADER_OPCODE_TXF_MS

This is very similar to the TXF opcode, but lowers to `ld2dms` rather
than `ld` on Gen7.

V4: - add SHADER_OPCODE_TXF_MS to is_tex() functions, so regalloc thinks
      it actually writes the correct number of registers. Otherwise in
      nontrivial shaders some of the registers tend to get clobbered,
      producing bad results.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Paul Berry <stereotype441@gmail.com>

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index d0794c841ab00d9dc445e6079d3f5c9f70789080..d9b7f9aeb15a1edf0d753cb7d211aa1a9bd37c34 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -709,6 +709,7 @@ enum opcode {
    SHADER_OPCODE_TXL,
    SHADER_OPCODE_TXS,
    FS_OPCODE_TXB,
+   SHADER_OPCODE_TXF_MS,
 
    SHADER_OPCODE_SHADER_TIME_ADD,
 

diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index fe3470184723d4f8017051f699ff06bc1890b5e4..7cc49347d8321abb6aff72a2b4a491cc2efa0fc2 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -336,6 +336,7 @@ fs_inst::is_tex()
            opcode == FS_OPCODE_TXB ||
            opcode == SHADER_OPCODE_TXD ||
            opcode == SHADER_OPCODE_TXF ||
+           opcode == SHADER_OPCODE_TXF_MS ||
            opcode == SHADER_OPCODE_TXL ||
            opcode == SHADER_OPCODE_TXS);
 }
@@ -740,6 +741,7 @@ fs_visitor::implied_mrf_writes(fs_inst *inst)
    case FS_OPCODE_TXB:
    case SHADER_OPCODE_TXD:
    case SHADER_OPCODE_TXF:
+   case SHADER_OPCODE_TXF_MS:
    case SHADER_OPCODE_TXL:
    case SHADER_OPCODE_TXS:
       return 1;

diff --git a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp b/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
index a25f594d9d88cf01193e21096d6c99d2dbbd9914..2391ad1202674f5630c723ee2af73c6dfe1488e5 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
@@ -398,6 +398,12 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src
       case SHADER_OPCODE_TXF:
         msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
         break;
+      case SHADER_OPCODE_TXF_MS:
+         if (intel->gen >= 7)
+            msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
+         else
+            msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
+         break;
       default:
         assert(!"not reached");
         break;
@@ -1236,6 +1242,7 @@ fs_generator::generate_code(exec_list *instructions)
       case FS_OPCODE_TXB:
       case SHADER_OPCODE_TXD:
       case SHADER_OPCODE_TXF:
+      case SHADER_OPCODE_TXF_MS:
       case SHADER_OPCODE_TXL:
       case SHADER_OPCODE_TXS:
         generate_tex(inst, dst, src[0]);

diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index 70f6b9d37f5392000d60d0256ae8e89b1febf18c..8182dccb02fa7df48eed4987a093b32f04dffee1 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -146,6 +146,7 @@ vec4_instruction::is_tex()
    return (opcode == SHADER_OPCODE_TEX ||
           opcode == SHADER_OPCODE_TXD ||
           opcode == SHADER_OPCODE_TXF ||
+          opcode == SHADER_OPCODE_TXF_MS ||
           opcode == SHADER_OPCODE_TXL ||
           opcode == SHADER_OPCODE_TXS);
 }

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
index cc2f5d4c8b009bfa8fd95897a335ad7cee0a3d83..b73711cf7adb42ab5245ff489be1029e4193e3c8 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
@@ -289,6 +289,12 @@ vec4_generator::generate_tex(vec4_instruction *inst,
       case SHADER_OPCODE_TXF:
         msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
         break;
+      case SHADER_OPCODE_TXF_MS:
+         if (intel->gen >= 7)
+            msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
+         else
+            msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
+         break;
       case SHADER_OPCODE_TXS:
         msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
         break;
@@ -645,6 +651,7 @@ vec4_generator::generate_vs_instruction(vec4_instruction *instruction,
    case SHADER_OPCODE_TEX:
    case SHADER_OPCODE_TXD:
    case SHADER_OPCODE_TXF:
+   case SHADER_OPCODE_TXF_MS:
    case SHADER_OPCODE_TXL:
    case SHADER_OPCODE_TXS:
       generate_tex(inst, dst, src[0]);