* mips3264r2.igen (DSHD): Fix compile warning.

diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog
index 9914dafd5190872ddbb12c47ad1b38e89942a0ee..c1a1677886060527da7cf2fff46b364044a687a5 100644 (file)
--- a/sim/mips/ChangeLog
+++ b/sim/mips/ChangeLog
@@ -1,3 +1,7 @@
+2007-05-15  Thiemo Seufer  <ths@mips.com>
+
+       * mips3264r2.igen (DSHD): Fix compile warning.
+
 2007-05-14  Thiemo Seufer  <ths@mips.com>
 
        * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,

diff --git a/sim/mips/mips3264r2.igen b/sim/mips/mips3264r2.igen
index e0d1326354e5f5a2ff25f50ad3ddb3d493254b1b..bfd2980f76884a434a8b87fedb7786b677a9f0ed 100644 (file)
--- a/sim/mips/mips3264r2.igen
+++ b/sim/mips/mips3264r2.igen
@@ -126,8 +126,8 @@
   d = GPR[RT];
   GPR[RD] = ((d >> 48)
             | (d << 48)
-            | ((d & 0x0000ffff00000000) >> 16)
-            | ((d & 0x00000000ffff0000) << 16));
+            | ((d & 0x0000ffff00000000ULL) >> 16)
+            | ((d & 0x00000000ffff0000ULL) << 16));
   TRACE_ALU_RESULT1 (GPR[RD]);
 }