arm, dev: Add support for listing DMA ports in new platforms

When using a Ruby memory system, the Ruby configuration scripts expect
to get a list of DMA ports to create the necessary DMA sequencers. Add
support in the utility functions that wire up devices to append DMA
ports to a list instead of connecting them to the IO bus. These
functions are currently only used by the VExpress_GEM5_V1 platform.

Change-Id: I46059e46b0f69e7be5f267e396811bd3caa3ed63
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Brad Beckmann <brad.beckmann@amd.com>

diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index 8dedc068d18297e157fcf28d21f7f4e7d5eb50fb..30e498ce13446a9396780b06d134eaac3c2615ad 100644 (file)
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -301,12 +301,18 @@ class RealView(Platform):
 
     _off_chip_ranges = []
 
-    def _attach_io(self, devices, bus):
+    def _attach_device(self, device, bus, dma_ports=None):
+        if hasattr(device, "pio"):
+            device.pio = bus.master
+        if hasattr(device, "dma"):
+            if dma_ports is None:
+                device.dma = bus.slave
+            else:
+                dma_ports.append(device.dma)
+
+    def _attach_io(self, devices, *args, **kwargs):
         for d in devices:
-            if hasattr(d, "pio"):
-                d.pio = bus.master
-            if hasattr(d, "dma"):
-                d.dma = bus.slave
+            self._attach_device(d, *args, **kwargs)
 
     def _attach_clk(self, devices, clkdomain):
         for d in devices:
@@ -325,13 +331,13 @@ class RealView(Platform):
     def offChipIOClkDomain(self, clkdomain):
         self._attach_clk(self._off_chip_devices(), clkdomain)
 
-    def attachOnChipIO(self, bus, bridge=None):
-        self._attach_io(self._on_chip_devices(), bus)
+    def attachOnChipIO(self, bus, bridge=None, **kwargs):
+        self._attach_io(self._on_chip_devices(), bus, **kwargs)
         if bridge:
             bridge.ranges = self._off_chip_ranges
 
-    def attachIO(self, bus):
-        self._attach_io(self._off_chip_devices(), bus)
+    def attachIO(self, *args, **kwargs):
+        self._attach_io(self._off_chip_devices(), *args, **kwargs)
 
 
     def setupBootLoader(self, mem_bus, cur_sys, loc):
@@ -923,10 +929,9 @@ Interrupts:
             self.energy_ctrl,
         ]
 
-    def attachPciDevice(self, device, bus):
+    def attachPciDevice(self, device, *args, **kwargs):
         device.host = self.pci_host
-        device.pio = bus.master
-        device.dma = bus.slave
+        self._attach_device(device, *args, **kwargs)
 
     def setupBootLoader(self, mem_bus, cur_sys, loc):
         self.nvmem = SimpleMemory(range=AddrRange(0, size='64MB'),