Reduce simulated and default FPGA RAM to 384kB

Micropython has been able to fit into 384kB for ages, so lets reduce our
simulated RAM. This is useful for testing if micropython will run on an
ECP5 85k, which has enough BRAM for 384kB but not enough for 512kB.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>

diff --git a/core_tb.vhdl b/core_tb.vhdl
index 90fc30c28c5dbcf430b2a40a004ce38ca2e8ca29..8597e060d86cb78f81ff138f78084a3d61d4a115 100644 (file)
--- a/core_tb.vhdl
+++ b/core_tb.vhdl
@@ -19,7 +19,7 @@ begin
     soc0: entity work.soc
        generic map(
            SIM => true,
-           MEMORY_SIZE => 524288,
+           MEMORY_SIZE => (384*1024),
            RAM_INIT_FILE => "main_ram.bin",
            RESET_LOW => false
            )

diff --git a/fpga/toplevel.vhdl b/fpga/toplevel.vhdl
index 38af730e9ccd539e19366054dad4f68dfbf654f7..a3b8282fbd2602065d33711d0face773db4a82b1 100644 (file)
--- a/fpga/toplevel.vhdl
+++ b/fpga/toplevel.vhdl
@@ -3,7 +3,7 @@ use ieee.std_logic_1164.all;
 
 entity toplevel is
     generic (
-       MEMORY_SIZE   : positive := 524288;
+       MEMORY_SIZE   : positive := (384*1024);
        RAM_INIT_FILE : string   := "firmware.hex";
        RESET_LOW     : boolean  := true;
        CLK_INPUT     : positive := 100000000;