(no commit message)

diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn
index 62e6a2c2dcafc247d49f77b4d181a76dd2dd20f9..765f43a7b683997b696c1a6a4e83984943fcc4ac 100644 (file)
--- a/openpower/sv/ldst.mdwn
+++ b/openpower/sv/ldst.mdwn
@@ -30,8 +30,9 @@ Memory Operations as well.
 Vectorised Load and Store also presents an extra dimension (literally)
 which creates scenarios unique to Vector applications, that a Scalar
 (and even a SIMD) ISA simply never encounters.  SVP64 endeavours to
-add such modes without changing the behaviour of the underlying Base
-(Scalar) v3.0B operations.
+add the modes typically found in *all* Scalable Vector ISAs,
+without changing the behaviour of the underlying Base
+(Scalar) v3.0B operations in any way.
 
 # Modes overview