Improved cells_sim_digital model for GP_COUNT8

diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index fe11d701e3c3c9e66258954468bfd7051d70fc60..13d7d19df56c1def2b0ba3eb01c6107ef9d155ef 100644 (file)
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -5,45 +5,6 @@
 
 //Cells still in this file have INCOMPLETE simulation models, need to finish them
 
-module GP_COUNT8(input CLK, input wire RST, output reg OUT, output reg[7:0] POUT);
-
-       parameter RESET_MODE    = "RISING";
-
-       parameter COUNT_TO              = 8'h1;
-       parameter CLKIN_DIVIDE  = 1;
-
-       //more complex hard IP blocks are not supported for simulation yet
-
-       reg[7:0] count = COUNT_TO;
-
-       //Combinatorially output whenever we wrap low
-       always @(*) begin
-               OUT <= (count == 8'h0);
-               OUT <= count;
-       end
-
-       //POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
-       //Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
-       //Datasheet seems to indicate that reset is asynchronous, but for now we model as sync due to Yosys issues...
-       always @(posedge CLK) begin
-
-               count           <= count - 1'd1;
-
-               if(count == 0)
-                       count   <= COUNT_TO;
-
-               /*
-               if((RESET_MODE == "RISING") && RST)
-                       count   <= 0;
-               if((RESET_MODE == "FALLING") && !RST)
-                       count   <= 0;
-               if((RESET_MODE == "BOTH") && RST)
-                       count   <= 0;
-               */
-       end
-
-endmodule
-
 module GP_COUNT14(input CLK, input wire RST, output reg OUT);
 
        parameter RESET_MODE    = "RISING";

diff --git a/techlibs/greenpak4/cells_sim_digital.v b/techlibs/greenpak4/cells_sim_digital.v
index cf80cece0fc463ef5b9c238fa83ec628ce9dc174..db5bd911213238800c84207798b84a1546130061 100644 (file)
--- a/techlibs/greenpak4/cells_sim_digital.v
+++ b/techlibs/greenpak4/cells_sim_digital.v
@@ -15,7 +15,13 @@ module GP_3LUT(input IN0, IN1, IN2, output OUT);
        assign OUT = INIT[{IN2, IN1, IN0}];
 endmodule
 
-module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
+module GP_4LUT(
+       input wire IN0,
+       input wire IN1,
+       input wire IN2,
+       input wire IN3,
+       output wire OUT);
+
        parameter [15:0] INIT = 0;
        assign OUT = INIT[{IN3, IN2, IN1, IN0}];
 endmodule
@@ -24,6 +30,74 @@ module GP_CLKBUF(input wire IN, output wire OUT);
        assign OUT = IN;
 endmodule
 
+module GP_COUNT8(
+       input wire CLK,
+       input wire RST,
+       output reg OUT,
+       output reg[7:0] POUT);
+
+       parameter RESET_MODE    = "RISING";
+
+       parameter COUNT_TO              = 8'h1;
+       parameter CLKIN_DIVIDE  = 1;
+
+       reg[7:0] count = COUNT_TO;
+
+       //Combinatorially output underflow flag whenever we wrap low
+       always @(*) begin
+               OUT <= (count == 8'h0);
+               OUT <= count;
+       end
+
+       //POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
+       //Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
+       generate
+               case(RESET_MODE)
+
+                       "RISING": begin
+                               always @(posedge CLK or posedge RST) begin
+                                       count           <= count - 1'd1;
+                                       if(count == 0)
+                                               count   <= COUNT_TO;
+
+                                       if(RST)
+                                               count   <= COUNT_0;
+                               end
+                       end
+
+                       "FALLING": begin
+                               always @(posedge CLK or negedge RST) begin
+                                       count           <= count - 1'd1;
+                                       if(count == 0)
+                                               count   <= COUNT_TO;
+
+                                       if(!RST)
+                                               count   <= COUNT_0;
+                               end
+                       end
+
+                       "BOTH": begin
+                               initial begin
+                                       $display("Both-edge reset mode for GP_COUNT8 not implemented");
+                                       $finish;
+                               end
+                       end
+
+                       "LEVEL": begin
+                       end
+
+                       default: begin
+                               initial begin
+                                       $display("Invalid RESET_MODE on GP_COUNT8");
+                                       $finish;
+                               end
+                       end
+
+               endcase
+       endgenerate
+
+endmodule
+
 module GP_DCMPREF(output reg[7:0]OUT);
        parameter[7:0] REF_VAL = 8'h00;
        initial OUT = REF_VAL;