Signed-off-by: Clifford Wolf <clifford@clifford.at>
--- /dev/null
+/example.edn
+/work
--- /dev/null
+module top (
+ input clk,
+ output LED1,
+ output LED2,
+ output LED3,
+ output LED4,
+ output LED5
+);
+
+ localparam BITS = 5;
+ localparam LOG2DELAY = 22;
+
+ reg [BITS+LOG2DELAY-1:0] counter = 0;
+ reg [BITS-1:0] outcnt;
+
+ always @(posedge clk) begin
+ counter <= counter + 1;
+ outcnt <= counter >> LOG2DELAY;
+ end
+
+ assign {LED1, LED2, LED3, LED4, LED5} = outcnt ^ (outcnt >> 1);
+endmodule
--- /dev/null
+read_verilog example.v
+synth_sf2 -top top -edif example.edn
--- /dev/null
+#!/bin/bash
+set -ex
+rm -rf work
+LM_LICENSE_FILE=1702@`hostname` /opt/microsemi/Libero_SoC_v11.9/Libero/bin/libero SCRIPT:libero.tcl
--- /dev/null
+# Run with "libero SCRIPT:libero.tcl"
+
+new_project \
+ -name top \
+ -location work \
+ -family IGLOO2 \
+ -die PA4MGL500 \
+ -package tq144 \
+ -speed -1 \
+ -hdl VERILOG
+
+import_files -edif {example.edn}
+run_tool –name {COMPILE}
+run_tool –name {PLACEROUTEN}