re PR rtl-optimization/8812 ([avr] Registers allocated for two uses at once)

PR target/8812
* reload1.c (choose_reload_regs): For equiv reg, add loop over all
hard regs for reload_reg_used_at_all and reg_class_contents checks.

From-SVN: r67751

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 50359950355cc8f9b4a55c5339d318bc2dbbbbf3..2fcaf5a7275a9f21a24188d979bdec29d7190683 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2003-06-10  James E Wilson  <wilson@tuliptree.org>
+
+       PR target/8812
+       * reload1.c (choose_reload_regs): For equiv reg, add loop over all
+       hard regs for reload_reg_used_at_all and reg_class_contents checks.
+
 2003-06-10  Kazu Hirata  <kazu@cs.umass.edu>
 
        * config/h8300/h8300.c (print_operand): Remove support for

diff --git a/gcc/reload1.c b/gcc/reload1.c
index 79ce9a1e809b881c103d39313fa3d5e2f719cc89..f8b3d5aef3497722393911b561c2eb577800a025 100644 (file)
--- a/gcc/reload1.c
+++ b/gcc/reload1.c
@@ -5685,14 +5685,27 @@ choose_reload_regs (chain)
 
              /* If we found a spill reg, reject it unless it is free
                 and of the desired class.  */
-             if (equiv != 0
-                 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)
+             if (equiv != 0)
+               {
+                 int regs_used = 0;
+                 int bad_for_class = 0;
+                 int max_regno = regno + rld[r].nregs;
+
+                 for (i = regno; i < max_regno; i++)
+                   {
+                     regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
+                                                     i);
+                     bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class], 
+                                                          i);
+                   }
+
+                 if ((regs_used
                       && ! free_for_value_p (regno, rld[r].mode,
                                              rld[r].opnum, rld[r].when_needed,
                                              rld[r].in, rld[r].out, r, 1))
-                     || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
-                                             regno)))
-               equiv = 0;
+                     || bad_for_class)
+                   equiv = 0;
+               }
 
              if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
                equiv = 0;