+2002-08-22 Nick Clifton <nickc@redhat.com>
+
+ * gas/arm/arch5tej.s: Add nops to align output.
+ * gas/arm/arch5tej.d: Expect nops.
+ * gas/arm/arm7t.s: Add nops, remove thumb instructions.
+ * gas/arm/arm7t.d: Expect nops.
+ * gas/arm/armv1.s: Add nops.
+ * gas/arm/armv1.d: Expect nops.
+ * gas/arm/fpa-mem.s: Add nops.
+ * gas/arm/fpa-mem.d: Expext nops.
+ * gas/arm/vfp1.s: Add nops.
+ * gas/arm/vfp1.d: Expect nops.
+ * gas/arm/xscale.s: Add nops.
+ * gas/arm/xscale.d: Expect nops.
+ * gas/arm/arm.exp: Do not run thumb tests for arm-aout
+ toolchain.
+
2002-08-22 Alan Modra <amodra@bigpond.net.au>
* gas/ppc/ppc.exp: Don't run e500 test on xcoff targets.
0+0c <[^>]*> 012fff20 ? bxjeq r0
0+10 <[^>]*> 412fff20 ? bxjmi r0
0+14 <[^>]*> 512fff27 ? bxjpl r7
+0+18 <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\)
+0+1c <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\)
bxjeq r0
bxjmi r0
bxjpl r7
+
+ # Add two nop instructions to ensure that the output
+ # is aligned as will automatically be done for arm-aout.
+ nop
+ nop
run_dump_test "arm7t"
- gas_test "thumb.s" "-mcpu=arm7t" $stdoptlist "Thumb instructions"
+ if {! [istarget arm*-*-aout]} then {
+ # The arm-aout port does not support Thumb mode.
+ gas_test "thumb.s" "-mcpu=arm7t" $stdoptlist "Thumb instructions"
+ }
gas_test "arch4t.s" "-march=armv4t" $stdoptlist "Arm architecture 4t instructions"
[ ]*dc:.*fred
0+e0 <[^>]*> 0000c0de ? .*
0+e4 <[^>]*> 0000dead ? .*
-0+e8 <[^>]*> 3800 sub r0, #0
-0+ea <[^>]*> 3000 add r0, #0
+0+e8 <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\)
+0+ec <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\)
.word fred
.ltorg
- .thumb
- .global thumb_tests
- .thumb_func
-thumb_tests:
- sub r0, #0
- add r0, #0
+
+ # Add two nop instructions to ensure that the
+ # output is 32-byte aligned as required for arm-aout.
+ nop
+ nop
0+e8 <[^>]*> e8100001 ? ldmda r0, {r0}
0+ec <[^>]*> e9100001 ? ldmdb r0, {r0}
0+f0 <[^>]*> e9900001 ? ldmib r0, {r0}
+0+f4 <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\)
+0+f8 <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\)
+0+fc <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\)
ldmfa r0, {r0}
ldmea r0, {r0}
ldmed r0, {r0}
+
+ # Add three nop instructions to ensure that the
+ # output is 32-byte aligned as required for arm-aout.
+ nop
+ nop
+ nop
0+4c <[^>]*> ed800200 ? sfm f0, 4, \[r0\]
0+50 <[^>]*> ed00020c ? sfm f0, 4, \[r0, -#48\]
0+54 <[^>]*> ed800200 ? sfm f0, 4, \[r0\]
+0+58 <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\)
+0+5c <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\)
sfm f0, 4, [r0]
sfmfd f0, 4, [r0]
sfmea f0, 4, [r0]
+
+ # Add two nop instructions to ensure that the
+ # output is 32-byte aligned as required for arm-aout.
+ nop
+ nop
0+2c8 <[^>]*> 0e1f7b10 fmrdleq r7, d15
0+2cc <[^>]*> 0e21fb10 fmdhreq d1, pc
0+2d0 <[^>]*> 0e0f1b10 fmdlreq d15, r1
+0+2d4 <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\)
+0+2d8 <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\)
+0+2dc <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\)
fmdhreq d1, r15
fmdlreq d15, r1
+
+ # Add three nop instructions to ensure that the
+ # output is 32-byte aligned as required for arm-aout.
+ nop
+ nop
+ nop
0+5c <[^>]*> e5910000 ldr r0, \[r1\]
0+60 <[^>]*> e5832000 str r2, \[r3\]
0+64 <[^>]*> e321f011 msr CPSR_c, #17 ; 0x11
+0+68 <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\)
+0+6c <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\)
str r2, [r3]
msr cpsr_ctl, #0x11
+
+ # Add two nop instructions to ensure that the
+ # output is 32-byte aligned as required for arm-aout.
+ nop
+ nop