add spi interface page

diff --git a/shakti/m_class.mdwn b/shakti/m_class.mdwn
index 2e4e9a072d197111c5e90c8715cb5d724b894655..2aff73f3e2338506e6a86150f689800470787d80 100644 (file)
--- a/shakti/m_class.mdwn
+++ b/shakti/m_class.mdwn
@@ -229,9 +229,7 @@ At its own page [[RGBTTL]]
 
 ## SPI
 
-* APB to SPI <https://opencores.org/project,apb2spi>
-* ASIC-proven <https://opencores.org/project,spi_master_slave>
-* Wishbone-compliant <https://opencores.org/project,simple_spi>
+At its own page [[SPI]]
 
 ## SD/MMC (including eMMC)
 

diff --git a/shakti/m_class/SPI.mdwn b/shakti/m_class/SPI.mdwn
new file mode 100644 (file)
index 0000000..f9d82cf
--- /dev/null
+++ b/shakti/m_class/SPI.mdwn
@@ -0,0 +1,11 @@
+# SPI
+
+* <http://bugs.libre-riscv.org/show_bug.cgi?id=6>
+* Optional 4-wire SPI NAND/NOR for boot (XIP - Execute In-place - recommended).
+* <https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/>
+  includes GPIO, SPI, UART, JTAG, I2C, PinCtrl, UART and PWM.  Also included
+  is a Watchdog Timer and others.
+* APB to SPI <https://opencores.org/project,apb2spi>
+* ASIC-proven <https://opencores.org/project,spi_master_slave>
+* Wishbone-compliant <https://opencores.org/project,simple_spi>
+