(no commit message)

diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index 84390476e081912ef79520fd2c9a7fcff735f823..bcd5a3be1bac9d82b932d040e6f2ec4552a13c00 100644 (file)
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -93,7 +93,6 @@ Fields:
   a CR bit and whether it is set (inv=0) or unset (inv=1)
 * **RG** Reverse-Gear: inverts the Vector Loop order (VL-1 downto 0) rather
   than the normal 0 upto VL-1
-* **SVM** sets "subvector" reduce mode
 * **VLi** VL inclusive: in fail-first mode, the truncation of
   VL *includes* the current element at the failure point rather
   than excludes it from the count.