Tell checker that an instruction is completed prior once it does the access to memory...

src/cpu/o3/lsq_unit_impl.hh:
    Tell checker that an instruction is completed prior once it does the access to memory.

--HG--
extra : convert_revision : 1d4bbac4b35fbd355f300eab76f29b38b5bc88cb

diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 083217d26c72955300dfc399e42b8a1d7e97a135..62bb96610d7b71f294caf12072dd7fcf7b1b9d41 100644 (file)
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -633,6 +633,14 @@ LSQUnit<Impl>::writebackStores()
                 assert(!storeQueue[storeWBIdx].inst->isStoreConditional());
                 // Non-store conditionals do not need a writeback.
                 state->noWB = true;
+
+                // The store is basically completed at this time. This
+                // only works so long as the checker doesn't try to
+                // verify the value in memory for stores.
+                storeQueue[storeWBIdx].inst->setCompleted();
+                if (cpu->checker) {
+                    cpu->checker->tick(storeQueue[storeWBIdx].inst);
+                }
             }
 
             if (data_pkt->result != Packet::Success) {