have to now add LD/ST-update instructions to list of explicit-allowed

(as .long) due to extension of RA/RT with EXTRAs, the test RA!=RT is not
a 5-bit test it is a 7-bit test

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index da25bd1e4caa46cbbdb3726a3956727ca58c4b81..5d8498857e7ee95b1f621f25cbc8f05d14694236 100644 (file)
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -44,6 +44,9 @@ from openpower.fpscr import FPSCRState
 from openpower.xer import XERState
 from openpower.util import LogKind, log
 
+LDST_UPDATE_INSNS = ['ldu', 'lwzu', 'lbzu', 'lhzu', 'lhau', 'lfsu', 'lfdu',
+                    ]
+
 instruction_info = namedtuple('instruction_info',
                               'func read_regs uninit_regs write_regs ' +
                               'special_regs op_fields form asmregs')
@@ -1931,6 +1934,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
         # list of instructions not being supported by binutils (.long)
         dotstrp = asmop[:-1] if asmop[-1] == '.' else asmop
         if dotstrp in [*FPTRANS_INSNS,
+                       *LDST_UPDATE_INSNS,
                        'ffmadds', 'fdmadds', 'ffadds',
                        'minmax',
                        'setvl', 'svindex', 'svremap', 'svstep',