type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm
+boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
+dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
+exit_on_work_items=false
flags_addr=469827632
gic_cpu_addr=738205696
have_large_asid_64=false
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
+readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/work/gem5/dist/disks/linux-aarch32-ael.img
+image_file=/home/stever/m5/aarch-system-2014-10/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=false
hit_latency=1
is_read_only=true
max_miss_count=0
clusivity=mostly_excl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=12
is_read_only=false
max_miss_count=0
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.cpu0.toL2Bus.snoop_filter
snoop_response_latency=1
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=false
hit_latency=1
is_read_only=true
max_miss_count=0
clusivity=mostly_excl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=12
is_read_only=false
max_miss_count=0
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.cpu1.toL2Bus.snoop_filter
snoop_response_latency=1
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=false
hit_latency=50
is_read_only=false
max_miss_count=0
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.toL2Bus.snoop_filter
snoop_response_latency=1
+Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual/simout
+Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 4 2015 11:13:17
-gem5 started Dec 4 2015 12:40:05
-gem5 executing on e104799-lin, pid 5560
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual
+gem5 compiled Mar 15 2016 21:26:42
+gem5 started Mar 15 2016 21:34:30
+gem5 executing on phenom, pid 15961
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+info: kernel located at: /home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80008000
-info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
+info: Loading DTB file: /home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-Exiting @ tick 2848979128500 because m5_exit instruction encountered
+Exiting @ tick 2649116242500 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 2.848869 # Number of seconds simulated
-sim_ticks 2848869082500 # Number of ticks simulated
-final_tick 2848869082500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.649116 # Number of seconds simulated
+sim_ticks 2649116242500 # Number of ticks simulated
+final_tick 2649116242500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 198569 # Simulator instruction rate (inst/s)
-host_op_rate 240456 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 4442491449 # Simulator tick rate (ticks/s)
-host_mem_usage 621364 # Number of bytes of host memory used
-host_seconds 641.28 # Real time elapsed on the host
-sim_insts 127338052 # Number of instructions simulated
-sim_ops 154199103 # Number of ops (including micro ops) simulated
+host_inst_rate 120147 # Simulator instruction rate (inst/s)
+host_op_rate 145490 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2497044812 # Simulator tick rate (ticks/s)
+host_mem_usage 602856 # Number of bytes of host memory used
+host_seconds 1060.90 # Real time elapsed on the host
+sim_insts 127464482 # Number of instructions simulated
+sim_ops 154350851 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker 8704 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker 7744 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 1697856 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 1350060 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher 8564736 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 768 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 206784 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 630484 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher 333888 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 1526336 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 1246188 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher 8224576 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 2560 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 394816 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 723292 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher 617536 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 12794304 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 1697856 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 206784 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1904640 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 8859904 # Number of bytes written to this memory
+system.physmem.bytes_read::total 12744072 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 1526336 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 394816 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1921152 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 8953600 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
-system.physmem.bytes_written::total 8877468 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker 136 # Number of read requests responded to by this memory
+system.physmem.bytes_written::total 8971164 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker 121 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 26529 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 21616 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher 133824 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 12 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 3231 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 9872 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher 5217 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 23849 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 19993 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher 128509 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 40 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 6169 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 11324 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher 9649 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 200453 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 138436 # Number of write requests responded to by this memory
+system.physmem.num_reads::total 199670 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 139900 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 142827 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker 3055 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 595975 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 473893 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher 3006363 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 270 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 72585 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 221310 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher 117200 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 4491012 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 595975 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 72585 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 668560 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 3109972 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 6151 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 3116138 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 3109972 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 3055 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 595975 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 480045 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher 3006363 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 270 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 72585 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 221324 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher 117200 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 7607149 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 200453 # Number of read requests accepted
-system.physmem.writeReqs 142827 # Number of write requests accepted
-system.physmem.readBursts 200453 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 142827 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 12818368 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 10624 # Total number of bytes read from write queue
-system.physmem.bytesWritten 8890624 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 12794304 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 8877468 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 166 # Number of DRAM read bursts serviced by the write queue
+system.physmem.num_writes::total 144291 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker 2923 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 24 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 576168 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 470417 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher 3104649 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 966 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 149037 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 273031 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher 233110 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide 362 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 4810688 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 576168 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 149037 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 725205 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 3379844 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 6615 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 15 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 3386474 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 3379844 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 2923 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 24 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 576168 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 477032 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher 3104649 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 966 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 149037 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 273047 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher 233110 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 362 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 8197162 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 199670 # Number of read requests accepted
+system.physmem.writeReqs 144291 # Number of write requests accepted
+system.physmem.readBursts 199670 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 144291 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 12768704 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 10176 # Total number of bytes read from write queue
+system.physmem.bytesWritten 8984192 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 12744072 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 8971164 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 159 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 3895 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 12269 # Per bank write bursts
-system.physmem.perBankRdBursts::1 12614 # Per bank write bursts
-system.physmem.perBankRdBursts::2 13475 # Per bank write bursts
-system.physmem.perBankRdBursts::3 12831 # Per bank write bursts
-system.physmem.perBankRdBursts::4 15664 # Per bank write bursts
-system.physmem.perBankRdBursts::5 12720 # Per bank write bursts
-system.physmem.perBankRdBursts::6 12662 # Per bank write bursts
-system.physmem.perBankRdBursts::7 12956 # Per bank write bursts
-system.physmem.perBankRdBursts::8 12071 # Per bank write bursts
-system.physmem.perBankRdBursts::9 12246 # Per bank write bursts
-system.physmem.perBankRdBursts::10 11615 # Per bank write bursts
-system.physmem.perBankRdBursts::11 10653 # Per bank write bursts
-system.physmem.perBankRdBursts::12 11883 # Per bank write bursts
-system.physmem.perBankRdBursts::13 12836 # Per bank write bursts
-system.physmem.perBankRdBursts::14 12055 # Per bank write bursts
-system.physmem.perBankRdBursts::15 11737 # Per bank write bursts
-system.physmem.perBankWrBursts::0 8758 # Per bank write bursts
-system.physmem.perBankWrBursts::1 9183 # Per bank write bursts
-system.physmem.perBankWrBursts::2 9791 # Per bank write bursts
-system.physmem.perBankWrBursts::3 9102 # Per bank write bursts
-system.physmem.perBankWrBursts::4 8279 # Per bank write bursts
-system.physmem.perBankWrBursts::5 8882 # Per bank write bursts
-system.physmem.perBankWrBursts::6 8907 # Per bank write bursts
-system.physmem.perBankWrBursts::7 8993 # Per bank write bursts
-system.physmem.perBankWrBursts::8 8509 # Per bank write bursts
-system.physmem.perBankWrBursts::9 8693 # Per bank write bursts
-system.physmem.perBankWrBursts::10 8248 # Per bank write bursts
-system.physmem.perBankWrBursts::11 7749 # Per bank write bursts
-system.physmem.perBankWrBursts::12 8519 # Per bank write bursts
-system.physmem.perBankWrBursts::13 8825 # Per bank write bursts
-system.physmem.perBankWrBursts::14 8545 # Per bank write bursts
-system.physmem.perBankWrBursts::15 7933 # Per bank write bursts
+system.physmem.perBankRdBursts::0 12456 # Per bank write bursts
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+system.physmem.perBankRdBursts::2 13452 # Per bank write bursts
+system.physmem.perBankRdBursts::3 12663 # Per bank write bursts
+system.physmem.perBankRdBursts::4 15992 # Per bank write bursts
+system.physmem.perBankRdBursts::5 12602 # Per bank write bursts
+system.physmem.perBankRdBursts::6 12853 # Per bank write bursts
+system.physmem.perBankRdBursts::7 13005 # Per bank write bursts
+system.physmem.perBankRdBursts::8 12164 # Per bank write bursts
+system.physmem.perBankRdBursts::9 12306 # Per bank write bursts
+system.physmem.perBankRdBursts::10 11290 # Per bank write bursts
+system.physmem.perBankRdBursts::11 10778 # Per bank write bursts
+system.physmem.perBankRdBursts::12 11668 # Per bank write bursts
+system.physmem.perBankRdBursts::13 12164 # Per bank write bursts
+system.physmem.perBankRdBursts::14 11811 # Per bank write bursts
+system.physmem.perBankRdBursts::15 11400 # Per bank write bursts
+system.physmem.perBankWrBursts::0 8970 # Per bank write bursts
+system.physmem.perBankWrBursts::1 9418 # Per bank write bursts
+system.physmem.perBankWrBursts::2 9818 # Per bank write bursts
+system.physmem.perBankWrBursts::3 9016 # Per bank write bursts
+system.physmem.perBankWrBursts::4 8619 # Per bank write bursts
+system.physmem.perBankWrBursts::5 8911 # Per bank write bursts
+system.physmem.perBankWrBursts::6 9199 # Per bank write bursts
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-system.physmem.bytesPerActivate::mean 234.543816 # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::256-383 6295 6.80% 80.62% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::768-895 907 0.98% 90.02% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::1024-1151 8215 8.88% 100.00% # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes
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-system.physmem.wrPerTurnAround::stdev 13.439026 # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::24-27 79 1.17% 91.80% # Writes before turning the bus around for reads
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 45756.47 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 4.50 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 3.12 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 4.49 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 3.12 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 45891.17 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 4.82 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 3.39 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 4.81 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 3.39 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.06 # Data bus utilization in percentage
system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 25.87 # Average write queue length when enqueuing
-system.physmem.readRowHits 166261 # Number of row buffer hits during reads
-system.physmem.writeRowHits 80380 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 83.01 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 57.86 # Row buffer hit rate for writes
-system.physmem.avgGap 8298964.51 # Average gap between requests
-system.physmem.pageHitRate 72.71 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 368829720 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 201246375 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 820489800 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 465801840 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 186073967040 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 85113851220 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 1634657451750 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 1907701637745 # Total energy per rank (pJ)
-system.physmem_0.averagePower 669.635783 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 2719265528725 # Time in different power states
-system.physmem_0.memoryStateTime::REF 95129840000 # Time in different power states
+system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 25.22 # Average write queue length when enqueuing
+system.physmem.readRowHits 165357 # Number of row buffer hits during reads
+system.physmem.writeRowHits 80567 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 82.88 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 57.39 # Row buffer hit rate for writes
+system.physmem.avgGap 7701790.94 # Average gap between requests
+system.physmem.pageHitRate 72.35 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 377130600 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 205775625 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 826254000 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 473461200 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 173027368800 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 81211791960 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 1518231236250 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 1774353018435 # Total energy per rank (pJ)
+system.physmem_0.averagePower 669.790588 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 2525572951341 # Time in different power states
+system.physmem_0.memoryStateTime::REF 88459800000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 34469380775 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 35083346159 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 330840720 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 180518250 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 741741000 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 434257200 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 186073967040 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 83792356380 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 1635816657750 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 1907370338340 # Total energy per rank (pJ)
-system.physmem_1.averagePower 669.519491 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 2721199868682 # Time in different power states
-system.physmem_1.memoryStateTime::REF 95129840000 # Time in different power states
+system.physmem_1.actEnergy 333237240 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 181825875 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 729924000 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 436188240 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 173027368800 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 79517209320 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 1519717712250 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 1773943465725 # Total energy per rank (pJ)
+system.physmem_1.averagePower 669.635988 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 2528054644365 # Time in different power states
+system.physmem_1.memoryStateTime::REF 88459800000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 32535082068 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 32601653135 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 512 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 832 # Number of bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 13 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 21 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 180 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst 292 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 472 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 180 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst 292 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 472 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 180 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst 292 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 472 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu0.inst 193 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst 314 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 507 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 193 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst 314 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 507 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 193 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst 314 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 507 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
-system.cpu0.branchPred.lookups 36420174 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 17682232 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 1669191 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 20721489 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 15026104 # Number of BTB hits
+system.cpu0.branchPred.lookups 19632721 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 12741106 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 957809 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 12414007 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 8826841 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 72.514596 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 11397312 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 800928 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 71.103883 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 3283973 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 196273 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.walks 73306 # Table walker walks requested
-system.cpu0.dtb.walker.walksShort 73306 # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 47488 # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 25818 # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walkWaitTime::samples 73306 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0 73306 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 73306 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples 7529 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 12317.505645 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 11403.047410 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 7148.063589 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-32767 7474 99.27% 99.27% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::32768-65535 46 0.61% 99.88% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-163839 7 0.09% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::163840-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total 7529 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walks 67362 # Table walker walks requested
+system.cpu0.dtb.walker.walksShort 67362 # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 44747 # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 22615 # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walkWaitTime::samples 67362 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0 67362 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total 67362 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples 6703 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 11941.220349 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 10822.969980 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 8452.619900 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-32767 6653 99.25% 99.25% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::32768-65535 41 0.61% 99.87% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-163839 8 0.12% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-425983 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total 6703 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 581987000 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0 581987000 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 581987000 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 5847 77.66% 77.66% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M 1682 22.34% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 7529 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 73306 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkPageSizes::4K 5190 77.43% 77.43% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M 1513 22.57% 100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total 6703 # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 67362 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 73306 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7529 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 67362 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6703 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7529 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 80835 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6703 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total 74065 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 24946697 # DTB read hits
-system.cpu0.dtb.read_misses 66576 # DTB read misses
-system.cpu0.dtb.write_hits 18555175 # DTB write hits
-system.cpu0.dtb.write_misses 6730 # DTB write misses
+system.cpu0.dtb.read_hits 16471465 # DTB read hits
+system.cpu0.dtb.read_misses 61259 # DTB read misses
+system.cpu0.dtb.write_hits 13861421 # DTB write hits
+system.cpu0.dtb.write_misses 6103 # DTB write misses
system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 3812 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 1386 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 2027 # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries 3499 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 1118 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 1582 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 638 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 25013273 # DTB read accesses
-system.cpu0.dtb.write_accesses 18561905 # DTB write accesses
+system.cpu0.dtb.perms_faults 565 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 16532724 # DTB read accesses
+system.cpu0.dtb.write_accesses 13867524 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 43501872 # DTB hits
-system.cpu0.dtb.misses 73306 # DTB misses
-system.cpu0.dtb.accesses 43575178 # DTB accesses
+system.cpu0.dtb.hits 30332886 # DTB hits
+system.cpu0.dtb.misses 67362 # DTB misses
+system.cpu0.dtb.accesses 30400248 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.walker.walks 4169 # Table walker walks requested
-system.cpu0.itb.walker.walksShort 4169 # Table walker walks initiated with short descriptors
-system.cpu0.itb.walker.walksShortTerminationLevel::Level1 324 # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3845 # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples 4169 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0 4169 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total 4169 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples 2671 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 12688.506177 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 11997.245115 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 5018.704234 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-16383 2423 90.72% 90.72% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::16384-32767 228 8.54% 99.25% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-49151 18 0.67% 99.93% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::49152-65535 1 0.04% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walks 3870 # Table walker walks requested
+system.cpu0.itb.walker.walksShort 3870 # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.walksShortTerminationLevel::Level1 303 # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3567 # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples 3870 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0 3870 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total 3870 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples 2416 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 12175.289735 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 11303.436072 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 5287.236665 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-16383 2213 91.60% 91.60% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::16384-32767 183 7.57% 99.17% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-49151 19 0.79% 99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total 2671 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total 2416 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 581277500 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 581277500 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 581277500 # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K 2352 88.06% 88.06% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::1M 319 11.94% 100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total 2671 # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::4K 2118 87.67% 87.67% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::1M 298 12.33% 100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total 2416 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 4169 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total 4169 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3870 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3870 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2671 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2671 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total 6840 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 71444406 # ITB inst hits
-system.cpu0.itb.inst_misses 4169 # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2416 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2416 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total 6286 # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits 36732226 # ITB inst hits
+system.cpu0.itb.inst_misses 3870 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 2449 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries 2219 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 8126 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 7242 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 71448575 # ITB inst accesses
-system.cpu0.itb.hits 71444406 # DTB hits
-system.cpu0.itb.misses 4169 # DTB misses
-system.cpu0.itb.accesses 71448575 # DTB accesses
-system.cpu0.numCycles 248815256 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 36736096 # ITB inst accesses
+system.cpu0.itb.hits 36732226 # DTB hits
+system.cpu0.itb.misses 3870 # DTB misses
+system.cpu0.itb.accesses 36736096 # DTB accesses
+system.cpu0.numCycles 162382442 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 113230333 # Number of instructions committed
-system.cpu0.committedOps 136910947 # Number of ops (including micro ops) committed
-system.cpu0.discardedOps 8928789 # Number of ops (including micro ops) which were discarded before commit
-system.cpu0.numFetchSuspends 1886 # Number of times Execute suspended instruction fetching
-system.cpu0.quiesceCycles 5448949721 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.cpi 2.197426 # CPI: cycles per instruction
-system.cpu0.ipc 0.455078 # IPC: instructions per cycle
+system.cpu0.committedInsts 75583432 # Number of instructions committed
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+system.cpu0.discardedOps 5013155 # Number of ops (including micro ops) which were discarded before commit
+system.cpu0.numFetchSuspends 2059 # Number of times Execute suspended instruction fetching
+system.cpu0.quiesceCycles 5135888904 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.cpi 2.148387 # CPI: cycles per instruction
+system.cpu0.ipc 0.465466 # IPC: instructions per cycle
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 1891 # number of quiesce instructions executed
-system.cpu0.tickCycles 199822657 # Number of cycles that the object actually ticked
-system.cpu0.idleCycles 48992599 # Total number of cycles that the object has spent stopped
-system.cpu0.dcache.tags.replacements 758548 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 499.039628 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 41909246 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 759060 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 55.212033 # Average number of references to valid blocks.
+system.cpu0.kern.inst.quiesce 2063 # number of quiesce instructions executed
+system.cpu0.tickCycles 121978989 # Number of cycles that the object actually ticked
+system.cpu0.idleCycles 40403453 # Total number of cycles that the object has spent stopped
+system.cpu0.dcache.tags.replacements 680701 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 486.682235 # Cycle average of tags in use
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+system.cpu0.dcache.tags.avg_refs 42.426931 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 600550000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 499.039628 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.974687 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.974687 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 486.682235 # Average occupied blocks per requestor
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system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id
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+system.cpu0.dcache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 86968977 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 86968977 # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data 23338731 # number of ReadReq hits
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-system.cpu0.dcache.WriteReq_hits::cpu0.data 17382396 # number of WriteReq hits
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-system.cpu0.dcache.SoftPFReq_hits::total 329314 # number of SoftPFReq hits
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-system.cpu0.dcache.LoadLockedReq_hits::total 374886 # number of LoadLockedReq hits
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-system.cpu0.dcache.StoreCondReq_hits::total 370842 # number of StoreCondReq hits
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-system.cpu0.dcache.ReadReq_misses::total 492920 # number of ReadReq misses
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-system.cpu0.dcache.SoftPFReq_misses::total 141961 # number of SoftPFReq misses
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-system.cpu0.dcache.LoadLockedReq_misses::total 21406 # number of LoadLockedReq misses
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-system.cpu0.dcache.overall_misses::total 1239685 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6985498500 # number of ReadReq miss cycles
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-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 26250.890200 # average StoreCondReq miss latency
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+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 26680.894214 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
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-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15772.420413 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 15772.420413 # average overall miss latency
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+system.cpu0.dcache.overall_avg_miss_latency::total 16061.222547 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 758548 # number of writebacks
-system.cpu0.dcache.writebacks::total 758548 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 75935 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 75935 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 266250 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 266250 # number of WriteReq MSHR hits
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-system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14874 # number of LoadLockedReq MSHR hits
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-system.cpu0.dcache.overall_mshr_hits::total 342185 # number of overall MSHR hits
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-system.cpu0.dcache.ReadReq_mshr_misses::total 416985 # number of ReadReq MSHR misses
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-system.cpu0.dcache.WriteReq_mshr_misses::total 338554 # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 108405 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total 108405 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6532 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6532 # number of LoadLockedReq MSHR misses
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-system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32039 # number of ReadReq MSHR uncacheable
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-system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28722 # number of WriteReq MSHR uncacheable
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-system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60761 # number of overall MSHR uncacheable misses
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-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1810098500 # number of SoftPFReq MSHR miss cycles
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-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 104404500 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 517681500 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 517681500 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 995000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 995000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12403434500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 12403434500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 14213533000 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 14213533000 # number of overall MSHR miss cycles
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-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6701732000 # number of ReadReq MSHR uncacheable cycles
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-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5452636000 # number of WriteReq MSHR uncacheable cycles
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-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12154368000 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017497 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017497 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018822 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018822 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.230025 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.230025 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016483 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016483 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052386 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052386 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018067 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.018067 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020429 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.020429 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12686.046261 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12686.046261 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 21011.547641 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 21011.547641 # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16697.555463 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16697.555463 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15983.542560 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15983.542560 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 25251.524316 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 25251.524316 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 680701 # number of writebacks
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+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14844 # number of LoadLockedReq MSHR hits
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+system.cpu0.dcache.overall_mshr_hits::total 315140 # number of overall MSHR hits
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+system.cpu0.dcache.StoreCondReq_mshr_misses::total 21449 # number of StoreCondReq MSHR misses
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+system.cpu0.dcache.ReadReq_mshr_uncacheable::total 17966 # number of ReadReq MSHR uncacheable
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+system.cpu0.dcache.WriteReq_mshr_uncacheable::total 16715 # number of WriteReq MSHR uncacheable
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+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7043871000 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024188 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024188 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023531 # mshr miss rate for WriteReq accesses
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+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016120 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016120 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.057454 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.057454 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023883 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.023883 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026926 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.026926 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12852.610691 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12852.610691 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 21375.951888 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 21375.951888 # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 17194.972922 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17194.972922 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15930.366234 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15930.366234 # average LoadLockedReq mshr miss latency
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+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 25681.360436 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16416.670086 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16416.670086 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16451.914707 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16451.914707 # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209174.193951 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209174.193951 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189841.793747 # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189841.793747 # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 200035.680782 # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 200035.680782 # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16744.861599 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16744.861599 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16801.706165 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16801.706165 # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 220675.442503 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220675.442503 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 184218.725695 # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184218.725695 # average WriteReq mshr uncacheable latency
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+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 203104.610594 # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements 2044571 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.728044 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 69390799 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 2045083 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 33.930554 # Average number of references to valid blocks.
+system.cpu0.icache.tags.replacements 1875262 # number of replacements
+system.cpu0.icache.tags.tagsinuse 511.707229 # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs 34848846 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 1875774 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 18.578382 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 6975539000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.728044 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999469 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.999469 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.707229 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999428 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total 0.999428 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 103 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2 109 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 144916894 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 144916894 # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst 69390799 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 69390799 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 69390799 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 69390799 # number of demand (read+write) hits
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-system.cpu0.icache.overall_hits::total 69390799 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 2045099 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 2045099 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 2045099 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 2045099 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 2045099 # number of overall misses
-system.cpu0.icache.overall_misses::total 2045099 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 20582559000 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 20582559000 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 20582559000 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 20582559000 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 20582559000 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 20582559000 # number of overall miss cycles
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-system.cpu0.icache.ReadReq_accesses::total 71435898 # number of ReadReq accesses(hits+misses)
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-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10064.333805 # average overall miss latency
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system.cpu0.icache.ReadReq_mshr_uncacheable::total 3917 # number of ReadReq MSHR uncacheable
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system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 557356500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 557356500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 557356500 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 557356500 # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028628 # mshr miss rate for ReadReq accesses
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-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9564.334049 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9564.334049 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9564.334049 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 9564.334049 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9564.334049 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 9564.334049 # average overall mshr miss latency
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+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9485.182800 # average overall mshr miss latency
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system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 142291.677304 # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 142291.677304 # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 142291.677304 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 142291.677304 # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.l2cache.prefetcher.num_hwpf_issued 1927519 # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified 1927689 # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit 149 # number of redundant prefetches already in prefetch queue
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+system.cpu0.l2cache.prefetcher.pfIdentified 1759695 # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.pfBufferHit 108 # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage 245495 # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.replacements 305066 # number of replacements
-system.cpu0.l2cache.tags.tagsinuse 16110.532476 # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs 4906564 # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs 321213 # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs 15.275110 # Average number of references to valid blocks.
+system.cpu0.l2cache.prefetcher.pfSpanPage 223393 # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.replacements 281012 # number of replacements
+system.cpu0.l2cache.tags.tagsinuse 16001.828165 # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs 4472083 # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs 297133 # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs 15.050779 # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks 14727.121799 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 58.543151 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.067969 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1324.799556 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks 0.898872 # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003573 # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_blocks::writebacks 15118.800161 # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 44.428887 # Average occupied blocks per requestor
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+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 838.528425 # Average occupied blocks per requestor
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system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy
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-system.cpu0.l2cache.tags.occ_percent::total 0.983309 # Average percentage of cache occupancy
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-system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15166 # Occupied blocks per task id
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-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 324 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 411 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 226 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 3 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 363 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4092 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 8366 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2250 # Occupied blocks per task id
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-system.cpu0.l2cache.WritebackDirty_hits::total 507120 # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackClean_hits::writebacks 2250930 # number of WritebackClean hits
-system.cpu0.l2cache.WritebackClean_hits::total 2250930 # number of WritebackClean hits
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-system.cpu0.l2cache.ReadCleanReq_hits::total 1975273 # number of ReadCleanReq hits
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-system.cpu0.l2cache.overall_hits::cpu0.inst 1975273 # number of overall hits
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-system.cpu0.l2cache.UpgradeReq_misses::total 57038 # number of UpgradeReq misses
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-system.cpu0.l2cache.UpgradeReq_miss_latency::total 207057500 # number of UpgradeReq miss cycles
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+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6774093500 # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7300113500 # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.009588 # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.023154 # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.010369 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.150881 # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.150881 # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.034109 # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.034109 # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.188585 # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.188585 # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.007986 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.017104 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.034109 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.175536 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total 0.072206 # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.007986 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.017104 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.034109 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.175536 # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.162793 # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.162793 # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.032080 # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.032080 # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.209154 # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.209154 # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.009588 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.023154 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.032080 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.192971 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total 0.075242 # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.009588 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.023154 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.032080 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.192971 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total 0.161419 # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 41370.165746 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18969.696970 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 38675.577157 # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 79986.785842 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 79986.785842 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 26729.206845 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 26729.206845 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17715.195122 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17715.195122 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 897500 # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 897500 # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57576.770958 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57576.770958 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 58591.927576 # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 58591.927576 # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 29095.821954 # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29095.821954 # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 41370.165746 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18969.696970 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 58591.927576 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37568.419587 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44445.898363 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 41370.165746 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18969.696970 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 58591.927576 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37568.419587 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 79986.785842 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 64088.648483 # average overall mshr miss latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total 0.166547 # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 36727.099237 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17288.793103 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 34227.272727 # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 81971.291951 # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 81971.291951 # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 25307.858808 # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25307.858808 # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 18145.521518 # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18145.521518 # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 200999.500000 # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 200999.500000 # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56332.256907 # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56332.256907 # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 59786.314915 # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 59786.314915 # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 27498.028017 # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 27498.028017 # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 36727.099237 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17288.793103 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 59786.314915 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 35989.317324 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 43034.348579 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 36727.099237 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17288.793103 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 59786.314915 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 35989.317324 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 81971.291951 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 64380.460217 # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 134291.549655 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 201169.028372 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 193883.482590 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182323.863241 # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182323.863241 # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 212665.896694 # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 198637.092720 # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 176687.885133 # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176687.885133 # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 134291.549655 # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 192260.833429 # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 188750.123690 # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 195325.783570 # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 189131.910980 # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.toL2Bus.snoop_filter.tot_requests 5762889 # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2904395 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 45067 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops 350664 # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 345809 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4855 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.trans_dist::ReadReq 143133 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp 2769477 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq 28722 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp 28722 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackDirty 745212 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackClean 2295997 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict 245518 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq 331271 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq 87260 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42942 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp 114488 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 6 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 18 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq 300512 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp 297211 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq 2045099 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq 606063 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq 3097 # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 6142602 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2764050 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13802 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 189783 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total 9110237 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 261989504 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 104964478 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 23152 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 362636 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total 367339770 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops 1076533 # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples 4071717 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean 0.104210 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev 0.309410 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_filter.tot_requests 5267322 # Total number of requests made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2655927 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 41328 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.snoop_filter.tot_snoops 334158 # Total number of snoops made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 329304 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4854 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.trans_dist::ReadReq 119336 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp 2522924 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq 16715 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp 16715 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackDirty 692222 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackClean 2091812 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict 222834 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq 309300 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq 91686 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43805 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp 115698 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 12 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq 274549 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp 271267 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1875793 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq 569005 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq 3104 # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 5634681 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2479031 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12447 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 171956 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total 8298115 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 240318144 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 94807159 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 20040 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 327916 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total 335473259 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops 1039321 # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples 3754204 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean 0.107024 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev 0.313298 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0 3652260 89.70% 89.70% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1 414602 10.18% 99.88% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2 4855 0.12% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0 3357269 89.43% 89.43% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1 392081 10.44% 99.87% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2 4854 0.13% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total 4071717 # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy 5772987994 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total 3754204 # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy 5255285493 # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy 116128992 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy 113846370 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy 3074216608 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy 2820178266 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy 1306190305 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy 1169961199 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy 8023481 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy 7446481 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy 99154439 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy 90008437 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu1.branchPred.lookups 3635973 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 2046610 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 209049 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 2276641 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 1455770 # Number of BTB hits
+system.cpu1.branchPred.lookups 20449244 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 7039055 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 963225 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 10410340 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 7679577 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 63.943766 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 756757 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 55280 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 73.768743 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 8836366 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 692168 # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.dtb.walker.walks 23538 # Table walker walks requested
-system.cpu1.dtb.walker.walksShort 23538 # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19270 # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4268 # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walkWaitTime::samples 23538 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0 23538 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total 23538 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples 1839 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 11777.052746 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 10980.884481 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 6685.927584 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-16383 1677 91.19% 91.19% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::16384-32767 150 8.16% 99.35% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-49151 7 0.38% 99.73% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::49152-65535 3 0.16% 99.89% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::147456-163839 2 0.11% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total 1839 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walks 30868 # Table walker walks requested
+system.cpu1.dtb.walker.walksShort 30868 # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 23108 # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7760 # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walkWaitTime::samples 30868 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0 30868 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total 30868 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples 2696 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 11992.210682 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 10915.827455 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 8355.113227 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-16383 2479 91.95% 91.95% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::16384-32767 196 7.27% 99.22% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-49151 12 0.45% 99.67% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::49152-65535 3 0.11% 99.78% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-147455 3 0.11% 99.89% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::147456-163839 3 0.11% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total 2696 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples -1558893032 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0 -1558893032 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total -1558893032 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K 1325 72.05% 72.05% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M 514 27.95% 100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total 1839 # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 23538 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkPageSizes::4K 1974 73.22% 73.22% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M 722 26.78% 100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total 2696 # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 30868 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 23538 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1839 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 30868 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2696 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1839 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total 25377 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2696 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total 33564 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 3603943 # DTB read hits
-system.cpu1.dtb.read_misses 21681 # DTB read misses
-system.cpu1.dtb.write_hits 2994136 # DTB write hits
-system.cpu1.dtb.write_misses 1857 # DTB write misses
+system.cpu1.dtb.read_hits 12117944 # DTB read hits
+system.cpu1.dtb.read_misses 28100 # DTB read misses
+system.cpu1.dtb.write_hits 7719144 # DTB write hits
+system.cpu1.dtb.write_misses 2768 # DTB write misses
system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 1716 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 128 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 253 # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries 2067 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 330 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 545 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 210 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 3625624 # DTB read accesses
-system.cpu1.dtb.write_accesses 2995993 # DTB write accesses
+system.cpu1.dtb.perms_faults 280 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 12146044 # DTB read accesses
+system.cpu1.dtb.write_accesses 7721912 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 6598079 # DTB hits
-system.cpu1.dtb.misses 23538 # DTB misses
-system.cpu1.dtb.accesses 6621617 # DTB accesses
+system.cpu1.dtb.hits 19837088 # DTB hits
+system.cpu1.dtb.misses 30868 # DTB misses
+system.cpu1.dtb.accesses 19867956 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.walker.walks 1941 # Table walker walks requested
-system.cpu1.itb.walker.walksShort 1941 # Table walker walks initiated with short descriptors
-system.cpu1.itb.walker.walksShortTerminationLevel::Level1 151 # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1790 # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples 1941 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0 1941 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total 1941 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples 844 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 11680.687204 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 11150.609492 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 4460.342613 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::4096-8191 146 17.30% 17.30% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::8192-12287 544 64.45% 81.75% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::12288-16383 112 13.27% 95.02% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::16384-20479 21 2.49% 97.51% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::20480-24575 2 0.24% 97.75% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::24576-28671 10 1.18% 98.93% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::28672-32767 1 0.12% 99.05% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-36863 1 0.12% 99.17% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::36864-40959 5 0.59% 99.76% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.12% 99.88% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::57344-61439 1 0.12% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total 844 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walks 2320 # Table walker walks requested
+system.cpu1.itb.walker.walksShort 2320 # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walksShortTerminationLevel::Level1 184 # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2136 # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples 2320 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0 2320 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total 2320 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples 1123 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 12081.032947 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 11456.275098 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 4603.593303 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::4096-8191 188 16.74% 16.74% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::8192-12287 645 57.44% 74.18% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::12288-16383 209 18.61% 92.79% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::16384-20479 49 4.36% 97.15% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::20480-24575 1 0.09% 97.24% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::24576-28671 15 1.34% 98.58% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::28672-32767 3 0.27% 98.84% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-36863 1 0.09% 98.93% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::36864-40959 10 0.89% 99.82% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.09% 99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.09% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total 1123 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples -1559948532 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 -1559948532 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total -1559948532 # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K 705 83.53% 83.53% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::1M 139 16.47% 100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total 844 # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::4K 953 84.86% 84.86% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M 170 15.14% 100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total 1123 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1941 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1941 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2320 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2320 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 844 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total 844 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total 2785 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 6953743 # ITB inst hits
-system.cpu1.itb.inst_misses 1941 # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1123 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1123 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total 3443 # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits 41835871 # ITB inst hits
+system.cpu1.itb.inst_misses 2320 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 908 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 1161 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 1049 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 1837 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 6955684 # ITB inst accesses
-system.cpu1.itb.hits 6953743 # DTB hits
-system.cpu1.itb.misses 1941 # DTB misses
-system.cpu1.itb.accesses 6955684 # DTB accesses
-system.cpu1.numCycles 40734093 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 41838191 # ITB inst accesses
+system.cpu1.itb.hits 41835871 # DTB hits
+system.cpu1.itb.misses 2320 # DTB misses
+system.cpu1.itb.accesses 41838191 # DTB accesses
+system.cpu1.numCycles 128464441 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 14107719 # Number of instructions committed
-system.cpu1.committedOps 17288156 # Number of ops (including micro ops) committed
-system.cpu1.discardedOps 1387486 # Number of ops (including micro ops) which were discarded before commit
-system.cpu1.numFetchSuspends 2746 # Number of times Execute suspended instruction fetching
-system.cpu1.quiesceCycles 5656373541 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.cpi 2.887362 # CPI: cycles per instruction
-system.cpu1.ipc 0.346337 # IPC: instructions per cycle
+system.cpu1.committedInsts 51881050 # Number of instructions committed
+system.cpu1.committedOps 63376562 # Number of ops (including micro ops) committed
+system.cpu1.discardedOps 5336781 # Number of ops (including micro ops) which were discarded before commit
+system.cpu1.numFetchSuspends 2726 # Number of times Execute suspended instruction fetching
+system.cpu1.quiesceCycles 5169132523 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.cpi 2.476134 # CPI: cycles per instruction
+system.cpu1.ipc 0.403855 # IPC: instructions per cycle
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 2746 # number of quiesce instructions executed
-system.cpu1.tickCycles 27498026 # Number of cycles that the object actually ticked
-system.cpu1.idleCycles 13236067 # Total number of cycles that the object has spent stopped
-system.cpu1.dcache.tags.replacements 156251 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 474.671754 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 6246920 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 156599 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 39.891187 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 91622282000 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 474.671754 # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data 0.927093 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total 0.927093 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024 348 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2 286 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3 62 # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024 0.679688 # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses 13254229 # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses 13254229 # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data 3282688 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 3282688 # number of ReadReq hits
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-system.cpu1.dcache.SoftPFReq_hits::total 42687 # number of SoftPFReq hits
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-system.cpu1.dcache.overall_hits::total 6073539 # number of overall hits
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-system.cpu1.dcache.StoreCondReq_misses::total 23399 # number of StoreCondReq misses
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-system.cpu1.dcache.overall_misses::total 280590 # number of overall misses
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-system.cpu1.dcache.ReadReq_accesses::cpu1.data 3417288 # number of ReadReq accesses(hits+misses)
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-system.cpu1.dcache.ReadReq_avg_miss_latency::total 16219.985141 # average ReadReq miss latency
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-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19287.984473 # average LoadLockedReq miss latency
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-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27094.961323 # average StoreCondReq miss latency
+system.cpu1.kern.inst.quiesce 2733 # number of quiesce instructions executed
+system.cpu1.tickCycles 105981069 # Number of cycles that the object actually ticked
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+system.cpu1.dcache.tags.replacements 234073 # number of replacements
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+system.cpu1.dcache.tags.avg_refs 82.401423 # Average number of references to valid blocks.
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+system.cpu1.dcache.ReadReq_avg_miss_latency::total 15719.654480 # average ReadReq miss latency
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system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
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-system.cpu1.dcache.demand_avg_miss_latency::total 26089.294219 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23818.719484 # average overall miss latency
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system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 156252 # number of writebacks
-system.cpu1.dcache.writebacks::total 156252 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 12906 # number of ReadReq MSHR hits
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-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 641439000 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 641439000 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035611 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035611 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027791 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027791 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.355939 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.355939 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054944 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054944 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.274041 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.274041 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.032042 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.032042 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035463 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.035463 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15247.152694 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15247.152694 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34329.707601 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34329.707601 # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18921.753328 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18921.753328 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18093.253968 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18093.253968 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26095.175007 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26095.175007 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks 234075 # number of writebacks
+system.cpu1.dcache.writebacks::total 234075 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 18534 # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total 18534 # number of ReadReq MSHR hits
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+system.cpu1.dcache.WriteReq_mshr_hits::total 62653 # number of WriteReq MSHR hits
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+system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12294 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data 81187 # number of demand (read+write) MSHR hits
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+system.cpu1.dcache.overall_mshr_hits::total 81187 # number of overall MSHR hits
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+system.cpu1.dcache.ReadReq_mshr_misses::total 168141 # number of ReadReq MSHR misses
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+system.cpu1.dcache.SoftPFReq_mshr_misses::total 33570 # number of SoftPFReq MSHR misses
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+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5471 # number of LoadLockedReq MSHR misses
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+system.cpu1.dcache.StoreCondReq_mshr_misses::total 23562 # number of StoreCondReq MSHR misses
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+system.cpu1.dcache.demand_mshr_misses::total 274360 # number of demand (read+write) MSHR misses
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+system.cpu1.dcache.ReadReq_mshr_uncacheable::total 17170 # number of ReadReq MSHR uncacheable
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+system.cpu1.dcache.WriteReq_mshr_uncacheable::total 14450 # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 31620 # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total 31620 # number of overall MSHR uncacheable misses
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+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2472737500 # number of ReadReq MSHR miss cycles
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+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3237291000 # number of WriteReq MSHR miss cycles
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+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 585199000 # number of SoftPFReq MSHR miss cycles
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+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 99091500 # number of LoadLockedReq MSHR miss cycles
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+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 217500 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 217500 # number of StoreCondFailReq MSHR miss cycles
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+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3132437500 # number of ReadReq MSHR uncacheable cycles
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+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 5763820500 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 5763820500 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014196 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.014196 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014071 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014071 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.331206 # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.331206 # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051381 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051381 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.226171 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.226171 # mshr miss rate for StoreCondReq accesses
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+system.cpu1.dcache.demand_mshr_miss_rate::total 0.014147 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.015796 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.015796 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14706.332780 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14706.332780 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30477.513439 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 30477.513439 # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17432.201370 # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17432.201370 # average SoftPFReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18112.136721 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18112.136721 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 25892.093201 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 25892.093201 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22802.005977 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22802.005977 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22390.688933 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22390.688933 # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 130846.606183 # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 130846.606183 # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 109013.624567 # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 109013.624567 # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 121300.869894 # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 121300.869894 # average overall mshr uncacheable latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20812.175609 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20812.175609 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20443.696619 # average overall mshr miss latency
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+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 182436.662784 # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 182436.662784 # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 182102.629758 # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 182102.629758 # average WriteReq mshr uncacheable latency
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+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 182284.013283 # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements 863100 # number of replacements
-system.cpu1.icache.tags.tagsinuse 499.134862 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 6088925 # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs 863612 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 7.050533 # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle 73321501000 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.134862 # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974873 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total 0.974873 # Average percentage of cache occupancy
+system.cpu1.icache.tags.replacements 1045294 # number of replacements
+system.cpu1.icache.tags.tagsinuse 498.164820 # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs 40788041 # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs 1045806 # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs 39.001537 # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle 73317918000 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.164820 # Average occupied blocks per requestor
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+system.cpu1.icache.tags.occ_percent::total 0.972978 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2 464 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3 47 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2 462 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::3 50 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses 14768686 # Number of tag accesses
-system.cpu1.icache.tags.data_accesses 14768686 # Number of data accesses
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-system.cpu1.icache.ReadReq_hits::total 6088925 # number of ReadReq hits
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-system.cpu1.icache.demand_hits::total 6088925 # number of demand (read+write) hits
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-system.cpu1.icache.overall_hits::total 6088925 # number of overall hits
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-system.cpu1.icache.ReadReq_misses::total 863612 # number of ReadReq misses
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-system.cpu1.icache.demand_misses::total 863612 # number of demand (read+write) misses
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-system.cpu1.icache.overall_misses::total 863612 # number of overall misses
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-system.cpu1.icache.ReadReq_miss_latency::total 7643358500 # number of ReadReq miss cycles
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-system.cpu1.icache.demand_miss_latency::total 7643358500 # number of demand (read+write) miss cycles
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-system.cpu1.icache.ReadReq_accesses::total 6952537 # number of ReadReq accesses(hits+misses)
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-system.cpu1.icache.demand_accesses::total 6952537 # number of demand (read+write) accesses
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-system.cpu1.icache.overall_accesses::total 6952537 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.124215 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total 0.124215 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.124215 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total 0.124215 # miss rate for demand accesses
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-system.cpu1.icache.overall_miss_rate::total 0.124215 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8850.454255 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 8850.454255 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8850.454255 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 8850.454255 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8850.454255 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 8850.454255 # average overall miss latency
+system.cpu1.icache.tags.tag_accesses 84713500 # Number of tag accesses
+system.cpu1.icache.tags.data_accesses 84713500 # Number of data accesses
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+system.cpu1.icache.ReadReq_hits::total 40788041 # number of ReadReq hits
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+system.cpu1.icache.demand_hits::total 40788041 # number of demand (read+write) hits
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+system.cpu1.icache.overall_hits::total 40788041 # number of overall hits
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+system.cpu1.icache.ReadReq_misses::total 1045806 # number of ReadReq misses
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+system.cpu1.icache.demand_misses::total 1045806 # number of demand (read+write) misses
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+system.cpu1.icache.overall_misses::total 1045806 # number of overall misses
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+system.cpu1.icache.ReadReq_miss_latency::total 9756409000 # number of ReadReq miss cycles
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+system.cpu1.icache.demand_miss_latency::total 9756409000 # number of demand (read+write) miss cycles
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+system.cpu1.icache.overall_miss_latency::total 9756409000 # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst 41833847 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total 41833847 # number of ReadReq accesses(hits+misses)
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+system.cpu1.icache.demand_accesses::total 41833847 # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst 41833847 # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total 41833847 # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024999 # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total 0.024999 # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024999 # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total 0.024999 # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024999 # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total 0.024999 # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9329.081111 # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 9329.081111 # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9329.081111 # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 9329.081111 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9329.081111 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 9329.081111 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 137058.035714 # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 137058.035714 # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 51000.767342 # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 51000.767342 # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 18030.280336 # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 18030.280336 # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16547.653959 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14114.583333 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 51000.767342 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27368.557233 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29999.190646 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16547.653959 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14114.583333 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 51000.767342 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27368.557233 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48657.133070 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 32777.297974 # average overall mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 45897.697672 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 45897.697672 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 48734.253283 # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 48734.253283 # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 20354.413270 # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 20354.413270 # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 22538.567493 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14465.116279 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 48734.253283 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 28657.067862 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 32532.103899 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 22538.567493 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14465.116279 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 48734.253283 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 28657.067862 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 46108.401788 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 35510.022313 # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 129058.035714 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 122826.444892 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 123052.461140 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 101459.558824 # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 101459.558824 # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 174430.984275 # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 174136.934383 # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 174593.944637 # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 174593.944637 # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 129058.035714 # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 113484.493192 # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 113807.500000 # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 174505.455408 # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 174345.046010 # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.toL2Bus.snoop_filter.tot_requests 2143691 # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1079194 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 18287 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops 177461 # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 175960 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1501 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.trans_dist::ReadReq 34625 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp 1085487 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq 2312 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp 2312 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackDirty 125339 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackClean 924619 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict 97697 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq 24084 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq 71468 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41763 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp 84759 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 18 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq 57626 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp 55185 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq 863612 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq 234129 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateReq 33 # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2590548 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 747561 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6394 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 53434 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total 3397937 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 110516736 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25535556 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 10652 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 102512 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total 136165456 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops 380835 # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples 1457969 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean 0.140235 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev 0.350184 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_filter.tot_requests 2671947 # Total number of requests made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1344357 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 22211 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.snoop_filter.tot_snoops 212012 # Total number of snoops made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 209828 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2184 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.trans_dist::ReadReq 60366 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp 1353600 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq 14450 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp 14450 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackDirty 179270 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackClean 1143304 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict 137947 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq 47540 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq 74191 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 43096 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 89660 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 12 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq 82906 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp 80697 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq 1045806 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq 295809 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateReq 50 # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 3137130 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 1052074 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7597 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 73953 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total 4270754 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 133837568 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 36094549 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 12564 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 141300 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total 170085981 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops 473244 # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples 1845377 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean 0.133426 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.343498 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0 1255011 86.08% 86.08% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1 201457 13.82% 99.90% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2 1501 0.10% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0 1601339 86.78% 86.78% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1 241854 13.11% 99.88% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2 2184 0.12% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total 1457969 # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy 2107221995 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total 1845377 # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy 2655073991 # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy 78416105 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy 86773438 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy 1295704762 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy 333278550 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy 1569094564 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
+system.cpu1.toL2Bus.respLayer1.occupancy 476141581 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy 3731000 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy 4456000 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy 27832447 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy 38655445 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 31009 # Transaction distribution
-system.iobus.trans_dist::ReadResp 31009 # Transaction distribution
-system.iobus.trans_dist::WriteReq 59425 # Transaction distribution
-system.iobus.trans_dist::WriteResp 59425 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56620 # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::ReadReq 31014 # Transaction distribution
+system.iobus.trans_dist::ReadResp 31014 # Transaction distribution
+system.iobus.trans_dist::WriteReq 59421 # Transaction distribution
+system.iobus.trans_dist::WriteResp 59421 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56600 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 846 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 107934 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 180868 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71564 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 107910 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72960 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 72960 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 180870 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71544 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 447 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 162814 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 2483990 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 51092500 # Layer occupancy (ticks)
+system.iobus.pkt_size_system.bridge.master::total 162792 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321280 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 2321280 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 2484072 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 51031501 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 109500 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 322000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy 336000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 30500 # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy 29000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer4.occupancy 14000 # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy 13000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
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-system.l2c.overall_mshr_uncacheable_latency::total 11579881514 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data 4963134507 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 11585399523 # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.236663 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.528066 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total 0.264073 # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.268760 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.571944 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.396986 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.721287 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.860924 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total 0.773675 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.241563 # mshr miss rate for ReadSharedReq accesses
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-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.155844 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.240331 # mshr miss rate for ReadSharedReq accesses
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-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.241563 # mshr miss rate for demand accesses
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-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.155844 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst 0.240331 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data 0.591143 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.586246 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0.531121 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.241563 # mshr miss rate for overall accesses
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-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.155844 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst 0.240331 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data 0.591143 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.586246 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.531121 # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 72833.870051 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 72392.681930 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 72750.884343 # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 74662.976630 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73882.886435 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 74187.650168 # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 138043.153987 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 122120.487067 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 131395.732529 # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 127419.117647 # average ReadSharedReq mshr miss latency
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system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 123000 # average ReadSharedReq mshr miss latency
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system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 123000 # average overall mshr miss latency
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system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 123000 # average overall mshr miss latency
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system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113291.549655 # average ReadReq mshr uncacheable latency
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system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 108053.571429 # average ReadReq mshr uncacheable latency
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-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165318.379779 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 84456.099481 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159294.225881 # average WriteReq mshr uncacheable latency
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system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113291.549655 # average overall mshr uncacheable latency
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system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 108053.571429 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 95972.564617 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 165249.825387 # average overall mshr uncacheable latency
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+system.l2c.overall_avg_mshr_uncacheable_latency::total 164736.154294 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 39041 # Transaction distribution
-system.membus.trans_dist::ReadResp 215941 # Transaction distribution
-system.membus.trans_dist::WriteReq 31034 # Transaction distribution
-system.membus.trans_dist::WriteResp 31034 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 138436 # Transaction distribution
-system.membus.trans_dist::CleanEvict 18070 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 73582 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 40721 # Transaction distribution
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+system.membus.trans_dist::ReadResp 215417 # Transaction distribution
+system.membus.trans_dist::WriteReq 31165 # Transaction distribution
+system.membus.trans_dist::WriteResp 31165 # Transaction distribution
+system.membus.trans_dist::WritebackDirty 139900 # Transaction distribution
+system.membus.trans_dist::CleanEvict 18801 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 78213 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 41798 # Transaction distribution
system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
-system.membus.trans_dist::ReadExReq 40108 # Transaction distribution
-system.membus.trans_dist::ReadExResp 19531 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 176900 # Transaction distribution
+system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution
+system.membus.trans_dist::ReadExReq 40189 # Transaction distribution
+system.membus.trans_dist::ReadExResp 19404 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 176255 # Transaction distribution
system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107934 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107910 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 42 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14216 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 664933 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 787125 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72931 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 72931 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 860056 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162814 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14740 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 671466 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 794158 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72957 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 72957 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 867115 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162792 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1344 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28432 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19353628 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 19546218 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29480 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19397092 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 19590708 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 21864362 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 120262 # Total snoops (count)
-system.membus.snoop_fanout::samples 594139 # Request fanout histogram
+system.membus.pkt_size::total 21908852 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 125573 # Total snoops (count)
+system.membus.snoop_fanout::samples 601741 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 594139 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 601741 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 594139 # Request fanout histogram
-system.membus.reqLayer0.occupancy 91324000 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 601741 # Request fanout histogram
+system.membus.reqLayer0.occupancy 91242999 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 23828 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 12307500 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 12732000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 1010896317 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 1019564727 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 1147679286 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 1144074788 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 1341127 # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy 1412877 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests 1042334 # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests 562614 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests 153410 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops 21132 # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops 20109 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops 1023 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq 39044 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 500861 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 31034 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 31034 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty 405302 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 139265 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 109721 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 43882 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 153603 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq 18 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp 18 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 51189 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 51189 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 461832 # Transaction distribution
+system.toL2Bus.snoop_filter.tot_requests 1069309 # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests 577929 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests 171835 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops 21548 # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops 20404 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops 1144 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.trans_dist::ReadReq 39165 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 514340 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 31165 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 31165 # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty 409596 # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict 144328 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 114559 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 44999 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 159558 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp 12 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 51602 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 51602 # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq 475191 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1332417 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 274320 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 1606737 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 36835698 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4378808 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 41214506 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 447707 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 941615 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 0.339048 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.475676 # Request fanout histogram
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1207299 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 435215 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 1642514 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34510571 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7361417 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 41871988 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 461244 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 963683 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 0.359503 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.482323 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 623385 66.20% 66.20% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 317207 33.69% 99.89% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 1023 0.11% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 618380 64.17% 64.17% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 344159 35.71% 99.88% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 1144 0.12% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 941615 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 901922668 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 963683 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 919452336 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 342123 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy 360123 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 690834076 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 640437781 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 214047025 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 288270065 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
ata1.00: configured for UDMA/33\r
scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
sd 0:0:0:0: [sda] 1048320 512-byte logical blocks: (536 MB/511 MiB)\r
-sd 0:0:0:0: Attached scsi generic sg0 type 0\r
sd 0:0:0:0: [sda] Write Protect is off\r
+sd 0:0:0:0: Attached scsi generic sg0 type 0\r
sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
sda: sda1\r
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm
+boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
+dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
+exit_on_work_items=false
flags_addr=469827632
gic_cpu_addr=738205696
have_large_asid_64=false
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
+readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/work/gem5/dist/disks/linux-aarch32-ael.img
+image_file=/home/stever/m5/aarch-system-2014-10/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=false
hit_latency=50
is_read_only=false
max_miss_count=0
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
warn: Ignoring write to miscreg pmovsr
warn: Ignoring write to miscreg pmcr
warn: Ignoring write to miscreg pmcr
-warn: 409464076500: Instruction results do not match! (Values may not actually be integers) Inst: 0x80000001, checker: 0x80000000
+warn: 409465425500: Instruction results do not match! (Values may not actually be integers) Inst: 0x80000001, checker: 0x80000000
warn: instruction 'mcr dcisw' unimplemented
warn: instruction 'mcr bpiall' unimplemented
+Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker/simout
+Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 4 2015 11:13:17
-gem5 started Dec 4 2015 12:53:29
-gem5 executing on e104799-lin, pid 6838
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker
+gem5 compiled Mar 15 2016 21:26:42
+gem5 started Mar 15 2016 21:34:31
+gem5 executing on phenom, pid 15958
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+info: kernel located at: /home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80008000
-info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
+info: Loading DTB file: /home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-Exiting @ tick 2832912592000 because m5_exit instruction encountered
+Exiting @ tick 2832922792000 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 2.832892 # Number of seconds simulated
-sim_ticks 2832892490000 # Number of ticks simulated
-final_tick 2832892490000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.832923 # Number of seconds simulated
+sim_ticks 2832922792000 # Number of ticks simulated
+final_tick 2832922792000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 98762 # Simulator instruction rate (inst/s)
-host_op_rate 119789 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2474201806 # Simulator tick rate (ticks/s)
-host_mem_usage 585008 # Number of bytes of host memory used
-host_seconds 1144.97 # Real time elapsed on the host
-sim_insts 113079496 # Number of instructions simulated
-sim_ops 137154742 # Number of ops (including micro ops) simulated
+host_inst_rate 64859 # Simulator instruction rate (inst/s)
+host_op_rate 78668 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1624421261 # Simulator tick rate (ticks/s)
+host_mem_usage 564480 # Number of bytes of host memory used
+host_seconds 1743.96 # Real time elapsed on the host
+sim_insts 113110851 # Number of instructions simulated
+sim_ops 137193114 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 1408 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 512 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 1315968 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9383464 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 1316352 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9383208 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 10702248 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 1315968 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1315968 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7997504 # Number of bytes written to this memory
+system.physmem.bytes_read::total 10702440 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 1316352 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1316352 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7997632 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
-system.physmem.bytes_written::total 8015028 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker 21 # Number of read requests responded to by this memory
+system.physmem.bytes_written::total 8015156 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker 22 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 8 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 22809 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 147137 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 22815 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 147133 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 169990 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 124961 # Number of write requests responded to by this memory
+system.physmem.num_reads::total 169993 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 124963 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 129342 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker 474 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 129344 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker 497 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 181 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 464532 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3312326 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::realview.ide 339 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 3777852 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 464532 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 464532 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 2823088 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu.data 6186 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2829274 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 2823088 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 474 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.itb.walker 181 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 464532 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 3318512 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.ide 339 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 6607125 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 169991 # Number of read requests accepted
-system.physmem.writeReqs 129342 # Number of write requests accepted
-system.physmem.readBursts 169991 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 129342 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 10867968 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 11456 # Total number of bytes read from write queue
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+system.physmem.bytesReadDRAM 10868544 # Total number of bytes read from DRAM
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system.physmem.bytesWritten 8027328 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 10702312 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 8015028 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 179 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 11395 # Per bank write bursts
system.physmem.perBankRdBursts::1 10614 # Per bank write bursts
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system.physmem.perBankRdBursts::3 11362 # Per bank write bursts
system.physmem.perBankRdBursts::4 12761 # Per bank write bursts
system.physmem.perBankRdBursts::5 10093 # Per bank write bursts
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system.physmem.perBankRdBursts::8 10555 # Per bank write bursts
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system.physmem.perBankRdBursts::15 10086 # Per bank write bursts
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system.physmem.perBankWrBursts::1 7964 # Per bank write bursts
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system.physmem.perBankWrBursts::3 8679 # Per bank write bursts
system.physmem.perBankWrBursts::4 7544 # Per bank write bursts
system.physmem.perBankWrBursts::5 7468 # Per bank write bursts
system.physmem.perBankWrBursts::6 8076 # Per bank write bursts
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system.physmem.perBankWrBursts::8 8056 # Per bank write bursts
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system.physmem.perBankWrBursts::10 7497 # Per bank write bursts
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system.physmem.perBankWrBursts::12 7556 # Per bank write bursts
system.physmem.perBankWrBursts::13 8041 # Per bank write bursts
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system.physmem.perBankWrBursts::15 7447 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 10 # Number of times write queue was full causing retry
-system.physmem.totGap 2832892258000 # Total gap between requests
+system.physmem.numWrRetry 20 # Number of times write queue was full causing retry
+system.physmem.totGap 2832922560000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 542 # Read request sizes (log2)
system.physmem.readPktSize::3 14 # Read request sizes (log2)
system.physmem.readPktSize::4 2996 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 166439 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 4381 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
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-system.physmem.bytesPerActivate::mean 304.427918 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 179.985587 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 324.629395 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 23230 37.43% 37.43% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::256-383 6492 10.46% 72.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 3585 5.78% 77.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2536 4.09% 81.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1572 2.53% 84.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1564 2.52% 86.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1071 1.73% 88.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 7002 11.28% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 62068 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 6143 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 27.640729 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 569.576579 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047 6142 99.98% 99.98% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes
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-system.physmem.wrPerTurnAround::84-87 1 0.02% 99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99 1 0.02% 99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103 1 0.02% 99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107 1 0.02% 99.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123 1 0.02% 99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127 2 0.03% 99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 4 0.07% 99.76% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::32-35 22 0.36% 92.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 18 0.29% 92.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 54 0.88% 93.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 11 0.18% 93.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 137 2.23% 95.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 15 0.24% 96.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 11 0.18% 96.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 9 0.15% 96.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 67 1.09% 97.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 4 0.07% 97.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 9 0.15% 97.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79 29 0.47% 98.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 82 1.34% 99.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95 1 0.02% 99.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99 1 0.02% 99.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107 1 0.02% 99.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115 1 0.02% 99.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123 1 0.02% 99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 7 0.11% 99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135 1 0.02% 99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 2 0.03% 99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147 9 0.15% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159 1 0.02% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163 1 0.02% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179 2 0.03% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 6143 # Writes before turning the bus around for reads
-system.physmem.totQLat 2131723500 # Total ticks spent queuing
-system.physmem.totMemAccLat 5315698500 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 849060000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 12553.43 # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::144-147 5 0.08% 99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155 1 0.02% 99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159 3 0.05% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163 1 0.02% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175 1 0.02% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179 1 0.02% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-195 1 0.02% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 6134 # Writes before turning the bus around for reads
+system.physmem.totQLat 2139801000 # Total ticks spent queuing
+system.physmem.totMemAccLat 5323944750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 849105000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 12600.33 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 31303.43 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 31350.33 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 3.84 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 2.83 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 3.78 # Average system read bandwidth in MiByte/s
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 26.05 # Average write queue length when enqueuing
-system.physmem.readRowHits 139329 # Number of row buffer hits during reads
-system.physmem.writeRowHits 93841 # Number of row buffer hits during writes
+system.physmem.avgWrQLen 27.97 # Average write queue length when enqueuing
+system.physmem.readRowHits 139332 # Number of row buffer hits during reads
+system.physmem.writeRowHits 93753 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.05 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 74.80 # Row buffer hit rate for writes
-system.physmem.avgGap 9464015.86 # Average gap between requests
-system.physmem.pageHitRate 78.97 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 247484160 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 135036000 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 696267000 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 421167600 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 185030401920 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 83639897910 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 1626363962250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 1896534216840 # Total energy per rank (pJ)
-system.physmem_0.averagePower 669.470442 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 2705464523500 # Time in different power states
-system.physmem_0.memoryStateTime::REF 94596320000 # Time in different power states
+system.physmem.writeRowHitRate 74.73 # Row buffer hit rate for writes
+system.physmem.avgGap 9463959.00 # Average gap between requests
+system.physmem.pageHitRate 78.94 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 247869720 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 135246375 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 696290400 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 421154640 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 185032436160 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 83656164285 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 1626368380500 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 1896557542080 # Total energy per rank (pJ)
+system.physmem_0.averagePower 669.471316 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 2705472781500 # Time in different power states
+system.physmem_0.memoryStateTime::REF 94597360000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 32831633000 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 32852637000 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 221749920 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 120994500 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 628258800 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 391599360 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 185030401920 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 81914804595 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 1627877202000 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 1896185011095 # Total energy per rank (pJ)
-system.physmem_1.averagePower 669.347174 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 2707992537250 # Time in different power states
-system.physmem_1.memoryStateTime::REF 94596320000 # Time in different power states
+system.physmem_1.actEnergy 222075000 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 121171875 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 628305600 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 391612320 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 185032436160 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 81913765770 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 1627896800250 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 1896206166975 # Total energy per rank (pJ)
+system.physmem_1.averagePower 669.347283 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 2708023579500 # Time in different power states
+system.physmem_1.memoryStateTime::REF 94597360000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 30298312750 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 30297375500 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
-system.cpu.branchPred.lookups 46858247 # Number of BP lookups
-system.cpu.branchPred.condPredicted 24018458 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 1233894 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 29504756 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 21322919 # Number of BTB hits
+system.cpu.branchPred.lookups 46900870 # Number of BP lookups
+system.cpu.branchPred.condPredicted 24033937 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 1233884 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 29535620 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 21344859 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 72.269430 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 11723897 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 33908 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 72.268193 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 11734674 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 33890 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin::total 17244 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
-system.cpu.checker.dtb.read_hits 24571828 # DTB read hits
+system.cpu.checker.dtb.read_hits 24578942 # DTB read hits
system.cpu.checker.dtb.read_misses 8287 # DTB read misses
-system.cpu.checker.dtb.write_hits 19630538 # DTB write hits
+system.cpu.checker.dtb.write_hits 19634178 # DTB write hits
system.cpu.checker.dtb.write_misses 1417 # DTB write misses
system.cpu.checker.dtb.flush_tlb 128 # Number of times complete TLB was flushed
system.cpu.checker.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA
system.cpu.checker.dtb.prefetch_faults 1642 # Number of TLB faults due to prefetch
system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions
-system.cpu.checker.dtb.read_accesses 24580115 # DTB read accesses
-system.cpu.checker.dtb.write_accesses 19631955 # DTB write accesses
+system.cpu.checker.dtb.read_accesses 24587229 # DTB read accesses
+system.cpu.checker.dtb.write_accesses 19635595 # DTB write accesses
system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.checker.dtb.hits 44202366 # DTB hits
+system.cpu.checker.dtb.hits 44213120 # DTB hits
system.cpu.checker.dtb.misses 9704 # DTB misses
-system.cpu.checker.dtb.accesses 44212070 # DTB accesses
+system.cpu.checker.dtb.accesses 44222824 # DTB accesses
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 3170 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 3170 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin::total 7995 # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.inst_hits 115776459 # ITB inst hits
+system.cpu.checker.itb.inst_hits 115809550 # ITB inst hits
system.cpu.checker.itb.inst_misses 4825 # ITB inst misses
system.cpu.checker.itb.read_hits 0 # DTB read hits
system.cpu.checker.itb.read_misses 0 # DTB read misses
system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses 0 # DTB read accesses
system.cpu.checker.itb.write_accesses 0 # DTB write accesses
-system.cpu.checker.itb.inst_accesses 115781284 # ITB inst accesses
-system.cpu.checker.itb.hits 115776459 # DTB hits
+system.cpu.checker.itb.inst_accesses 115814375 # ITB inst accesses
+system.cpu.checker.itb.hits 115809550 # DTB hits
system.cpu.checker.itb.misses 4825 # DTB misses
-system.cpu.checker.itb.accesses 115781284 # DTB accesses
-system.cpu.checker.numCycles 139003748 # number of cpu cycles simulated
+system.cpu.checker.itb.accesses 115814375 # DTB accesses
+system.cpu.checker.numCycles 139043856 # number of cpu cycles simulated
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.walks 71892 # Table walker walks requested
-system.cpu.dtb.walker.walksShort 71892 # Table walker walks initiated with short descriptors
-system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29751 # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22366 # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksSquashedBefore 19775 # Table walks squashed before starting
-system.cpu.dtb.walker.walkWaitTime::samples 52117 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::mean 422.184700 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::stdev 2564.754173 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0-4095 50340 96.59% 96.59% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::4096-8191 585 1.12% 97.71% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::8192-12287 526 1.01% 98.72% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::12288-16383 339 0.65% 99.37% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::16384-20479 52 0.10% 99.47% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walks 71837 # Table walker walks requested
+system.cpu.dtb.walker.walksShort 71837 # Table walker walks initiated with short descriptors
+system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29758 # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22348 # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksSquashedBefore 19731 # Table walks squashed before starting
+system.cpu.dtb.walker.walkWaitTime::samples 52106 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::mean 420.441024 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::stdev 2560.543879 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0-4095 50336 96.60% 96.60% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::4096-8191 584 1.12% 97.72% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::8192-12287 523 1.00% 98.73% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::12288-16383 337 0.65% 99.37% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::16384-20479 50 0.10% 99.47% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::20480-24575 220 0.42% 99.89% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::24576-28671 14 0.03% 99.92% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::24576-28671 15 0.03% 99.92% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::28672-32767 10 0.02% 99.94% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::32768-36863 8 0.02% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::36864-40959 5 0.01% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::53248-57343 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::57344-61439 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::61440-65535 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total 52117 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples 17509 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 11528.471072 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 9159.485910 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev 8140.517404 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-32767 17326 98.95% 98.95% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkWaitTime::total 52106 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples 17457 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 11531.334135 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 9171.811391 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev 8140.859549 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-32767 17274 98.95% 98.95% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::32768-65535 177 1.01% 99.97% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::131072-163839 5 0.03% 99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total 17509 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples 131356952816 # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::mean 0.616906 # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::stdev 0.493482 # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0-1 131302352316 99.96% 99.96% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::2-3 37456000 0.03% 99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::4-5 6990000 0.01% 99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::6-7 6140500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::8-9 1200000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::10-11 643000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::12-13 1366500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::14-15 794500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walkCompletionTime::total 17457 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples 131387254816 # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::mean 0.617449 # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::stdev 0.493362 # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0-1 131332759316 99.96% 99.96% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::2-3 37388500 0.03% 99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::4-5 6986000 0.01% 99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::6-7 6081500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::8-9 1205000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::10-11 646500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::12-13 1379500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::14-15 798500 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::16-17 10000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total 131356952816 # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K 6353 82.36% 82.36% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::1M 1361 17.64% 100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total 7714 # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 71892 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walksPending::total 131387254816 # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K 6345 82.34% 82.34% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::1M 1361 17.66% 100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total 7706 # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 71837 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 71892 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7714 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total 71837 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7706 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7714 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 79606 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7706 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total 79543 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 25445841 # DTB read hits
-system.cpu.dtb.read_misses 61989 # DTB read misses
-system.cpu.dtb.write_hits 19906354 # DTB write hits
-system.cpu.dtb.write_misses 9903 # DTB write misses
+system.cpu.dtb.read_hits 25453240 # DTB read hits
+system.cpu.dtb.read_misses 61907 # DTB read misses
+system.cpu.dtb.write_hits 19910032 # DTB write hits
+system.cpu.dtb.write_misses 9930 # DTB write misses
system.cpu.dtb.flush_tlb 128 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.align_faults 357 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 2185 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 1330 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 25507830 # DTB read accesses
-system.cpu.dtb.write_accesses 19916257 # DTB write accesses
+system.cpu.dtb.perms_faults 1331 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 25515147 # DTB read accesses
+system.cpu.dtb.write_accesses 19919962 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 45352195 # DTB hits
-system.cpu.dtb.misses 71892 # DTB misses
-system.cpu.dtb.accesses 45424087 # DTB accesses
+system.cpu.dtb.hits 45363272 # DTB hits
+system.cpu.dtb.misses 71837 # DTB misses
+system.cpu.dtb.accesses 45435109 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.walks 11896 # Table walker walks requested
-system.cpu.itb.walker.walksShort 11896 # Table walker walks initiated with short descriptors
-system.cpu.itb.walker.walksShortTerminationLevel::Level1 3936 # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walksShortTerminationLevel::Level2 7739 # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walksSquashedBefore 221 # Table walks squashed before starting
-system.cpu.itb.walker.walkWaitTime::samples 11675 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::mean 618.158458 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::stdev 2886.319815 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0-4095 11119 95.24% 95.24% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::4096-8191 158 1.35% 96.59% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::8192-12287 193 1.65% 98.24% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::12288-16383 62 0.53% 98.78% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::16384-20479 98 0.84% 99.61% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::20480-24575 33 0.28% 99.90% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::24576-28671 2 0.02% 99.91% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walks 13224 # Table walker walks requested
+system.cpu.itb.walker.walksShort 13224 # Table walker walks initiated with short descriptors
+system.cpu.itb.walker.walksShortTerminationLevel::Level1 3935 # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walksShortTerminationLevel::Level2 7779 # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walksSquashedBefore 1510 # Table walks squashed before starting
+system.cpu.itb.walker.walkWaitTime::samples 11714 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::mean 663.436913 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::stdev 2983.675240 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0-4095 11112 94.86% 94.86% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::4096-8191 167 1.43% 96.29% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::8192-12287 192 1.64% 97.93% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::12288-16383 98 0.84% 98.76% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::16384-20479 101 0.86% 99.62% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::20480-24575 31 0.26% 99.89% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::24576-28671 3 0.03% 99.91% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::28672-32767 7 0.06% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::45056-49151 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::49152-53247 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::57344-61439 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total 11675 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples 3548 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 12874.295378 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 10192.055773 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev 8701.296219 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-16383 2600 73.28% 73.28% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::16384-32767 890 25.08% 98.37% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::32768-49151 56 1.58% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::131072-147455 2 0.06% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total 3548 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples 23982708416 # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::mean 0.963466 # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::stdev 0.187762 # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0 876788500 3.66% 3.66% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::1 23105369416 96.34% 100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::2 493000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walkWaitTime::total 11714 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples 4832 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 11551.427980 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 9033.563647 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev 8305.140651 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-16383 3848 79.64% 79.64% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::16384-32767 915 18.94% 98.57% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::32768-49151 67 1.39% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::131072-147455 2 0.04% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total 4832 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples 24013010416 # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::mean 0.681227 # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::stdev 0.466165 # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0 7656484500 31.88% 31.88% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::1 16354802916 68.11% 99.99% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::2 1665500 0.01% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::3 57500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total 23982708416 # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K 3008 90.41% 90.41% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::1M 319 9.59% 100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total 3327 # Table walker page sizes translated
+system.cpu.itb.walker.walksPending::total 24013010416 # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K 3004 90.43% 90.43% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::1M 318 9.57% 100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total 3322 # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 11896 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 11896 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 13224 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total 13224 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3327 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 3327 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 15223 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 66221900 # ITB inst hits
-system.cpu.itb.inst_misses 11896 # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3322 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total 3322 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total 16546 # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits 66215474 # ITB inst hits
+system.cpu.itb.inst_misses 13224 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 3095 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 3093 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 2205 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 2222 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 66233796 # ITB inst accesses
-system.cpu.itb.hits 66221900 # DTB hits
-system.cpu.itb.misses 11896 # DTB misses
-system.cpu.itb.accesses 66233796 # DTB accesses
-system.cpu.numCycles 278773245 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 66228698 # ITB inst accesses
+system.cpu.itb.hits 66215474 # DTB hits
+system.cpu.itb.misses 13224 # DTB misses
+system.cpu.itb.accesses 66228698 # DTB accesses
+system.cpu.numCycles 278849039 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 104752235 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 184598573 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 46858247 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 33046816 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 161804794 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 6150362 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 189820 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles 10294 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 357135 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 560172 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 186 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 66222091 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 1133757 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 5184 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 270749817 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.831543 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 1.217938 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 104825039 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 184547548 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 46900870 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 33079533 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 161783291 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 6174948 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 189837 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles 10053 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 357428 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 560111 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 175 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 66214357 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 1060583 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 6520 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 270813408 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.831546 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 1.217852 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 171531140 63.35% 63.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 29224382 10.79% 74.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 14067275 5.20% 79.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 55927020 20.66% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 171553183 63.35% 63.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 29255757 10.80% 74.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 14075334 5.20% 79.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 55929134 20.65% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 270749817 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.168087 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.662182 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 77852001 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 121869294 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 64587229 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 3844010 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 2597283 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 3423147 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 486289 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 157329382 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 3698909 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 2597283 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 83697131 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 11783559 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 76650059 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 62587653 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 33434132 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 146702491 # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts 957120 # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents 451934 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 63799 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 16325 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 30684565 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 150381225 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 678253528 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 164322158 # Number of integer rename lookups
+system.cpu.fetch.rateDist::total 270813408 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.168194 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.661819 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 77914241 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 121818980 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 64632452 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 3838198 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 2609537 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 3423128 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 486335 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 157406934 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 3698656 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 2609537 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 83756930 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 11780773 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 76597873 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 62631659 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 33436636 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 146755972 # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts 956855 # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents 452398 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 63697 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 16353 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 30702971 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 150428298 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 678515900 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 164385434 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 10889 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 141709530 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 8671692 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 2840546 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 2644403 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 13862058 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 26394800 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 21292698 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1688864 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 2213691 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 143441668 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 2121624 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 143228772 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 270823 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 8408546 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 14699465 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 125775 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 270749817 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.529008 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 0.865566 # Number of insts issued each cycle
+system.cpu.rename.CommittedMaps 141750240 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 8678055 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 2842275 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 2646130 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 13851175 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 26402053 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 21296304 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1688639 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 2128632 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 143481450 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 2121615 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 143268725 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 270645 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 8409947 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 14700028 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 125764 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 270813408 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.529031 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 0.865143 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 182513589 67.41% 67.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 45134220 16.67% 84.08% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 32022113 11.83% 95.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 10269287 3.79% 99.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 810575 0.30% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 182463558 67.38% 67.38% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 45313359 16.73% 84.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 31963465 11.80% 95.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 10263701 3.79% 99.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 809292 0.30% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 270749817 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 270813408 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 7336339 32.73% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 32 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 5631595 25.13% 57.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 9443725 42.14% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 7332102 32.71% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 32 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 5631471 25.13% 57.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 9448597 42.16% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 95929894 66.98% 66.98% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 113798 0.08% 67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 95958706 66.98% 66.98% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 113835 0.08% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 8576 0.01% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 26176243 18.28% 85.34% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 20997924 14.66% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 8576 0.01% 67.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 26183625 18.28% 85.34% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 21001646 14.66% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 143228772 # Type of FU issued
-system.cpu.iq.rate 0.513782 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 22411691 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.156475 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 579854290 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 153977213 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 140119725 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 35585 # Number of floating instruction queue reads
+system.cpu.iq.FU_type_0::total 143268725 # Type of FU issued
+system.cpu.iq.rate 0.513786 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 22412202 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.156435 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 579998115 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 154018366 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 140157777 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 35590 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 13122 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 11367 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 165614781 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 23345 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 322762 # Number of loads that had data forwarded from stores
+system.cpu.iq.int_alu_accesses 165655240 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 23350 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 322841 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1496089 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 504 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 18542 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 704390 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1496212 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 510 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 18521 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 704329 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 87859 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 6368 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 88213 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 6464 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 2597283 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 1242021 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 536402 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 145764225 # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles 2609537 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 1244131 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 534453 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 145804019 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 26394800 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 21292698 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1096198 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 17994 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 502218 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 18542 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 317968 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 471203 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 789171 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 142285969 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 25773594 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 871017 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts 26402053 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 21296304 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1096200 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 17993 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 500261 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 18521 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 317950 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 471174 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 789124 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 142326073 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 25781011 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 870919 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 200933 # number of nop insts executed
-system.cpu.iew.exec_refs 46642596 # number of memory reference insts executed
-system.cpu.iew.exec_branches 26501312 # Number of branches executed
-system.cpu.iew.exec_stores 20869002 # Number of stores executed
-system.cpu.iew.exec_rate 0.510400 # Inst execution rate
-system.cpu.iew.wb_sent 141899463 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 140131092 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 63222174 # num instructions producing a value
-system.cpu.iew.wb_consumers 95712525 # num instructions consuming a value
-system.cpu.iew.wb_rate 0.502671 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.660542 # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts 7607261 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1995849 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 755996 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 267815570 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.512702 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.117847 # Number of insts commited each cycle
+system.cpu.iew.exec_nop 200954 # number of nop insts executed
+system.cpu.iew.exec_refs 46653702 # number of memory reference insts executed
+system.cpu.iew.exec_branches 26511824 # Number of branches executed
+system.cpu.iew.exec_stores 20872691 # Number of stores executed
+system.cpu.iew.exec_rate 0.510405 # Inst execution rate
+system.cpu.iew.wb_sent 141939572 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 140169144 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 63244057 # num instructions producing a value
+system.cpu.iew.wb_consumers 95727511 # num instructions consuming a value
+system.cpu.iew.wb_rate 0.502670 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.660668 # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts 7609153 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1995851 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 755947 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 267866819 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.512747 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.116675 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 194420599 72.59% 72.59% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 43232205 16.14% 88.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 15469123 5.78% 94.51% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 4394347 1.64% 96.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 6341720 2.37% 98.52% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1685703 0.63% 99.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 801057 0.30% 99.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 412110 0.15% 99.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 1058706 0.40% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 194366787 72.56% 72.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 43325916 16.17% 88.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 15476786 5.78% 94.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 4394475 1.64% 96.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 6423634 2.40% 98.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1609805 0.60% 99.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 801244 0.30% 99.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 411295 0.15% 99.61% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 1056877 0.39% 100.00% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 267815570 # Number of insts commited each cycle
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system.cpu.commit.membars 814912 # Number of memory barriers committed
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system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
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system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.87% # Class of committed instruction
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-system.cpu.commit.op_class_0::total 137309647 # Class of committed instruction
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-system.cpu.idleCycles 8023428 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 5387011736 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 113079496 # Number of Instructions Simulated
-system.cpu.committedOps 137154742 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 2.465286 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 2.465286 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.405633 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.405633 # IPC: Total IPC of All Threads
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+system.cpu.cpi_total 2.465272 # CPI: Total CPI of All Threads
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system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 43142.857143 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 43142.857143 # average StoreCondReq miss latency
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu.icache.tags.total_refs 64239998 # Total number of references to valid blocks.
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+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2431176001 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17916869000 # number of overall MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 340117000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5887198000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6227315000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4756961000 # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4756961000 # number of WriteReq MSHR uncacheable cycles
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+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6227712000 # number of ReadReq MSHR uncacheable cycles
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system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 340117000 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10644159000 # number of overall MSHR uncacheable cycles
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-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000385 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000675 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000436 # mshr miss rate for ReadReq accesses
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system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.988017 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.988017 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.428571 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.428571 # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.455926 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.455926 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010500 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010500 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.024649 # mshr miss rate for ReadSharedReq accesses
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-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000385 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000675 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010500 # mshr miss rate for demand accesses
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-system.cpu.l2cache.demand_mshr_miss_rate::total 0.060387 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000385 # mshr miss rate for overall accesses
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-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010500 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.177503 # mshr miss rate for overall accesses
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-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 136714.285714 # average ReadReq mshr miss latency
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-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 132862.068966 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68012.862918 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68012.862918 # average UpgradeReq mshr miss latency
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system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69833.333333 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69833.333333 # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 119968.506961 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 119968.506961 # average ReadExReq mshr miss latency
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-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122395.084881 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125346.958674 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125346.958674 # average ReadSharedReq mshr miss latency
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-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122395.084881 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120450.668334 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120681.372474 # average overall mshr miss latency
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-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122395.084881 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120450.668334 # average overall mshr miss latency
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+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122650.388508 # average ReadCleanReq mshr miss latency
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+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120470.596541 # average overall mshr miss latency
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+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120470.596541 # average overall mshr miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113221.371505 # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189122.618780 # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 182442.650807 # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172447.380823 # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172447.380823 # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189135.372161 # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 182454.281780 # average ReadReq mshr uncacheable latency
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+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172423.001631 # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113221.371505 # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181288.261743 # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177975.242231 # average overall mshr uncacheable latency
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+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177970.778379 # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests 5483442 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 2758353 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 47114 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 381 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 381 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests 5483800 # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 2758533 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 47116 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops 382 # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops 382 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadReq 128030 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 2556317 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq 128080 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 2556548 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 27585 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 27585 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty 820394 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 1886695 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 149869 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty 820436 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean 1886845 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict 149868 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 2755 # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 2761 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 296967 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 296967 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 1887230 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 541172 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 296964 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 296964 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 1887380 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 541203 # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq 36194 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5667118 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2636221 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31264 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 129096 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 8463699 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 241576384 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98323817 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 47400 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 218452 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 340166053 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 196965 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 3052848 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.025894 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.158818 # Request fanout histogram
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5667569 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2636305 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31377 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 129075 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 8464326 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 241595648 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98327529 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 47536 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 218484 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 340189197 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 196985 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 3053089 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 0.025893 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.158816 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 2973799 97.41% 97.41% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 79049 2.59% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 2974035 97.41% 97.41% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 79054 2.59% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 3052848 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 5399685497 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 3053089 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 5400068497 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy 264877 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 2834668847 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 2834904825 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 1303356559 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 1303398559 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy 19420986 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy 19499986 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy 74535395 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy 74506395 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.trans_dist::ReadReq 30198 # Transaction distribution
system.iobus.trans_dist::ReadResp 30198 # Transaction distribution
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321224 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321224 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2480349 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 43091000 # Layer occupancy (ticks)
+system.iobus.reqLayer0.occupancy 43092000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 99500 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 14500 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer7.occupancy 91000 # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy 91500 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer8.occupancy 648000 # Layer occupancy (ticks)
+system.iobus.reqLayer8.occupancy 654000 # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 21000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 3000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer20.occupancy 9500 # Layer occupancy (ticks)
+system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 8500 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 6193500 # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy 6200500 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer24.occupancy 33084000 # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy 32980000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 187182974 # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy 187207462 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 36770000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 36409 # number of replacements
-system.iocache.tags.tagsinuse 1.005274 # Cycle average of tags in use
+system.iocache.tags.tagsinuse 1.005413 # Cycle average of tags in use
system.iocache.tags.total_refs 30 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 36425 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0.000824 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 256605904000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide 1.005274 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide 0.062830 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.062830 # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle 256609976000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide 1.005413 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide 0.062838 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.062838 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.demand_misses::total 249 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 249 # number of overall misses
system.iocache.overall_misses::total 249 # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide 31308877 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 31308877 # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide 4546803097 # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total 4546803097 # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide 31308877 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 31308877 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide 31308877 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 31308877 # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide 31311877 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 31311877 # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide 4548827585 # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total 4548827585 # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide 31311877 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 31311877 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide 31311877 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 31311877 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide 249 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 125738.461847 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 125738.461847 # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125619.646277 # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 125619.646277 # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 125738.461847 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 125738.461847 # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 125738.461847 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 125738.461847 # average overall miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 125750.510040 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 125750.510040 # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125675.579086 # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 125675.579086 # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 125750.510040 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 125750.510040 # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 125750.510040 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 125750.510040 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.demand_mshr_misses::total 249 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide 249 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 249 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide 18858877 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 18858877 # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2735602611 # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total 2735602611 # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide 18858877 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 18858877 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide 18858877 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 18858877 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide 18861877 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 18861877 # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2737619112 # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total 2737619112 # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide 18861877 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 18861877 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide 18861877 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 18861877 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.999199 # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 75738.461847 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 75738.461847 # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75579.572068 # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75579.572068 # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 75738.461847 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 75738.461847 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 75738.461847 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 75738.461847 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 75750.510040 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 75750.510040 # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75635.284211 # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75635.284211 # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 75750.510040 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 75750.510040 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 75750.510040 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 75750.510040 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 34133 # Transaction distribution
-system.membus.trans_dist::ReadResp 67559 # Transaction distribution
+system.membus.trans_dist::ReadResp 67562 # Transaction distribution
system.membus.trans_dist::WriteReq 27585 # Transaction distribution
system.membus.trans_dist::WriteResp 27585 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 124961 # Transaction distribution
-system.membus.trans_dist::CleanEvict 7937 # Transaction distribution
+system.membus.trans_dist::WritebackDirty 124963 # Transaction distribution
+system.membus.trans_dist::CleanEvict 7938 # Transaction distribution
system.membus.trans_dist::UpgradeReq 4594 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
system.membus.trans_dist::ReadExReq 133523 # Transaction distribution
system.membus.trans_dist::ReadExResp 133523 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 33427 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 33430 # Transaction distribution
system.membus.trans_dist::InvalidateReq 36194 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2076 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 450075 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 557645 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 450084 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 557654 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72868 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 72868 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 630513 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 630522 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4152 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16402076 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16565481 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16402396 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16565801 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2315200 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2315200 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 18880681 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 18881001 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 513 # Total snoops (count)
-system.membus.snoop_fanout::samples 402367 # Request fanout histogram
+system.membus.snoop_fanout::samples 402383 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 402367 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 402383 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 402367 # Request fanout histogram
-system.membus.reqLayer0.occupancy 83710000 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 402383 # Request fanout histogram
+system.membus.reqLayer0.occupancy 83620000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 1748000 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 1745500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 873736629 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 873794635 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 978197500 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 978214250 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 1313623 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=134217728
-boot_loader=/dist/m5/system/binaries/boot_emm.arm
+boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
+dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/z/stever/hg/gem5/tests/halt.sh
+readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/dist/m5/system/disks/linux-aarch32-ael.img
+image_file=/home/stever/m5/aarch-system-2014-10/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=false
hit_latency=1
is_read_only=true
max_miss_count=0
clusivity=mostly_excl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=12
is_read_only=false
max_miss_count=0
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.cpu0.toL2Bus.snoop_filter
snoop_response_latency=1
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=false
hit_latency=1
is_read_only=true
max_miss_count=0
clusivity=mostly_excl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=12
is_read_only=false
max_miss_count=0
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.cpu1.toL2Bus.snoop_filter
snoop_response_latency=1
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=false
hit_latency=50
is_read_only=false
max_miss_count=0
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.toL2Bus.snoop_filter
snoop_response_latency=1
+Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual/simout
+Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 30 2015 02:49:35
-gem5 started Dec 30 2015 02:49:58
-gem5 executing on zizzer, pid 30293
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
+gem5 compiled Mar 15 2016 21:26:42
+gem5 started Mar 15 2016 21:34:31
+gem5 executing on phenom, pid 15964
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+info: kernel located at: /home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80008000
-info: Loading DTB file: /dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
+info: Loading DTB file: /home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-Exiting @ tick 2827514981500 because m5_exit instruction encountered
+Exiting @ tick 2837474672000 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 2.827476 # Number of seconds simulated
-sim_ticks 2827475548000 # Number of ticks simulated
-final_tick 2827475548000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.837475 # Number of seconds simulated
+sim_ticks 2837474672000 # Number of ticks simulated
+final_tick 2837474672000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 107187 # Simulator instruction rate (inst/s)
-host_op_rate 130034 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2524753544 # Simulator tick rate (ticks/s)
-host_mem_usage 623308 # Number of bytes of host memory used
-host_seconds 1119.90 # Real time elapsed on the host
-sim_insts 120039450 # Number of instructions simulated
-sim_ops 145624845 # Number of ops (including micro ops) simulated
+host_inst_rate 80224 # Simulator instruction rate (inst/s)
+host_op_rate 97291 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1891605778 # Simulator tick rate (ticks/s)
+host_mem_usage 603308 # Number of bytes of host memory used
+host_seconds 1500.04 # Real time elapsed on the host
+sim_insts 120338385 # Number of instructions simulated
+sim_ops 145939190 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker 1728 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 1298560 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 1281000 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher 8477568 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 384 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 174256 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 561876 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher 361024 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 1300544 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 1269544 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher 8448640 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 171296 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 573268 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher 376832 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 12157612 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 1298560 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 174256 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1472816 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 8578432 # Number of bytes written to this memory
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+system.physmem.bytes_inst_read::cpu0.inst 1300544 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 171296 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1471840 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 8572864 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
-system.physmem.bytes_written::total 8595996 # Number of bytes written to this memory
+system.physmem.bytes_written::total 8590428 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 27 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 22537 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 20536 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher 132462 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 6 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 2791 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 8800 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher 5641 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 22568 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 20357 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher 132010 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 2744 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 8978 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher 5888 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 192819 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 134038 # Number of write requests responded to by this memory
+system.physmem.num_reads::total 192594 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 133951 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 138429 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker 611 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 91 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 459265 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 453054 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher 2998282 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 136 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 61630 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 198720 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher 127684 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 4299812 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 459265 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 61630 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 520894 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 3033954 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 6198 # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 138342 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker 609 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 68 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 458346 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 447420 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher 2977521 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 68 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 60369 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 202035 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher 132805 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide 338 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 4279601 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 458346 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 60369 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 518715 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 3021301 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 6176 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 3040166 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 3033954 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 611 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 91 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 459265 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 459252 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher 2998282 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 136 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 61630 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 198734 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher 127684 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 7339978 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 192820 # Number of read requests accepted
-system.physmem.writeReqs 138429 # Number of write requests accepted
-system.physmem.readBursts 192820 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 138429 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 12329536 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 10880 # Total number of bytes read from write queue
-system.physmem.bytesWritten 8609152 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 12157676 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 8595996 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 170 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_write::total 3027491 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 3021301 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 609 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 68 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 458346 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 453596 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher 2977521 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 68 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 60369 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 202049 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher 132805 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 338 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 7307092 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 192595 # Number of read requests accepted
+system.physmem.writeReqs 138342 # Number of write requests accepted
+system.physmem.readBursts 192595 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 138342 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 12315840 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 10240 # Total number of bytes read from write queue
+system.physmem.bytesWritten 8603136 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 12143324 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 8590428 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 160 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 11576 # Per bank write bursts
-system.physmem.perBankRdBursts::1 11126 # Per bank write bursts
-system.physmem.perBankRdBursts::2 12008 # Per bank write bursts
-system.physmem.perBankRdBursts::3 12324 # Per bank write bursts
-system.physmem.perBankRdBursts::4 14472 # Per bank write bursts
-system.physmem.perBankRdBursts::5 12248 # Per bank write bursts
-system.physmem.perBankRdBursts::6 12234 # Per bank write bursts
-system.physmem.perBankRdBursts::7 12314 # Per bank write bursts
-system.physmem.perBankRdBursts::8 11863 # Per bank write bursts
-system.physmem.perBankRdBursts::9 12111 # Per bank write bursts
-system.physmem.perBankRdBursts::10 11927 # Per bank write bursts
-system.physmem.perBankRdBursts::11 10878 # Per bank write bursts
-system.physmem.perBankRdBursts::12 11632 # Per bank write bursts
-system.physmem.perBankRdBursts::13 12420 # Per bank write bursts
-system.physmem.perBankRdBursts::14 12142 # Per bank write bursts
-system.physmem.perBankRdBursts::15 11374 # Per bank write bursts
-system.physmem.perBankWrBursts::0 8212 # Per bank write bursts
-system.physmem.perBankWrBursts::1 8081 # Per bank write bursts
-system.physmem.perBankWrBursts::2 8787 # Per bank write bursts
-system.physmem.perBankWrBursts::3 8816 # Per bank write bursts
-system.physmem.perBankWrBursts::4 8301 # Per bank write bursts
-system.physmem.perBankWrBursts::5 8710 # Per bank write bursts
-system.physmem.perBankWrBursts::6 8720 # Per bank write bursts
-system.physmem.perBankWrBursts::7 8560 # Per bank write bursts
-system.physmem.perBankWrBursts::8 8226 # Per bank write bursts
-system.physmem.perBankWrBursts::9 8556 # Per bank write bursts
-system.physmem.perBankWrBursts::10 8511 # Per bank write bursts
-system.physmem.perBankWrBursts::11 8034 # Per bank write bursts
-system.physmem.perBankWrBursts::12 8394 # Per bank write bursts
-system.physmem.perBankWrBursts::13 8529 # Per bank write bursts
-system.physmem.perBankWrBursts::14 8449 # Per bank write bursts
-system.physmem.perBankWrBursts::15 7632 # Per bank write bursts
+system.physmem.perBankRdBursts::0 11930 # Per bank write bursts
+system.physmem.perBankRdBursts::1 11054 # Per bank write bursts
+system.physmem.perBankRdBursts::2 12038 # Per bank write bursts
+system.physmem.perBankRdBursts::3 12107 # Per bank write bursts
+system.physmem.perBankRdBursts::4 14171 # Per bank write bursts
+system.physmem.perBankRdBursts::5 12096 # Per bank write bursts
+system.physmem.perBankRdBursts::6 12498 # Per bank write bursts
+system.physmem.perBankRdBursts::7 12306 # Per bank write bursts
+system.physmem.perBankRdBursts::8 12126 # Per bank write bursts
+system.physmem.perBankRdBursts::9 12003 # Per bank write bursts
+system.physmem.perBankRdBursts::10 11820 # Per bank write bursts
+system.physmem.perBankRdBursts::11 10972 # Per bank write bursts
+system.physmem.perBankRdBursts::12 11787 # Per bank write bursts
+system.physmem.perBankRdBursts::13 12524 # Per bank write bursts
+system.physmem.perBankRdBursts::14 11749 # Per bank write bursts
+system.physmem.perBankRdBursts::15 11254 # Per bank write bursts
+system.physmem.perBankWrBursts::0 8457 # Per bank write bursts
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+system.physmem.perBankWrBursts::7 8687 # Per bank write bursts
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+system.physmem.perBankWrBursts::12 8500 # Per bank write bursts
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+system.physmem.perBankWrBursts::14 8126 # Per bank write bursts
+system.physmem.perBankWrBursts::15 7529 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 14 # Number of times write queue was full causing retry
-system.physmem.totGap 2827475264500 # Total gap between requests
+system.physmem.numWrRetry 17 # Number of times write queue was full causing retry
+system.physmem.totGap 2837474405000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 551 # Read request sizes (log2)
system.physmem.readPktSize::3 28 # Read request sizes (log2)
-system.physmem.readPktSize::4 3087 # Read request sizes (log2)
+system.physmem.readPktSize::4 3086 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 189154 # Read request sizes (log2)
+system.physmem.readPktSize::6 188930 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 4391 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 134038 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 61526 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 73950 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 12963 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 10011 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 8224 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 7155 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 6169 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 5077 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 4439 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 1284 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 803 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 555 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 257 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 222 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 133951 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 61287 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 73690 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 12995 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 10046 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 8300 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 7163 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 6190 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 5111 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 4461 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 1302 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 831 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 561 # What read queue length does an incoming req see
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-system.physmem.bytesPerActivate::mean 241.087472 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 135.747966 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 303.663203 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 46826 53.92% 53.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 16666 19.19% 73.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 5740 6.61% 79.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 3326 3.83% 83.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2736 3.15% 86.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1522 1.75% 88.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 967 1.11% 89.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 891 1.03% 90.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 8177 9.41% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 86851 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 6471 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 29.771133 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 578.111149 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047 6469 99.97% 99.97% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples 86799 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 241.004067 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 135.845956 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 303.218552 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 46693 53.79% 53.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 16731 19.28% 73.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 5770 6.65% 79.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 3383 3.90% 83.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2638 3.04% 86.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1583 1.82% 88.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 983 1.13% 89.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 925 1.07% 90.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 8093 9.32% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 86799 # Bytes accessed per row activation
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+system.physmem.rdPerTurnAround::mean 29.714330 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 6471 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 6471 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 20.787823 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 18.938766 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 13.675923 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 5299 81.89% 81.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 491 7.59% 89.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 106 1.64% 91.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 48 0.74% 91.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 55 0.85% 92.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 30 0.46% 93.17% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::44-47 20 0.31% 94.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 127 1.96% 96.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 8 0.12% 96.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 7 0.11% 96.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 12 0.19% 96.58% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::72-75 4 0.06% 97.87% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::80-83 78 1.21% 99.46% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::120-123 1 0.02% 99.66% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::132-135 1 0.02% 99.80% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::160-163 2 0.03% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 6471 # Writes before turning the bus around for reads
-system.physmem.totQLat 6248738813 # Total ticks spent queuing
-system.physmem.totMemAccLat 9860907563 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 963245000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 32435.71 # Average queueing delay per DRAM burst
-system.physmem.avgBusLat 4999.97 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 51185.61 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 4.36 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 3.04 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 4.30 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 3.04 # Average system write bandwidth in MiByte/s
+system.physmem.rdPerTurnAround::total 6476 # Reads before turning the bus around for writes
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+system.physmem.wrPerTurnAround::148-151 1 0.02% 99.94% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::total 6476 # Writes before turning the bus around for reads
+system.physmem.totQLat 6262539288 # Total ticks spent queuing
+system.physmem.totMemAccLat 9870695538 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 962175000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 32543.66 # Average queueing delay per DRAM burst
+system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat 51293.66 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 4.34 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 3.03 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 4.28 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 3.03 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.06 # Data bus utilization in percentage
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 25.73 # Average write queue length when enqueuing
-system.physmem.readRowHits 160837 # Number of row buffer hits during reads
-system.physmem.writeRowHits 79479 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 83.49 # Row buffer hit rate for reads
+system.physmem.avgWrQLen 22.64 # Average write queue length when enqueuing
+system.physmem.readRowHits 160629 # Number of row buffer hits during reads
+system.physmem.writeRowHits 79430 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 83.47 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 59.08 # Row buffer hit rate for writes
-system.physmem.avgGap 8535800.15 # Average gap between requests
-system.physmem.pageHitRate 73.45 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 333433800 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 181933125 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 766755600 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 441851760 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 184676952720 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 80138844765 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 1626188195250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 1892727967020 # Total energy per rank (pJ)
-system.physmem_0.averagePower 669.405562 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 2705208494482 # Time in different power states
-system.physmem_0.memoryStateTime::REF 94415360000 # Time in different power states
+system.physmem.avgGap 8574062.15 # Average gap between requests
+system.physmem.pageHitRate 73.44 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 333396000 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 181912500 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 765952200 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 442260000 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 185329943760 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 80518312575 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 1631853855750 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 1899425632785 # Total energy per rank (pJ)
+system.physmem_0.averagePower 669.407413 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 2714633882248 # Time in different power states
+system.physmem_0.memoryStateTime::REF 94749460000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 27851611768 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 28091326752 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 323159760 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 176327250 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 735906600 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 429824880 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 184676952720 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 80034809220 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 1626279454500 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 1892656434930 # Total energy per rank (pJ)
-system.physmem_1.averagePower 669.380263 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 2705361200169 # Time in different power states
-system.physmem_1.memoryStateTime::REF 94415360000 # Time in different power states
+system.physmem_1.actEnergy 322804440 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 176133375 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 735033000 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 428807520 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 185329943760 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 80062823295 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 1632253407750 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 1899308953140 # Total energy per rank (pJ)
+system.physmem_1.averagePower 669.366292 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 2715300909163 # Time in different power states
+system.physmem_1.memoryStateTime::REF 94749460000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 27698906081 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 27422902087 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 128 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 192 # Number of bytes read from this memory
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
-system.cpu0.branchPred.lookups 53905391 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 24966840 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 1032917 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 32635895 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 24264793 # Number of BTB hits
+system.cpu0.branchPred.lookups 53970528 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 25026545 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 1030924 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 32677551 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 24281541 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 74.350016 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 15570273 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 33772 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 74.306489 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 15568765 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 33847 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.walks 72512 # Table walker walks requested
-system.cpu0.dtb.walker.walksShort 72512 # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 26965 # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 21131 # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore 24416 # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples 48096 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean 467.596058 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev 2968.857131 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-8191 46825 97.36% 97.36% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::8192-16383 988 2.05% 99.41% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::16384-24575 122 0.25% 99.67% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::24576-32767 128 0.27% 99.93% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::32768-40959 9 0.02% 99.95% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::40960-49151 16 0.03% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::57344-65535 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walks 71872 # Table walker walks requested
+system.cpu0.dtb.walker.walksShort 71872 # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 26693 # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 21064 # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore 24115 # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples 47757 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean 506.909982 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev 3155.228311 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-8191 46441 97.24% 97.24% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::8192-16383 936 1.96% 99.20% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::16384-24575 182 0.38% 99.59% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::24576-32767 156 0.33% 99.91% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::32768-40959 14 0.03% 99.94% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::40960-49151 21 0.04% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::57344-65535 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::65536-73727 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::73728-81919 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::81920-90111 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::98304-106495 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::106496-114687 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::114688-122879 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 48096 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples 18855 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 10765.367277 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 9357.714559 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 7448.182030 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-32767 18771 99.55% 99.55% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::32768-65535 62 0.33% 99.88% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-163839 20 0.11% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::163840-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total 18855 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples 82990542356 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean 0.627007 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::stdev 0.496515 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0-1 82928307856 99.93% 99.93% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::2-3 44597000 0.05% 99.98% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::4-5 7454000 0.01% 99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::6-7 4958000 0.01% 99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::8-9 1796000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::10-11 1081000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::12-13 1137000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::14-15 1210500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::16-17 1000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 82990542356 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 5809 78.88% 78.88% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M 1555 21.12% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 7364 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 72512 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkWaitTime::total 47757 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples 18781 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 11082.663330 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 9588.241676 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 7811.113486 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-32767 18652 99.31% 99.31% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::32768-65535 107 0.57% 99.88% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-163839 11 0.06% 99.94% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::163840-196607 10 0.05% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total 18781 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples 75809851172 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean 0.731325 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev 0.459247 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0 20539595904 27.09% 27.09% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::1 55205651768 72.82% 99.91% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::2 30292500 0.04% 99.95% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::3 15753500 0.02% 99.98% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::4 4835000 0.01% 99.98% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::5 2801000 0.00% 99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::6 4041000 0.01% 99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::7 1434000 0.00% 99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::8 1051000 0.00% 99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::9 726000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::10 722500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::11 355500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::12 1232500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::13 309000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::14 147500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::15 902500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 75809851172 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K 5808 79.13% 79.13% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M 1532 20.87% 100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total 7340 # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 71872 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 72512 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7364 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 71872 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7340 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7364 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 79876 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7340 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total 79212 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 24390364 # DTB read hits
-system.cpu0.dtb.read_misses 61238 # DTB read misses
-system.cpu0.dtb.write_hits 18168033 # DTB write hits
-system.cpu0.dtb.write_misses 11274 # DTB write misses
+system.cpu0.dtb.read_hits 24452865 # DTB read hits
+system.cpu0.dtb.read_misses 61042 # DTB read misses
+system.cpu0.dtb.write_hits 18137868 # DTB write hits
+system.cpu0.dtb.write_misses 10830 # DTB write misses
system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 3796 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 307 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 2501 # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries 3798 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 179 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 2460 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 1008 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 24451602 # DTB read accesses
-system.cpu0.dtb.write_accesses 18179307 # DTB write accesses
+system.cpu0.dtb.perms_faults 1027 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 24513907 # DTB read accesses
+system.cpu0.dtb.write_accesses 18148698 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 42558397 # DTB hits
-system.cpu0.dtb.misses 72512 # DTB misses
-system.cpu0.dtb.accesses 42630909 # DTB accesses
+system.cpu0.dtb.hits 42590733 # DTB hits
+system.cpu0.dtb.misses 71872 # DTB misses
+system.cpu0.dtb.accesses 42662605 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.walker.walks 10837 # Table walker walks requested
-system.cpu0.itb.walker.walksShort 10837 # Table walker walks initiated with short descriptors
-system.cpu0.itb.walker.walksShortTerminationLevel::Level1 4138 # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6571 # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksSquashedBefore 128 # Table walks squashed before starting
-system.cpu0.itb.walker.walkWaitTime::samples 10709 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::mean 537.118312 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::stdev 2502.473477 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0-4095 10215 95.39% 95.39% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::4096-8191 152 1.42% 96.81% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::8192-12287 230 2.15% 98.95% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::12288-16383 65 0.61% 99.56% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::16384-20479 13 0.12% 99.68% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::20480-24575 22 0.21% 99.89% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::24576-28671 3 0.03% 99.92% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::28672-32767 4 0.04% 99.95% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::32768-36863 3 0.03% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::36864-40959 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walks 11904 # Table walker walks requested
+system.cpu0.itb.walker.walksShort 11904 # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.walksShortTerminationLevel::Level1 4233 # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6584 # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksSquashedBefore 1087 # Table walks squashed before starting
+system.cpu0.itb.walker.walkWaitTime::samples 10817 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::mean 600.397522 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::stdev 2698.053078 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0-4095 10265 94.90% 94.90% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::4096-8191 149 1.38% 96.27% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::8192-12287 271 2.51% 98.78% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::12288-16383 75 0.69% 99.47% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::16384-20479 17 0.16% 99.63% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::20480-24575 19 0.18% 99.81% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::24576-28671 9 0.08% 99.89% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::28672-32767 7 0.06% 99.95% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::32768-36863 2 0.02% 99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::36864-40959 2 0.02% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::40960-45055 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total 10709 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples 3004 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 12684.087883 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 11728.240532 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 5609.984659 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-16383 2772 92.28% 92.28% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::16384-32767 204 6.79% 99.07% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-49151 24 0.80% 99.87% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::49152-65535 3 0.10% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkWaitTime::total 10817 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples 3962 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 12538.112065 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 11491.228550 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 5924.134206 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-16383 3642 91.92% 91.92% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::16384-32767 274 6.92% 98.84% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-49151 42 1.06% 99.90% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::49152-65535 3 0.08% 99.97% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.03% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total 3004 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples 18565989416 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean 0.960744 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::stdev 0.194475 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0 729735500 3.93% 3.93% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1 17835412416 96.06% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::2 771500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walkCompletionTime::total 3962 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples 19975198824 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean 0.751864 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::stdev 0.432117 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0 4958102500 24.82% 24.82% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1 15015628824 75.17% 99.99% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::2 1397500 0.01% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3 70000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 18565989416 # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K 2530 87.97% 87.97% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::1M 346 12.03% 100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total 2876 # Table walker page sizes translated
+system.cpu0.itb.walker.walksPending::total 19975198824 # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K 2530 88.00% 88.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::1M 345 12.00% 100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total 2875 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10837 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10837 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 11904 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total 11904 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2876 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2876 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total 13713 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 74149475 # ITB inst hits
-system.cpu0.itb.inst_misses 10837 # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2875 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2875 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total 14779 # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits 74216434 # ITB inst hits
+system.cpu0.itb.inst_misses 11904 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 2177 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 2203 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 74160312 # ITB inst accesses
-system.cpu0.itb.hits 74149475 # DTB hits
-system.cpu0.itb.misses 10837 # DTB misses
-system.cpu0.itb.accesses 74160312 # DTB accesses
-system.cpu0.numCycles 211083313 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 74228338 # ITB inst accesses
+system.cpu0.itb.hits 74216434 # DTB hits
+system.cpu0.itb.misses 11904 # DTB misses
+system.cpu0.itb.accesses 74228338 # DTB accesses
+system.cpu0.numCycles 211032659 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles 21223431 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 200300307 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 53905391 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 39835066 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 180535577 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 5889142 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles 161904 # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles 68557 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles 388699 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 473615 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 104901 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 74149781 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 285289 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes 4990 # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples 205901255 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 1.189189 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 1.306256 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles 21140186 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 200489800 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 53970528 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 39850306 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 180538670 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 5902720 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles 164381 # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles 72575 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles 387139 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 466386 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 108060 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 74215735 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 285684 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes 6141 # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples 205828757 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 1.190746 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 1.306340 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 98579580 47.88% 47.88% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 31081229 15.10% 62.97% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 14947160 7.26% 70.23% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 61293286 29.77% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 98382336 47.80% 47.80% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 31160617 15.14% 62.94% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 14928225 7.25% 70.19% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 61357579 29.81% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 205901255 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.255375 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.948916 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 26485725 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 111121300 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 60553458 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 5155672 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 2585100 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 3186918 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 364053 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 158727281 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 4198172 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 2585100 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 35410452 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 13324080 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 85173312 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 56642777 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 12765534 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 141784227 # Number of instructions processed by rename
-system.cpu0.rename.SquashedInsts 1134861 # Number of squashed instructions processed by rename
-system.cpu0.rename.ROBFullEvents 1512506 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 171242 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents 63990 # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents 8419059 # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands 145923157 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 653859214 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 157615965 # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups 11018 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 133662052 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 12261102 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 2732054 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 2584956 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 22955704 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 25402528 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 19781437 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 1763657 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 2641114 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 138643116 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 1767872 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 136516412 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 515589 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 11570507 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 23858027 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 127265 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 205901255 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.663019 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 0.962571 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 205828757 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.255745 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 0.950042 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 26450347 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 110999505 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 60649256 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 5136264 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 2593385 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 3184080 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 362502 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 158814101 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 4185741 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 2593385 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 35368680 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 13285879 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 85120734 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 56726611 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 12733468 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 141845783 # Number of instructions processed by rename
+system.cpu0.rename.SquashedInsts 1133457 # Number of squashed instructions processed by rename
+system.cpu0.rename.ROBFullEvents 1506583 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 170458 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents 63498 # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents 8406258 # Number of times rename has blocked due to SQ full
+system.cpu0.rename.RenamedOperands 146030033 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 654050739 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 157600072 # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups 10971 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 133759652 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 12270378 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 2729976 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 2583213 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 22947942 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 25466090 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 19748562 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 1757357 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 2684729 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 138695125 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 1764118 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 136568956 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 514251 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 11572106 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 23832263 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 127429 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples 205828757 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 0.663508 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 0.962661 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 127147396 61.75% 61.75% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 34442708 16.73% 78.48% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 32032196 15.56% 94.04% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 11106549 5.39% 99.43% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 1172365 0.57% 100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 41 0.00% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 127035634 61.72% 61.72% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 34468527 16.75% 78.47% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 32041551 15.57% 94.03% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 11114901 5.40% 99.43% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 1168096 0.57% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 48 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 205901255 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 205828757 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 11130379 43.68% 43.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 74 0.00% 43.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 43.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 43.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 43.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 43.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 43.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 43.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 43.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 43.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 43.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 43.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 43.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 43.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 43.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 43.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 43.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 43.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 43.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 43.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 43.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 43.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 43.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 43.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 43.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 43.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 43.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 43.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 5931854 23.28% 66.95% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 8421894 33.05% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 11115121 43.73% 43.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 78 0.00% 43.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 0 0.00% 43.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 43.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 43.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 43.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 43.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 43.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 43.73% # attempts to use FU when none available
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+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 43.73% # attempts to use FU when none available
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+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 43.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 43.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 43.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 43.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 43.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 43.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 43.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 43.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 43.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 43.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 43.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 43.73% # attempts to use FU when none available
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+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 43.73% # attempts to use FU when none available
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+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 43.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 5928119 23.32% 67.05% # attempts to use FU when none available
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system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass 2315 0.00% 0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 91995657 67.39% 67.39% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 112676 0.08% 67.47% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 67.47% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 1 0.00% 67.47% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.47% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.47% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.47% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.47% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.47% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 67.47% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.47% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 67.47% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 67.47% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 67.47% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 67.47% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 67.47% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.47% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 67.47% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.47% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 67.47% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.47% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.47% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.47% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.47% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.47% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 8005 0.01% 67.48% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.48% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.48% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.48% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 25126496 18.41% 85.88% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 19271262 14.12% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 92017831 67.38% 67.38% # Type of FU issued
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+system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 67.46% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.46% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.46% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.46% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.46% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.46% # Type of FU issued
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+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.46% # Type of FU issued
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+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.46% # Type of FU issued
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+system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.46% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 67.46% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.46% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.46% # Type of FU issued
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+system.cpu0.iq.FU_type_0::SimdFloatMisc 8135 0.01% 67.47% # Type of FU issued
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+system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.47% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 25188018 18.44% 85.91% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 19239929 14.09% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 136516412 # Type of FU issued
-system.cpu0.iq.rate 0.646742 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 25484201 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.186675 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 504896258 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 151989102 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 132800903 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 37611 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 13286 # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses 11444 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 161974001 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 24297 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 381848 # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total 136568956 # Type of FU issued
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+system.cpu0.iq.fu_busy_rate 0.186133 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 504862433 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 152038807 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 132856114 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads 38448 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 13226 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses 11442 # Number of floating instruction queue wakeup accesses
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+system.cpu0.iq.fp_alu_accesses 25065 # Number of floating point alu accesses
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system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 2124335 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 2693 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 20966 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 1085688 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 2126828 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 2734 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 20764 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 1086115 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 122039 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 394742 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads 121849 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 393509 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 2585100 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 1946406 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 232120 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 140620014 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewSquashCycles 2593385 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 1923862 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 225428 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 140668675 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 25402528 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 19781437 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 904543 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 28856 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 178897 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 20966 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 314635 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 420768 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 735403 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 135358106 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 24646455 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 1085945 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewDispLoadInsts 25466090 # Number of dispatched load instructions
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+system.cpu0.iew.iewDispNonSpecInsts 902405 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents 28750 # Number of times the IQ has become full, causing a stall
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+system.cpu0.iew.predictedTakenIncorrect 314258 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 420576 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 734834 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 135413166 # Number of executed instructions
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system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 209026 # number of nop insts executed
-system.cpu0.iew.exec_refs 43717751 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 26098625 # Number of branches executed
-system.cpu0.iew.exec_stores 19071296 # Number of stores executed
-system.cpu0.iew.exec_rate 0.641254 # Inst execution rate
-system.cpu0.iew.wb_sent 134752568 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 132812347 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 67711784 # num instructions producing a value
-system.cpu0.iew.wb_consumers 109592899 # num instructions consuming a value
-system.cpu0.iew.wb_rate 0.629194 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.617848 # average fanout of values written-back
-system.cpu0.commit.commitSquashedInsts 10460496 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 1640607 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 673446 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 202593421 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 0.636705 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 1.338464 # Number of insts commited each cycle
+system.cpu0.iew.exec_nop 209432 # number of nop insts executed
+system.cpu0.iew.exec_refs 43749631 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 26148134 # Number of branches executed
+system.cpu0.iew.exec_stores 19040822 # Number of stores executed
+system.cpu0.iew.exec_rate 0.641669 # Inst execution rate
+system.cpu0.iew.wb_sent 134807850 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 132867556 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 67789134 # num instructions producing a value
+system.cpu0.iew.wb_consumers 109636664 # num instructions consuming a value
+system.cpu0.iew.wb_rate 0.629607 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.618307 # average fanout of values written-back
+system.cpu0.commit.commitSquashedInsts 10465399 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls 1636689 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts 672949 # The number of times a branch was mispredicted
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+system.cpu0.commit.committed_per_cycle::mean 0.637192 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 1.338822 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 140886474 69.54% 69.54% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 34073921 16.82% 86.36% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 12920125 6.38% 92.74% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 3397713 1.68% 94.41% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 4982698 2.46% 96.87% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 2731294 1.35% 98.22% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 1467251 0.72% 98.95% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 577318 0.28% 99.23% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 1556627 0.77% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 140790239 69.52% 69.52% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 34042188 16.81% 86.33% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 12969775 6.40% 92.74% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 3421790 1.69% 94.43% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 4963486 2.45% 96.88% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 2698624 1.33% 98.21% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 1492584 0.74% 98.95% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 576020 0.28% 99.23% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 1557145 0.77% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 202593421 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 106498180 # Number of instructions committed
-system.cpu0.commit.committedOps 128992320 # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total 202511851 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 106573853 # Number of instructions committed
+system.cpu0.commit.committedOps 129038976 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 41973942 # Number of memory references committed
-system.cpu0.commit.loads 23278193 # Number of loads committed
-system.cpu0.commit.membars 666414 # Number of memory barriers committed
-system.cpu0.commit.branches 25425121 # Number of branches committed
+system.cpu0.commit.refs 42001709 # Number of memory references committed
+system.cpu0.commit.loads 23339262 # Number of loads committed
+system.cpu0.commit.membars 664486 # Number of memory barriers committed
+system.cpu0.commit.branches 25472286 # Number of branches committed
system.cpu0.commit.fp_insts 11428 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 112579800 # Number of committed integer instructions.
-system.cpu0.commit.function_calls 4882067 # Number of function calls committed.
+system.cpu0.commit.int_insts 112576869 # Number of committed integer instructions.
+system.cpu0.commit.function_calls 4879585 # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu 86900184 67.37% 67.37% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult 110189 0.09% 67.45% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.45% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.45% # Class of committed instruction
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-system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.45% # Class of committed instruction
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-system.cpu0.committedOps 128840477 # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi 1.984867 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 1.984867 # CPI: Total CPI of All Threads
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-system.cpu0.ipc_total 0.503812 # IPC: Total IPC of All Threads
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+system.cpu0.dcache.demand_accesses::total 40198790 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data 40668416 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 40668416 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.030138 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.030138 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.113579 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total 0.113579 # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.326598 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total 0.326598 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.065615 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.065615 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051842 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051842 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.066157 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.066157 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.069165 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.069165 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14464.071956 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 14464.071956 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18408.834224 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 18408.834224 # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16012.970069 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16012.970069 # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 26462.679923 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 26462.679923 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17468.589452 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 17468.589452 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16513.038076 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 16513.038076 # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs 1294 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 5611564 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 45 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 212264 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs 28.755556 # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets 26.436720 # average number of cycles each access was blocked
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17387.535297 # average overall miss latency
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+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16439.417847 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 16439.417847 # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs 1356 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets 5556289 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs 48 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets 211720 # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs 28.250000 # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets 26.243572 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 752119 # number of writebacks
-system.cpu0.dcache.writebacks::total 752119 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 276058 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 276058 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1637615 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 1637615 # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 19358 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total 19358 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data 1913673 # number of demand (read+write) MSHR hits
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-system.cpu0.dcache.overall_mshr_hits::total 1913673 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 411180 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 411180 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 336757 # number of WriteReq MSHR misses
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-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 107638 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total 107638 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6783 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6783 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20265 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total 20265 # number of StoreCondReq MSHR misses
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-system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31813 # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28497 # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28497 # number of WriteReq MSHR uncacheable
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-system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60310 # number of overall MSHR uncacheable misses
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-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 109526500 # number of LoadLockedReq MSHR miss cycles
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-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12019710500 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.018050 # mshr miss rate for ReadReq accesses
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-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019371 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.228748 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.228748 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017036 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017036 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051828 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051828 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018622 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.018622 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.021055 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.021055 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12522.171555 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12522.171555 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22749.360524 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22749.360524 # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16668.072614 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16668.072614 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16147.206251 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16147.206251 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 25468.591167 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 25468.591167 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 750354 # number of writebacks
+system.cpu0.dcache.writebacks::total 750354 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 278216 # number of ReadReq MSHR hits
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+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016953 # mshr miss rate for LoadLockedReq accesses
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+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12501.551255 # average ReadReq mshr miss latency
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+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16183.796228 # average LoadLockedReq mshr miss latency
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system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17126.941042 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17126.941042 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17069.211819 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17069.211819 # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208222.283343 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208222.283343 # average ReadReq mshr uncacheable latency
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-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189336.947749 # average WriteReq mshr uncacheable latency
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-system.cpu0.icache.demand_mshr_miss_latency::total 13463982231 # number of demand (read+write) MSHR miss cycles
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system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
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system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 398120500 # number of ReadReq MSHR uncacheable cycles
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system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 398120500 # number of overall MSHR uncacheable cycles
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system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999951 # mshr miss rate for SCUpgradeReq accesses
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system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
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-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.042186 # mshr miss rate for ReadCleanReq accesses
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-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.042186 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.172696 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total 0.088851 # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.005649 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.007305 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.042186 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.172696 # mshr miss rate for overall accesses
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system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
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-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 21566.666667 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25966.592428 # average ReadReq mshr miss latency
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-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 82410.767063 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 26130.289096 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 26130.289096 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17910.809378 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17910.809378 # average SCUpgradeReq mshr miss latency
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-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56739.632206 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56739.632206 # average ReadExReq mshr miss latency
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-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62641.722809 # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28707.974399 # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28707.974399 # average ReadSharedReq mshr miss latency
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-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 21566.666667 # average overall mshr miss latency
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-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37246.367967 # average overall mshr miss latency
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-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 21566.666667 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 62641.722809 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37246.367967 # average overall mshr miss latency
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+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25964.367984 # average UpgradeReq mshr miss latency
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+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17902.280075 # average SCUpgradeReq mshr miss latency
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system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 132530.126498 # average ReadReq mshr uncacheable latency
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-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 194371.844214 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181722.829140 # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181722.829140 # average WriteReq mshr uncacheable latency
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system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 132530.126498 # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191475.368297 # average overall mshr uncacheable latency
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+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 188698.925659 # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.toL2Bus.snoop_filter.tot_requests 4287266 # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2165878 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 33429 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops 330817 # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 325927 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4890 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.trans_dist::ReadReq 121349 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp 2010442 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq 28497 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp 28497 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackDirty 741210 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackClean 1560498 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict 209521 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq 320891 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq 86097 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42565 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp 113963 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 15 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 26 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq 298891 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp 295589 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1315095 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq 595916 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq 3396 # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3950726 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2739036 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 31654 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 130125 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total 6851541 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 168343936 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 103984190 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 57496 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 243592 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total 272629214 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops 1021824 # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples 3257313 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean 0.120341 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev 0.329941 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_filter.tot_requests 4273775 # Total number of requests made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2158237 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 33113 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.snoop_filter.tot_snoops 328951 # Total number of snoops made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 324011 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4940 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.trans_dist::ReadReq 121086 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp 2004866 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq 28493 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp 28493 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackDirty 738565 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackClean 1555705 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict 211042 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq 317280 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq 85893 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42559 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp 113529 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 8 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 20 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq 299037 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp 295734 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1310580 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq 595787 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq 3352 # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3937175 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2734284 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 32274 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 130084 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total 6833817 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 167765632 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 103829284 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 59492 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 245052 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total 271899460 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops 1019958 # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples 3249040 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean 0.119755 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev 0.329325 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0 2870216 88.12% 88.12% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1 382207 11.73% 99.85% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2 4890 0.15% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0 2864891 88.18% 88.18% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1 379209 11.67% 99.85% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2 4940 0.15% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total 3257313 # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy 4288108443 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total 3249040 # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy 4275333939 # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy 113808525 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy 114905569 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy 1976208867 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy 1969437864 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy 1295252494 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy 1292879675 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy 17289481 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy 17411978 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy 69274405 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy 68871898 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu1.branchPred.lookups 3960492 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 2278371 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 239603 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 1992874 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 1474633 # Number of BTB hits
+system.cpu1.branchPred.lookups 4004674 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 2314065 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 245791 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 2020541 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 1485653 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 73.995295 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 786361 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 6053 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 73.527486 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 787487 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 5760 # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.dtb.walker.walks 15222 # Table walker walks requested
-system.cpu1.dtb.walker.walksShort 15222 # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 7935 # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 3046 # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore 4241 # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples 10981 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean 629.359803 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev 3543.870184 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-8191 10629 96.79% 96.79% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::8192-16383 248 2.26% 99.05% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::16384-24575 28 0.25% 99.31% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::24576-32767 51 0.46% 99.77% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::32768-40959 21 0.19% 99.96% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::40960-49151 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::49152-57343 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::81920-90111 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::90112-98303 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total 10981 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples 3183 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 11717.562048 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 10260.840497 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 8597.667676 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-16383 2739 86.05% 86.05% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::16384-32767 395 12.41% 98.46% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-49151 36 1.13% 99.59% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::49152-65535 3 0.09% 99.69% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::81920-98303 1 0.03% 99.72% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::98304-114687 6 0.19% 99.91% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-147455 2 0.06% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walks 15918 # Table walker walks requested
+system.cpu1.dtb.walker.walksShort 15918 # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8430 # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 3084 # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore 4404 # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples 11514 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean 608.824040 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev 3343.959858 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-4095 10992 95.47% 95.47% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::4096-8191 174 1.51% 96.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::8192-12287 180 1.56% 98.54% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::12288-16383 59 0.51% 99.05% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::16384-20479 13 0.11% 99.17% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::20480-24575 23 0.20% 99.37% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::24576-28671 5 0.04% 99.41% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::28672-32767 43 0.37% 99.78% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::32768-36863 5 0.04% 99.83% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::36864-40959 19 0.17% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::53248-57343 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total 11514 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples 3241 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 11888.614625 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 10569.570735 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 6910.032291 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-16383 2741 84.57% 84.57% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::16384-32767 457 14.10% 98.67% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-49151 35 1.08% 99.75% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::49152-65535 7 0.22% 99.97% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::147456-163839 1 0.03% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total 3183 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples 78410323560 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean 0.145148 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev 0.354804 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0 67057915756 85.52% 85.52% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::1 11337246804 14.46% 99.98% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::2 10462000 0.01% 99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::3 1830000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::4 951000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::5 350500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::6 990500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::7 120500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::8 94000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::9 139000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::10 14000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::11 14500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::12 22500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::13 12000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::14 7500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::15 153000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total 78410323560 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K 1233 73.13% 73.13% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M 453 26.87% 100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total 1686 # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 15222 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkCompletionTime::total 3241 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples 79820713468 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean 0.176976 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev 0.384068 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0 65723853356 82.34% 82.34% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::1 14081443112 17.64% 99.98% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::2 10527000 0.01% 99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::3 1956000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::4 949000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::5 421000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::6 996500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::7 109000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::8 31000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::9 149000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::10 36500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::11 15000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::12 23000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::13 37500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::14 15000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::15 151500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total 79820713468 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K 1248 73.11% 73.11% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M 459 26.89% 100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total 1707 # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 15918 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 15222 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1686 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 15918 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1707 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1686 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total 16908 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1707 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total 17625 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 3499603 # DTB read hits
-system.cpu1.dtb.read_misses 13349 # DTB read misses
-system.cpu1.dtb.write_hits 2989645 # DTB write hits
-system.cpu1.dtb.write_misses 1873 # DTB write misses
+system.cpu1.dtb.read_hits 3542440 # DTB read hits
+system.cpu1.dtb.read_misses 14035 # DTB read misses
+system.cpu1.dtb.write_hits 3032103 # DTB write hits
+system.cpu1.dtb.write_misses 1883 # DTB write misses
system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 1646 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 45 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 267 # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries 1668 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 48 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 364 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 252 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 3512952 # DTB read accesses
-system.cpu1.dtb.write_accesses 2991518 # DTB write accesses
+system.cpu1.dtb.read_accesses 3556475 # DTB read accesses
+system.cpu1.dtb.write_accesses 3033986 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 6489248 # DTB hits
-system.cpu1.dtb.misses 15222 # DTB misses
-system.cpu1.dtb.accesses 6504470 # DTB accesses
+system.cpu1.dtb.hits 6574543 # DTB hits
+system.cpu1.dtb.misses 15918 # DTB misses
+system.cpu1.dtb.accesses 6590461 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.walker.walks 6092 # Table walker walks requested
-system.cpu1.itb.walker.walksShort 6092 # Table walker walks initiated with short descriptors
-system.cpu1.itb.walker.walksShortTerminationLevel::Level1 3792 # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2256 # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksSquashedBefore 44 # Table walks squashed before starting
-system.cpu1.itb.walker.walkWaitTime::samples 6048 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::mean 194.031085 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::stdev 1498.555311 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0-4095 5941 98.23% 98.23% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::4096-8191 54 0.89% 99.12% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::8192-12287 35 0.58% 99.70% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::12288-16383 7 0.12% 99.82% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::16384-20479 3 0.05% 99.87% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::20480-24575 4 0.07% 99.93% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::24576-28671 2 0.03% 99.97% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::32768-36863 2 0.03% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total 6048 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples 878 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 11682.801822 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 10808.720287 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 5784.559551 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-8191 174 19.82% 19.82% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::8192-16383 650 74.03% 93.85% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::16384-24575 15 1.71% 95.56% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::24576-32767 28 3.19% 98.75% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-40959 5 0.57% 99.32% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::40960-49151 3 0.34% 99.66% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::49152-57343 1 0.11% 99.77% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::57344-65535 1 0.11% 99.89% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::73728-81919 1 0.11% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total 878 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples 13953243120 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::mean 0.946198 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::stdev 0.225667 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0 750840264 5.38% 5.38% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::1 13202275856 94.62% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::2 127000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total 13953243120 # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K 691 82.85% 82.85% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::1M 143 17.15% 100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total 834 # Table walker page sizes translated
+system.cpu1.itb.walker.walks 6720 # Table walker walks requested
+system.cpu1.itb.walker.walksShort 6720 # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walksShortTerminationLevel::Level1 4032 # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2330 # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksSquashedBefore 358 # Table walks squashed before starting
+system.cpu1.itb.walker.walkWaitTime::samples 6362 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::mean 276.642565 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::stdev 2156.603073 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0-4095 6226 97.86% 97.86% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::4096-8191 61 0.96% 98.82% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::8192-12287 38 0.60% 99.42% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::12288-16383 9 0.14% 99.56% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::16384-20479 2 0.03% 99.59% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::20480-24575 2 0.03% 99.62% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::24576-28671 16 0.25% 99.87% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::28672-32767 7 0.11% 99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::40960-45055 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total 6362 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples 1209 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 11358.974359 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 10416.514513 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 5795.722698 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-8191 235 19.44% 19.44% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::8192-16383 915 75.68% 95.12% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::16384-24575 19 1.57% 96.69% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::24576-32767 26 2.15% 98.84% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-40959 6 0.50% 99.34% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::40960-49151 4 0.33% 99.67% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::49152-57343 1 0.08% 99.75% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::57344-65535 1 0.08% 99.83% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::73728-81919 2 0.17% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total 1209 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples 15394402028 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::mean 0.620378 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::stdev 0.485344 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0 5844439264 37.96% 37.96% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::1 9549582764 62.03% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::2 380000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total 15394402028 # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K 707 83.08% 83.08% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M 144 16.92% 100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total 851 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6092 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6092 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6720 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6720 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 834 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total 834 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total 6926 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 7131526 # ITB inst hits
-system.cpu1.itb.inst_misses 6092 # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 851 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total 851 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total 7571 # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits 7202560 # ITB inst hits
+system.cpu1.itb.inst_misses 6720 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 898 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 915 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 335 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 341 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 7137618 # ITB inst accesses
-system.cpu1.itb.hits 7131526 # DTB hits
-system.cpu1.itb.misses 6092 # DTB misses
-system.cpu1.itb.accesses 7137618 # DTB accesses
-system.cpu1.numCycles 32153663 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 7209280 # ITB inst accesses
+system.cpu1.itb.hits 7202560 # DTB hits
+system.cpu1.itb.misses 6720 # DTB misses
+system.cpu1.itb.accesses 7209280 # DTB accesses
+system.cpu1.numCycles 32401432 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles 7900141 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 21121078 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 3960492 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 2260994 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 22525520 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 690384 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles 85873 # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles 36828 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles 183368 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 268596 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles 16764 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 7131220 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 101425 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes 2175 # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples 31362282 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 0.823323 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 1.195698 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles 8088351 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 21358444 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 4004674 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 2273140 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 22559668 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 709698 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles 89320 # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles 30191 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles 187953 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 272100 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 17466 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 7201931 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 106041 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes 2579 # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples 31599898 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 0.827450 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 1.197285 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 19419839 61.92% 61.92% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 4322960 13.78% 75.70% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 1360110 4.34% 80.04% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 6259373 19.96% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 19506083 61.73% 61.73% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 4380023 13.86% 75.59% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 1374078 4.35% 79.94% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 6339714 20.06% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 31362282 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.123174 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 0.656879 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 6476013 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 16288433 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 7449358 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 919688 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 228790 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 612596 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 118905 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 19752784 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 909327 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 228790 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 7703782 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 2255288 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 11537440 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 7124756 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 2512226 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 18734047 # Number of instructions processed by rename
-system.cpu1.rename.SquashedInsts 149896 # Number of squashed instructions processed by rename
-system.cpu1.rename.ROBFullEvents 201471 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 27483 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents 12915 # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents 1654980 # Number of times rename has blocked due to SQ full
-system.cpu1.rename.RenamedOperands 18476585 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 87682069 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 21592076 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 6 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 16547143 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 1929442 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 373208 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 305811 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 2461191 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 3733224 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 3288117 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 552829 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 458093 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 18036557 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 513632 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 17896075 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 81001 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 1765820 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 4051574 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 42199 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 31362282 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.570624 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 0.921463 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 31599898 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.123596 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 0.659182 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 6634182 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 16202869 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 7616699 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 910855 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 235293 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 619161 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 122169 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 20057728 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 931915 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 235293 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 7874159 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 2260152 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 11399374 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 7269011 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 2561909 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 19031053 # Number of instructions processed by rename
+system.cpu1.rename.SquashedInsts 153065 # Number of squashed instructions processed by rename
+system.cpu1.rename.ROBFullEvents 202989 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 28113 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents 12734 # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents 1710748 # Number of times rename has blocked due to SQ full
+system.cpu1.rename.RenamedOperands 18778237 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 89017572 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 21965763 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 3 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 16813455 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 1964782 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 364894 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 300103 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 2457661 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 3778976 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 3342332 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 554105 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 450807 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 18329749 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 508607 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 18175118 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 83980 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 1786298 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 4127648 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 40965 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 31599898 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 0.575164 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 0.924804 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 20726941 66.09% 66.09% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 5363186 17.10% 83.19% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 3506961 11.18% 94.37% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 1541817 4.92% 99.29% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 223369 0.71% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 20823460 65.90% 65.90% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 5404189 17.10% 83.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 3573075 11.31% 94.31% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 1571925 4.97% 99.28% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 227241 0.72% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 8 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 31362282 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 31599898 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 1114950 27.66% 27.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 668 0.02% 27.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv 0 0.00% 27.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd 0 0.00% 27.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp 0 0.00% 27.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt 0 0.00% 27.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult 0 0.00% 27.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv 0 0.00% 27.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 27.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd 0 0.00% 27.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 27.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu 0 0.00% 27.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp 0 0.00% 27.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt 0 0.00% 27.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc 0 0.00% 27.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult 0 0.00% 27.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 27.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift 0 0.00% 27.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 27.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 27.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 27.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 27.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 27.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 27.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 27.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 27.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 27.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 27.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 1322557 32.82% 60.50% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 1592153 39.50% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 1136230 27.62% 27.62% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 665 0.02% 27.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv 0 0.00% 27.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 27.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 27.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 27.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 27.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv 0 0.00% 27.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 27.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 27.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 27.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 27.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 27.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 27.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 27.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 27.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 27.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 27.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 27.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 27.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 27.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 27.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 27.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 27.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 27.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 27.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 27.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 27.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 1332872 32.40% 60.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 1643603 39.96% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass 24 0.00% 0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 11018686 61.57% 61.57% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 25379 0.14% 61.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 61.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 61.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 3144 0.02% 61.73% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.73% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.73% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.73% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 3679682 20.56% 82.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 3169160 17.71% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 11198655 61.62% 61.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 26151 0.14% 61.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 61.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 61.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 3134 0.02% 61.78% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.78% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.78% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.78% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 3723841 20.49% 82.27% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 3223313 17.73% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 17896075 # Type of FU issued
-system.cpu1.iq.rate 0.556580 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 4030328 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.225207 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 71265761 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 20324002 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 17511405 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.FU_type_0::total 18175118 # Type of FU issued
+system.cpu1.iq.rate 0.560936 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 4113370 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.226319 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 72147484 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 20632628 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 17784107 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 21926379 # Number of integer alu accesses
+system.cpu1.iq.int_alu_accesses 22288464 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 71343 # Number of loads that had data forwarded from stores
+system.cpu1.iew.lsq.thread0.forwLoads 72358 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 337548 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 508 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 8028 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 276059 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 345916 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 595 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 8007 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 274863 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 35249 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 51219 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads 35609 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 53341 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 228790 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 526676 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 150264 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 18566765 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewSquashCycles 235293 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 517337 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 146372 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 18855001 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 3733224 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 3288117 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 271755 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 6489 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 137973 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 8028 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 29675 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 101337 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 131012 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 17697567 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 3606675 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 183289 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewDispLoadInsts 3778976 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 3342332 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 266125 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 6620 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 133975 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 8007 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 29726 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 104216 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 133942 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 17973018 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 3647924 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 186185 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 16576 # number of nop insts executed
-system.cpu1.iew.exec_refs 6722071 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 2541515 # Number of branches executed
-system.cpu1.iew.exec_stores 3115396 # Number of stores executed
-system.cpu1.iew.exec_rate 0.550406 # Inst execution rate
-system.cpu1.iew.wb_sent 17598968 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 17511405 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 8692607 # num instructions producing a value
-system.cpu1.iew.wb_consumers 13471004 # num instructions consuming a value
-system.cpu1.iew.wb_rate 0.544616 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.645283 # average fanout of values written-back
-system.cpu1.commit.commitSquashedInsts 1597357 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 471433 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 123201 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 31002866 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.541480 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.295585 # Number of insts commited each cycle
+system.cpu1.iew.exec_nop 16645 # number of nop insts executed
+system.cpu1.iew.exec_refs 6817035 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 2587014 # Number of branches executed
+system.cpu1.iew.exec_stores 3169111 # Number of stores executed
+system.cpu1.iew.exec_rate 0.554698 # Inst execution rate
+system.cpu1.iew.wb_sent 17871186 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 17784107 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 8844810 # num instructions producing a value
+system.cpu1.iew.wb_consumers 13737258 # num instructions consuming a value
+system.cpu1.iew.wb_rate 0.548868 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.643856 # average fanout of values written-back
+system.cpu1.commit.commitSquashedInsts 1617174 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 467642 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 126235 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 31232048 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 0.546078 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 1.299760 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 22873291 73.78% 73.78% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 4864873 15.69% 89.47% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 1409236 4.55% 94.02% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 529319 1.71% 95.72% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 438451 1.41% 97.14% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 294402 0.95% 98.09% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 179192 0.58% 98.66% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 97652 0.31% 98.98% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 316450 1.02% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 22985371 73.60% 73.60% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 4918403 15.75% 89.34% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 1437568 4.60% 93.95% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 538908 1.73% 95.67% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 452299 1.45% 97.12% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 299028 0.96% 98.08% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 181643 0.58% 98.66% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 99960 0.32% 98.98% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 318868 1.02% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 31002866 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 13696177 # Number of instructions committed
-system.cpu1.commit.committedOps 16787432 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 31232048 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 13919439 # Number of instructions committed
+system.cpu1.commit.committedOps 17055121 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 6407734 # Number of memory references committed
-system.cpu1.commit.loads 3395676 # Number of loads committed
-system.cpu1.commit.membars 190902 # Number of memory barriers committed
-system.cpu1.commit.branches 2419020 # Number of branches committed
+system.cpu1.commit.refs 6500529 # Number of memory references committed
+system.cpu1.commit.loads 3433060 # Number of loads committed
+system.cpu1.commit.membars 191637 # Number of memory barriers committed
+system.cpu1.commit.branches 2464934 # Number of branches committed
system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 14992163 # Number of committed integer instructions.
-system.cpu1.commit.function_calls 410100 # Number of function calls committed.
+system.cpu1.commit.int_insts 15221061 # Number of committed integer instructions.
+system.cpu1.commit.function_calls 413171 # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu 10351952 61.66% 61.66% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult 24602 0.15% 61.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv 0 0.00% 61.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 61.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 61.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 61.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult 0 0.00% 61.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 61.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 61.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 61.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 61.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 61.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 61.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 61.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 61.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult 0 0.00% 61.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 61.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift 0 0.00% 61.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 61.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 61.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 61.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 61.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 61.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 61.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 61.81% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc 3144 0.02% 61.83% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 61.83% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.83% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.83% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead 3395676 20.23% 82.06% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite 3012058 17.94% 100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu 10526100 61.72% 61.72% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult 25358 0.15% 61.87% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv 0 0.00% 61.87% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 61.87% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 61.87% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 61.87% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult 0 0.00% 61.87% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 61.87% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 61.87% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 61.87% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 61.87% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 61.87% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 61.87% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 61.87% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 61.87% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult 0 0.00% 61.87% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 61.87% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift 0 0.00% 61.87% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 61.87% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 61.87% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 61.87% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 61.87% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 61.87% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 61.87% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 61.87% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc 3134 0.02% 61.89% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 61.89% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.89% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.89% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead 3433060 20.13% 82.01% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite 3067469 17.99% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total 16787432 # Class of committed instruction
-system.cpu1.commit.bw_lim_events 316450 # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads 48173976 # The number of ROB reads
-system.cpu1.rob.rob_writes 37125010 # The number of ROB writes
-system.cpu1.timesIdled 52987 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 791381 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 5622225995 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 13693113 # Number of Instructions Simulated
-system.cpu1.committedOps 16784368 # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi 2.348163 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 2.348163 # CPI: Total CPI of All Threads
-system.cpu1.ipc 0.425865 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.425865 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 19830637 # number of integer regfile reads
-system.cpu1.int_regfile_writes 11457060 # number of integer regfile writes
-system.cpu1.cc_regfile_reads 63567667 # number of cc regfile reads
-system.cpu1.cc_regfile_writes 5386626 # number of cc regfile writes
-system.cpu1.misc_regfile_reads 46959699 # number of misc regfile reads
-system.cpu1.misc_regfile_writes 351107 # number of misc regfile writes
-system.cpu1.dcache.tags.replacements 146387 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 464.874328 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 5757831 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 146736 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 39.239389 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 89642414500 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 464.874328 # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data 0.907958 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total 0.907958 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2 344 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024 0.681641 # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses 12687956 # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses 12687956 # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data 3034292 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 3034292 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 2492465 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 2492465 # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data 42455 # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total 42455 # number of SoftPFReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 70401 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 70401 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data 61757 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 61757 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 5526757 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 5526757 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 5569212 # number of overall hits
-system.cpu1.dcache.overall_hits::total 5569212 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data 176347 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 176347 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 307156 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 307156 # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data 23291 # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total 23291 # number of SoftPFReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17298 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 17298 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23328 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 23328 # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data 483503 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 483503 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data 506794 # number of overall misses
-system.cpu1.dcache.overall_misses::total 506794 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3277543500 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 3277543500 # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 10809748445 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 10809748445 # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 356539500 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total 356539500 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 632211000 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total 632211000 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1062000 # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1062000 # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 14087291945 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 14087291945 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 14087291945 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 14087291945 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 3210639 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 3210639 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data 2799621 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 2799621 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 65746 # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total 65746 # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 87699 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total 87699 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 85085 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total 85085 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data 6010260 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 6010260 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data 6076006 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 6076006 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.054926 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total 0.054926 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.109713 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total 0.109713 # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.354257 # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total 0.354257 # miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.197243 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.197243 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.274173 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total 0.274173 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data 0.080446 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total 0.080446 # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data 0.083409 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total 0.083409 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 18585.762729 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 18585.762729 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 35193.023887 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 35193.023887 # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20611.602497 # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20611.602497 # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27100.951646 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27100.951646 # average StoreCondReq miss latency
+system.cpu1.commit.op_class_0::total 17055121 # Class of committed instruction
+system.cpu1.commit.bw_lim_events 318868 # number cycles where commit BW limit reached
+system.cpu1.rob.rob_reads 48693377 # The number of ROB reads
+system.cpu1.rob.rob_writes 37704462 # The number of ROB writes
+system.cpu1.timesIdled 54449 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles 801534 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles 5641978926 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts 13916375 # Number of Instructions Simulated
+system.cpu1.committedOps 17052057 # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi 2.328295 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 2.328295 # CPI: Total CPI of All Threads
+system.cpu1.ipc 0.429499 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 0.429499 # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads 20171144 # number of integer regfile reads
+system.cpu1.int_regfile_writes 11610273 # number of integer regfile writes
+system.cpu1.cc_regfile_reads 64505089 # number of cc regfile reads
+system.cpu1.cc_regfile_writes 5511942 # number of cc regfile writes
+system.cpu1.misc_regfile_reads 46426595 # number of misc regfile reads
+system.cpu1.misc_regfile_writes 345736 # number of misc regfile writes
+system.cpu1.dcache.tags.replacements 150581 # number of replacements
+system.cpu1.dcache.tags.tagsinuse 478.131368 # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs 5834465 # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs 150940 # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs 38.654200 # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle 89605225500 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data 478.131368 # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data 0.933850 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total 0.933850 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024 359 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2 351 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024 0.701172 # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses 12862288 # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses 12862288 # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data 3070880 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total 3070880 # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data 2527415 # number of WriteReq hits
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+system.cpu1.dcache.SoftPFReq_hits::cpu1.data 42897 # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total 42897 # number of SoftPFReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 70538 # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total 70538 # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data 61948 # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total 61948 # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data 5598295 # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total 5598295 # number of demand (read+write) hits
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+system.cpu1.dcache.overall_hits::total 5641192 # number of overall hits
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+system.cpu1.dcache.ReadReq_misses::total 179007 # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data 316590 # number of WriteReq misses
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+system.cpu1.dcache.SoftPFReq_misses::cpu1.data 23941 # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total 23941 # number of SoftPFReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17385 # number of LoadLockedReq misses
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+system.cpu1.dcache.StoreCondReq_misses::total 23392 # number of StoreCondReq misses
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+system.cpu1.dcache.demand_misses::total 495597 # number of demand (read+write) misses
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+system.cpu1.dcache.overall_misses::total 519538 # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3308418500 # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total 3308418500 # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 11036821442 # number of WriteReq miss cycles
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+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 357595000 # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total 357595000 # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 636551500 # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total 636551500 # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 787500 # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total 787500 # number of StoreCondFailReq miss cycles
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+system.cpu1.dcache.demand_miss_latency::total 14345239942 # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data 14345239942 # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total 14345239942 # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data 3249887 # number of ReadReq accesses(hits+misses)
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+system.cpu1.dcache.WriteReq_accesses::total 2844005 # number of WriteReq accesses(hits+misses)
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+system.cpu1.dcache.SoftPFReq_accesses::total 66838 # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 87923 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total 87923 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 85340 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total 85340 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data 6093892 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total 6093892 # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data 6160730 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total 6160730 # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.055081 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total 0.055081 # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.111318 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total 0.111318 # miss rate for WriteReq accesses
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+system.cpu1.dcache.SoftPFReq_miss_rate::total 0.358194 # miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.197730 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.197730 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.274104 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total 0.274104 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data 0.081327 # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total 0.081327 # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data 0.084331 # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total 0.084331 # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 18482.062154 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 18482.062154 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34861.560510 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 34861.560510 # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20569.168824 # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20569.168824 # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27212.358926 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27212.358926 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29135.893562 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 29135.893562 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 27796.879886 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 27796.879886 # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs 331 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets 1608332 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs 34 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets 29276 # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.735294 # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets 54.936877 # average number of cycles each access was blocked
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 28945.372837 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 28945.372837 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 27611.531672 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 27611.531672 # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs 640 # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets 1636825 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs 27 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets 30227 # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs 23.703704 # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets 54.151090 # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 146387 # number of writebacks
-system.cpu1.dcache.writebacks::total 146387 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 61765 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total 61765 # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 230665 # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total 230665 # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12462 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12462 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data 292430 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total 292430 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data 292430 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total 292430 # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 114582 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 114582 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 76491 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 76491 # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 22561 # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total 22561 # number of SoftPFReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4836 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4836 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23328 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total 23328 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 191073 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 191073 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data 213634 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 213634 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3393 # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3393 # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2735 # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2735 # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 6128 # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total 6128 # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1708391000 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1708391000 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2716718455 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2716718455 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 399807500 # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 399807500 # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 95324000 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 95324000 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 608894000 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 608894000 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1051000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1051000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4425109455 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 4425109455 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4824916955 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 4824916955 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 456207000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 456207000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 319373000 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 319373000 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 775580000 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 775580000 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035688 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035688 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027322 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027322 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.343154 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.343154 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.055143 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.055143 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.274173 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.274173 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031791 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.031791 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035160 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.035160 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14909.767677 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14909.767677 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35516.837994 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 35516.837994 # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17721.178139 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17721.178139 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 19711.331679 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 19711.331679 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26101.423182 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26101.423182 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks 150582 # number of writebacks
+system.cpu1.dcache.writebacks::total 150582 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 62660 # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total 62660 # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 238202 # number of WriteReq MSHR hits
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+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12477 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12477 # number of LoadLockedReq MSHR hits
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+system.cpu1.dcache.demand_mshr_hits::total 300862 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data 300862 # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total 300862 # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 116347 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total 116347 # number of ReadReq MSHR misses
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+system.cpu1.dcache.WriteReq_mshr_misses::total 78388 # number of WriteReq MSHR misses
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+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 19439.792176 # average LoadLockedReq mshr miss latency
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system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
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-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23159.260885 # average overall mshr miss latency
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-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22584.967538 # average overall mshr miss latency
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-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 134455.349248 # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 116772.577697 # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 116772.577697 # average WriteReq mshr uncacheable latency
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-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8614.935533 # average overall mshr miss latency
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system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage 47159 # number of prefetches not generated due to page crossing
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system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
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-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16048.723898 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14097.472924 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15285.310734 # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 56508.442098 # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 56508.442098 # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20261.416638 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20261.416638 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18573.137272 # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18573.137272 # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 484250 # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 484250 # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 46945.824841 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 46945.824841 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 54545.169535 # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 54545.169535 # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16810.473866 # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16810.473866 # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16048.723898 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14097.472924 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 54545.169535 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 26585.614107 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29160.141220 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16048.723898 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14097.472924 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 54545.169535 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26585.614107 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 56508.442098 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33295.843646 # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 125543.689320 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 126367.079281 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 126342.820366 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 109185.007678 # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 109185.007678 # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 125543.689320 # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 118698.514360 # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 118811.666827 # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total 0.164694 # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15210.706150 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14588.447653 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14969.972067 # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 58071.731431 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 58071.731431 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20291.668101 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20291.668101 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18685.776538 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18685.776538 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 46971.492480 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 46971.492480 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 52870.063660 # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 52870.063660 # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16854.748616 # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16854.748616 # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15210.706150 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14588.447653 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 52870.063660 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 26688.570934 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29164.193344 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15210.706150 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14588.447653 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 52870.063660 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26688.570934 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 58071.731431 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33623.968463 # average overall mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 125039.215686 # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134123.812643 # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 133830.110935 # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117128.575280 # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117128.575280 # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 125039.215686 # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 126624.633053 # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 126595.579411 # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.toL2Bus.snoop_filter.tot_requests 1486808 # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests 750931 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12198 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops 171006 # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 168745 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2261 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.trans_dist::ReadReq 25827 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp 751423 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq 2735 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp 2735 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackDirty 116660 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackClean 601248 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict 88861 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq 22992 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq 70535 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41533 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp 84868 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 17 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 26 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq 55768 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp 52923 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq 545548 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq 220317 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateReq 68 # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1636337 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 718931 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 15307 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 26144 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total 2396719 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 69798960 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24301530 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 28012 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 48468 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total 94176970 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops 362810 # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples 1100696 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean 0.175235 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev 0.385533 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_filter.tot_requests 1522873 # Total number of requests made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_requests 769340 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12387 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.snoop_filter.tot_snoops 172724 # Total number of snoops made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 169892 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2832 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.trans_dist::ReadReq 26445 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp 767980 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq 2411 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp 2411 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackDirty 120637 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackClean 616293 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict 90499 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq 23834 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq 71062 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41585 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 84984 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 20 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq 57226 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp 54414 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq 559261 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq 224052 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateReq 24 # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1677474 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 729934 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 16099 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 27235 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total 2450742 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 71554208 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24804884 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 29628 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 50548 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total 96439268 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops 367369 # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples 1124026 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean 0.173917 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.385628 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0 910077 82.68% 82.68% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1 188358 17.11% 99.79% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2 2261 0.21% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0 931371 82.86% 82.86% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1 189823 16.89% 99.75% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2 2832 0.25% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total 1100696 # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy 1446777487 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total 1124026 # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy 1482640983 # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy 80382983 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy 79919843 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy 818547754 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy 839140704 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy 317524641 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy 323172006 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy 8315477 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy 8701980 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy 14039475 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy 14614966 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.trans_dist::ReadReq 31018 # Transaction distribution
system.iobus.trans_dist::ReadResp 31018 # Transaction distribution
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2484060 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 40401000 # Layer occupancy (ticks)
+system.iobus.reqLayer0.occupancy 40406500 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 111000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 326000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy 323500 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 31500 # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy 31000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 16500 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer7.occupancy 91000 # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy 89500 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer8.occupancy 591500 # Layer occupancy (ticks)
+system.iobus.reqLayer8.occupancy 580500 # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 22000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy 21500 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks)
+system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 6158500 # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy 6147500 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer24.occupancy 34127000 # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy 34101000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 187100472 # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy 187141705 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 84732000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 36776000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 36458 # number of replacements
-system.iocache.tags.tagsinuse 14.549835 # Cycle average of tags in use
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-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 72275.160600 # average UpgradeReq mshr miss latency
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-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 129170.252729 # average ReadSharedReq mshr miss latency
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system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 114529.960053 # average ReadReq mshr uncacheable latency
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-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107533.980583 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 108463.275516 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 170176.664396 # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164718.620872 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 92178.247166 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 158366.228388 # average WriteReq mshr uncacheable latency
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system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 114529.960053 # average overall mshr uncacheable latency
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-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107533.980583 # average overall mshr uncacheable latency
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system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 38310 # Transaction distribution
-system.membus.trans_dist::ReadResp 209204 # Transaction distribution
-system.membus.trans_dist::WriteReq 31232 # Transaction distribution
-system.membus.trans_dist::WriteResp 31232 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 134038 # Transaction distribution
-system.membus.trans_dist::CleanEvict 15311 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 73680 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 40459 # Transaction distribution
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+system.membus.trans_dist::WriteReq 30904 # Transaction distribution
+system.membus.trans_dist::WriteResp 30904 # Transaction distribution
+system.membus.trans_dist::WritebackDirty 133951 # Transaction distribution
+system.membus.trans_dist::CleanEvict 15326 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 74253 # Transaction distribution
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system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution
-system.membus.trans_dist::ReadExReq 38317 # Transaction distribution
-system.membus.trans_dist::ReadExResp 18829 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 170895 # Transaction distribution
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system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107932 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 40 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14998 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 641245 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 764215 # Packet count per connected master and slave (bytes)
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+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 641454 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72949 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 72949 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 837164 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 836077 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162812 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 320 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29996 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18435464 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 18628592 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27404 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18415544 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 18606080 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 20946736 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 119950 # Total snoops (count)
-system.membus.snoop_fanout::samples 578486 # Request fanout histogram
+system.membus.pkt_size::total 20924224 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 120501 # Total snoops (count)
+system.membus.snoop_fanout::samples 578275 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 578486 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 578275 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 578486 # Request fanout histogram
-system.membus.reqLayer0.occupancy 82005000 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 578275 # Request fanout histogram
+system.membus.reqLayer0.occupancy 81956500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 27500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 12415490 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 11341491 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 979073321 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 978727928 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 1095686984 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 1093472967 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 1343381 # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy 1338381 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests 986513 # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests 532898 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests 144750 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops 20257 # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops 19380 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops 877 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq 38313 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 474331 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 31232 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 31232 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty 393751 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 116065 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 108396 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 43566 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 151962 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq 26 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp 26 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 49800 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 49800 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 436034 # Transaction distribution
+system.toL2Bus.snoop_filter.tot_requests 990338 # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests 533884 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests 147185 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops 20219 # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops 19375 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops 844 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.trans_dist::ReadReq 37992 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 475955 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 30904 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 30904 # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty 393750 # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict 117353 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 108673 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 43588 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 152261 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq 20 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp 20 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 50171 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 50171 # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq 437979 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1264986 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 256361 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 1521347 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 35072434 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 3807934 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 38880368 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 439648 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 904500 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 0.339928 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.475727 # Request fanout histogram
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1264500 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 260756 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 1525256 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 35008152 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 3970344 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 38978496 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 440946 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 906523 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 0.342627 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.476546 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 597912 66.10% 66.10% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 305711 33.80% 99.90% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 877 0.10% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 596768 65.83% 65.83% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 308911 34.08% 99.91% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 844 0.09% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 904500 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 870687772 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 906523 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 872587716 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 356119 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 657373534 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 657818310 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 203531555 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 206175111 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 1892 # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce 1860 # number of quiesce instructions executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 2705 # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce 2731 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm
+boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
+dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
+exit_on_work_items=false
flags_addr=469827632
gic_cpu_addr=738205696
have_large_asid_64=false
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
+readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/work/gem5/dist/disks/linux-aarch32-ael.img
+image_file=/home/stever/m5/aarch-system-2014-10/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=false
hit_latency=50
is_read_only=false
max_miss_count=0
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
+Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3/simout
+Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 4 2015 11:13:17
-gem5 started Dec 4 2015 13:05:09
-gem5 executing on e104799-lin, pid 8022
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3
+gem5 compiled Mar 15 2016 21:26:42
+gem5 started Mar 15 2016 21:34:35
+gem5 executing on phenom, pid 15973
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+info: kernel located at: /home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80008000
-info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
+info: Loading DTB file: /home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-Exiting @ tick 2832912592000 because m5_exit instruction encountered
+Exiting @ tick 2832922792000 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 2.832892 # Number of seconds simulated
-sim_ticks 2832892490000 # Number of ticks simulated
-final_tick 2832892490000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.832923 # Number of seconds simulated
+sim_ticks 2832922792000 # Number of ticks simulated
+final_tick 2832922792000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 124603 # Simulator instruction rate (inst/s)
-host_op_rate 151132 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 3121592879 # Simulator tick rate (ticks/s)
-host_mem_usage 587312 # Number of bytes of host memory used
-host_seconds 907.52 # Real time elapsed on the host
-sim_insts 113079496 # Number of instructions simulated
-sim_ops 137154742 # Number of ops (including micro ops) simulated
+host_inst_rate 79525 # Simulator instruction rate (inst/s)
+host_op_rate 96457 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1991756148 # Simulator tick rate (ticks/s)
+host_mem_usage 563904 # Number of bytes of host memory used
+host_seconds 1422.32 # Real time elapsed on the host
+sim_insts 113110851 # Number of instructions simulated
+sim_ops 137193114 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 1408 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 512 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 1315968 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9383464 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 1316352 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9383208 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 10702248 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 1315968 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1315968 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7997504 # Number of bytes written to this memory
+system.physmem.bytes_read::total 10702440 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 1316352 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1316352 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7997632 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
-system.physmem.bytes_written::total 8015028 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker 21 # Number of read requests responded to by this memory
+system.physmem.bytes_written::total 8015156 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker 22 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 8 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 22809 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 147137 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 22815 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 147133 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 169990 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 124961 # Number of write requests responded to by this memory
+system.physmem.num_reads::total 169993 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 124963 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 129342 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker 474 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 129344 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker 497 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 181 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 464532 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3312326 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 464662 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3312200 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 339 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 3777852 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 464532 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 464532 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 2823088 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 3777879 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 464662 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 464662 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 2823103 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 6186 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2829274 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 2823088 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 474 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total 2829289 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 2823103 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 497 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 181 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 464532 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 3318512 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 464662 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 3318386 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 339 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 6607125 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 169991 # Number of read requests accepted
-system.physmem.writeReqs 129342 # Number of write requests accepted
-system.physmem.readBursts 169991 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 129342 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 10867968 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 11456 # Total number of bytes read from write queue
+system.physmem.bw_total::total 6607168 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 169994 # Number of read requests accepted
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+system.physmem.bytesReadDRAM 10868544 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 11072 # Total number of bytes read from write queue
system.physmem.bytesWritten 8027328 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 10702312 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 8015028 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 179 # Number of DRAM read bursts serviced by the write queue
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+system.physmem.servicedByWrQ 173 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 11395 # Per bank write bursts
system.physmem.perBankRdBursts::1 10614 # Per bank write bursts
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system.physmem.perBankRdBursts::3 11362 # Per bank write bursts
system.physmem.perBankRdBursts::4 12761 # Per bank write bursts
system.physmem.perBankRdBursts::5 10093 # Per bank write bursts
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system.physmem.perBankRdBursts::15 10086 # Per bank write bursts
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system.physmem.perBankWrBursts::1 7964 # Per bank write bursts
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system.physmem.perBankWrBursts::3 8679 # Per bank write bursts
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system.physmem.perBankWrBursts::5 7468 # Per bank write bursts
system.physmem.perBankWrBursts::6 8076 # Per bank write bursts
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system.physmem.perBankWrBursts::8 8056 # Per bank write bursts
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system.physmem.perBankWrBursts::10 7497 # Per bank write bursts
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system.physmem.perBankWrBursts::12 7556 # Per bank write bursts
system.physmem.perBankWrBursts::13 8041 # Per bank write bursts
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system.physmem.perBankWrBursts::15 7447 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 10 # Number of times write queue was full causing retry
-system.physmem.totGap 2832892258000 # Total gap between requests
+system.physmem.numWrRetry 20 # Number of times write queue was full causing retry
+system.physmem.totGap 2832922560000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 542 # Read request sizes (log2)
system.physmem.readPktSize::3 14 # Read request sizes (log2)
system.physmem.readPktSize::4 2996 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 166439 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 4381 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 124961 # Write request sizes (log2)
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-system.physmem.bytesPerActivate::samples 62068 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 304.427918 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 179.985587 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 324.629395 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 23230 37.43% 37.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 15016 24.19% 61.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 6492 10.46% 72.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 3585 5.78% 77.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2536 4.09% 81.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1572 2.53% 84.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1564 2.52% 86.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1071 1.73% 88.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 7002 11.28% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 62068 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 6143 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 27.640729 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 569.576579 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047 6142 99.98% 99.98% # Reads before turning the bus around for writes
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+system.physmem.bytesPerActivate::total 62162 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes
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-system.physmem.wrPerTurnAround::samples 6143 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 20.417874 # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::28-31 44 0.72% 91.81% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::36-39 15 0.24% 92.59% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::44-47 11 0.18% 93.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 132 2.15% 95.80% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::56-59 5 0.08% 96.16% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::96-99 1 0.02% 99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103 1 0.02% 99.63% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::120-123 1 0.02% 99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127 2 0.03% 99.69% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::samples 6134 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::140-143 2 0.03% 99.79% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::156-159 1 0.02% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163 1 0.02% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179 2 0.03% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 6143 # Writes before turning the bus around for reads
-system.physmem.totQLat 2131723500 # Total ticks spent queuing
-system.physmem.totMemAccLat 5315698500 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 849060000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 12553.43 # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::144-147 5 0.08% 99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155 1 0.02% 99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159 3 0.05% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163 1 0.02% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175 1 0.02% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179 1 0.02% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-195 1 0.02% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 6134 # Writes before turning the bus around for reads
+system.physmem.totQLat 2139801000 # Total ticks spent queuing
+system.physmem.totMemAccLat 5323944750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 849105000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 12600.33 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 31303.43 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 31350.33 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 3.84 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 2.83 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 3.78 # Average system read bandwidth in MiByte/s
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 26.05 # Average write queue length when enqueuing
-system.physmem.readRowHits 139329 # Number of row buffer hits during reads
-system.physmem.writeRowHits 93841 # Number of row buffer hits during writes
+system.physmem.avgWrQLen 27.97 # Average write queue length when enqueuing
+system.physmem.readRowHits 139332 # Number of row buffer hits during reads
+system.physmem.writeRowHits 93753 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.05 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 74.80 # Row buffer hit rate for writes
-system.physmem.avgGap 9464015.86 # Average gap between requests
-system.physmem.pageHitRate 78.97 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 247484160 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 135036000 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 696267000 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 421167600 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 185030401920 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 83639897910 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 1626363962250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 1896534216840 # Total energy per rank (pJ)
-system.physmem_0.averagePower 669.470442 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 2705464523500 # Time in different power states
-system.physmem_0.memoryStateTime::REF 94596320000 # Time in different power states
+system.physmem.writeRowHitRate 74.73 # Row buffer hit rate for writes
+system.physmem.avgGap 9463959.00 # Average gap between requests
+system.physmem.pageHitRate 78.94 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 247869720 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 135246375 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 696290400 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 421154640 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 185032436160 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 83656164285 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 1626368380500 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 1896557542080 # Total energy per rank (pJ)
+system.physmem_0.averagePower 669.471316 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 2705472781500 # Time in different power states
+system.physmem_0.memoryStateTime::REF 94597360000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 32831633000 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 32852637000 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 221749920 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 120994500 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 628258800 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 391599360 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 185030401920 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 81914804595 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 1627877202000 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 1896185011095 # Total energy per rank (pJ)
-system.physmem_1.averagePower 669.347174 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 2707992537250 # Time in different power states
-system.physmem_1.memoryStateTime::REF 94596320000 # Time in different power states
+system.physmem_1.actEnergy 222075000 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 121171875 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 628305600 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 391612320 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 185032436160 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 81913765770 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 1627896800250 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 1896206166975 # Total energy per rank (pJ)
+system.physmem_1.averagePower 669.347283 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 2708023579500 # Time in different power states
+system.physmem_1.memoryStateTime::REF 94597360000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 30298312750 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 30297375500 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
-system.cpu.branchPred.lookups 46858247 # Number of BP lookups
-system.cpu.branchPred.condPredicted 24018458 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 1233894 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 29504756 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 21322919 # Number of BTB hits
+system.cpu.branchPred.lookups 46900870 # Number of BP lookups
+system.cpu.branchPred.condPredicted 24033937 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 1233884 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 29535620 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 21344859 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 72.269430 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 11723897 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 33908 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 72.268193 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 11734674 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 33890 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.walks 71892 # Table walker walks requested
-system.cpu.dtb.walker.walksShort 71892 # Table walker walks initiated with short descriptors
-system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29751 # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22366 # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksSquashedBefore 19775 # Table walks squashed before starting
-system.cpu.dtb.walker.walkWaitTime::samples 52117 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::mean 422.184700 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::stdev 2564.754173 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0-4095 50340 96.59% 96.59% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::4096-8191 585 1.12% 97.71% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::8192-12287 526 1.01% 98.72% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::12288-16383 339 0.65% 99.37% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::16384-20479 52 0.10% 99.47% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walks 71837 # Table walker walks requested
+system.cpu.dtb.walker.walksShort 71837 # Table walker walks initiated with short descriptors
+system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29758 # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22348 # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksSquashedBefore 19731 # Table walks squashed before starting
+system.cpu.dtb.walker.walkWaitTime::samples 52106 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::mean 420.441024 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::stdev 2560.543879 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0-4095 50336 96.60% 96.60% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::4096-8191 584 1.12% 97.72% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::8192-12287 523 1.00% 98.73% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::12288-16383 337 0.65% 99.37% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::16384-20479 50 0.10% 99.47% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::20480-24575 220 0.42% 99.89% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::24576-28671 14 0.03% 99.92% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::24576-28671 15 0.03% 99.92% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::28672-32767 10 0.02% 99.94% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::32768-36863 8 0.02% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::36864-40959 5 0.01% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::53248-57343 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::57344-61439 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::61440-65535 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total 52117 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples 17509 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 11528.471072 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 9159.485910 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev 8140.517404 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-32767 17326 98.95% 98.95% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkWaitTime::total 52106 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples 17457 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 11531.334135 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 9171.811391 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev 8140.859549 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-32767 17274 98.95% 98.95% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::32768-65535 177 1.01% 99.97% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::131072-163839 5 0.03% 99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total 17509 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples 131356952816 # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::mean 0.616906 # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::stdev 0.493482 # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0-1 131302352316 99.96% 99.96% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::2-3 37456000 0.03% 99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::4-5 6990000 0.01% 99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::6-7 6140500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::8-9 1200000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::10-11 643000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::12-13 1366500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::14-15 794500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walkCompletionTime::total 17457 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples 131387254816 # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::mean 0.617449 # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::stdev 0.493362 # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0-1 131332759316 99.96% 99.96% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::2-3 37388500 0.03% 99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::4-5 6986000 0.01% 99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::6-7 6081500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::8-9 1205000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::10-11 646500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::12-13 1379500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::14-15 798500 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::16-17 10000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total 131356952816 # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K 6353 82.36% 82.36% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::1M 1361 17.64% 100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total 7714 # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 71892 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walksPending::total 131387254816 # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K 6345 82.34% 82.34% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::1M 1361 17.66% 100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total 7706 # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 71837 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 71892 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7714 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total 71837 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7706 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7714 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 79606 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7706 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total 79543 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 25445841 # DTB read hits
-system.cpu.dtb.read_misses 61989 # DTB read misses
-system.cpu.dtb.write_hits 19906354 # DTB write hits
-system.cpu.dtb.write_misses 9903 # DTB write misses
+system.cpu.dtb.read_hits 25453240 # DTB read hits
+system.cpu.dtb.read_misses 61907 # DTB read misses
+system.cpu.dtb.write_hits 19910032 # DTB write hits
+system.cpu.dtb.write_misses 9930 # DTB write misses
system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.align_faults 357 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 2185 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 1330 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 25507830 # DTB read accesses
-system.cpu.dtb.write_accesses 19916257 # DTB write accesses
+system.cpu.dtb.perms_faults 1331 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 25515147 # DTB read accesses
+system.cpu.dtb.write_accesses 19919962 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 45352195 # DTB hits
-system.cpu.dtb.misses 71892 # DTB misses
-system.cpu.dtb.accesses 45424087 # DTB accesses
+system.cpu.dtb.hits 45363272 # DTB hits
+system.cpu.dtb.misses 71837 # DTB misses
+system.cpu.dtb.accesses 45435109 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.walks 11896 # Table walker walks requested
-system.cpu.itb.walker.walksShort 11896 # Table walker walks initiated with short descriptors
-system.cpu.itb.walker.walksShortTerminationLevel::Level1 3936 # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walksShortTerminationLevel::Level2 7739 # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walksSquashedBefore 221 # Table walks squashed before starting
-system.cpu.itb.walker.walkWaitTime::samples 11675 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::mean 618.158458 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::stdev 2886.319815 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0-4095 11119 95.24% 95.24% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::4096-8191 158 1.35% 96.59% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::8192-12287 193 1.65% 98.24% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::12288-16383 62 0.53% 98.78% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::16384-20479 98 0.84% 99.61% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::20480-24575 33 0.28% 99.90% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::24576-28671 2 0.02% 99.91% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walks 13224 # Table walker walks requested
+system.cpu.itb.walker.walksShort 13224 # Table walker walks initiated with short descriptors
+system.cpu.itb.walker.walksShortTerminationLevel::Level1 3935 # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walksShortTerminationLevel::Level2 7779 # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walksSquashedBefore 1510 # Table walks squashed before starting
+system.cpu.itb.walker.walkWaitTime::samples 11714 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::mean 663.436913 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::stdev 2983.675240 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0-4095 11112 94.86% 94.86% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::4096-8191 167 1.43% 96.29% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::8192-12287 192 1.64% 97.93% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::12288-16383 98 0.84% 98.76% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::16384-20479 101 0.86% 99.62% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::20480-24575 31 0.26% 99.89% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::24576-28671 3 0.03% 99.91% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::28672-32767 7 0.06% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::45056-49151 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::49152-53247 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::57344-61439 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total 11675 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples 3548 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 12874.295378 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 10192.055773 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev 8701.296219 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-16383 2600 73.28% 73.28% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::16384-32767 890 25.08% 98.37% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::32768-49151 56 1.58% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::131072-147455 2 0.06% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total 3548 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples 23982708416 # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::mean 0.963466 # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::stdev 0.187762 # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0 876788500 3.66% 3.66% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::1 23105369416 96.34% 100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::2 493000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walkWaitTime::total 11714 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples 4832 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 11551.427980 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 9033.563647 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev 8305.140651 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-16383 3848 79.64% 79.64% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::16384-32767 915 18.94% 98.57% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::32768-49151 67 1.39% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::131072-147455 2 0.04% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total 4832 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples 24013010416 # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::mean 0.681227 # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::stdev 0.466165 # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0 7656484500 31.88% 31.88% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::1 16354802916 68.11% 99.99% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::2 1665500 0.01% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::3 57500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total 23982708416 # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K 3008 90.41% 90.41% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::1M 319 9.59% 100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total 3327 # Table walker page sizes translated
+system.cpu.itb.walker.walksPending::total 24013010416 # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K 3004 90.43% 90.43% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::1M 318 9.57% 100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total 3322 # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 11896 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 11896 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 13224 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total 13224 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3327 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 3327 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 15223 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 66221900 # ITB inst hits
-system.cpu.itb.inst_misses 11896 # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3322 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total 3322 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total 16546 # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits 66215474 # ITB inst hits
+system.cpu.itb.inst_misses 13224 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 3095 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 3093 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 2205 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 2222 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 66233796 # ITB inst accesses
-system.cpu.itb.hits 66221900 # DTB hits
-system.cpu.itb.misses 11896 # DTB misses
-system.cpu.itb.accesses 66233796 # DTB accesses
-system.cpu.numCycles 278773245 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 66228698 # ITB inst accesses
+system.cpu.itb.hits 66215474 # DTB hits
+system.cpu.itb.misses 13224 # DTB misses
+system.cpu.itb.accesses 66228698 # DTB accesses
+system.cpu.numCycles 278849039 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 104752235 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 184598573 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 46858247 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 33046816 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 161804794 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 6150362 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 189820 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles 10294 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 357135 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 560172 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 186 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 66222091 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 1133757 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 5184 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 270749817 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.831543 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 1.217938 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 104825039 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 184547548 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 46900870 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 33079533 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 161783291 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 6174948 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 189837 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles 10053 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 357428 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 560111 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 175 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 66214357 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 1060583 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 6520 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 270813408 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.831546 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 1.217852 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 171531140 63.35% 63.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 29224382 10.79% 74.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 14067275 5.20% 79.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 55927020 20.66% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 171553183 63.35% 63.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 29255757 10.80% 74.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 14075334 5.20% 79.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 55929134 20.65% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 270749817 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.168087 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.662182 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 77852001 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 121869294 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 64587229 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 3844010 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 2597283 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 3423147 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 486289 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 157329382 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 3698909 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 2597283 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 83697131 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 11783559 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 76650059 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 62587653 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 33434132 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 146702491 # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts 957120 # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents 451934 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 63799 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 16325 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 30684565 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 150381225 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 678253528 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 164322158 # Number of integer rename lookups
+system.cpu.fetch.rateDist::total 270813408 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.168194 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.661819 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 77914241 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 121818980 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 64632452 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 3838198 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 2609537 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 3423128 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 486335 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 157406934 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 3698656 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 2609537 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 83756930 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 11780773 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 76597873 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 62631659 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 33436636 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 146755972 # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts 956855 # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents 452398 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 63697 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 16353 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 30702971 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 150428298 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 678515900 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 164385434 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 10889 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 141709530 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 8671692 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 2840546 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 2644403 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 13862058 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 26394800 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 21292698 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1688864 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 2213691 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 143441668 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 2121624 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 143228772 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 270823 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 8408546 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 14699465 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 125775 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 270749817 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.529008 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 0.865566 # Number of insts issued each cycle
+system.cpu.rename.CommittedMaps 141750240 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 8678055 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 2842275 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 2646130 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 13851175 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 26402053 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 21296304 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1688639 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 2128632 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 143481450 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 2121615 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 143268725 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 270645 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 8409947 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 14700028 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 125764 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 270813408 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.529031 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 0.865143 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 182513589 67.41% 67.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 45134220 16.67% 84.08% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 32022113 11.83% 95.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 10269287 3.79% 99.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 810575 0.30% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 182463558 67.38% 67.38% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 45313359 16.73% 84.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 31963465 11.80% 95.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 10263701 3.79% 99.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 809292 0.30% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 270749817 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 270813408 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 7336339 32.73% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 32 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 5631595 25.13% 57.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 9443725 42.14% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 7332102 32.71% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 32 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 5631471 25.13% 57.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 9448597 42.16% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 95929894 66.98% 66.98% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 113798 0.08% 67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 95958706 66.98% 66.98% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 113835 0.08% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 8576 0.01% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 26176243 18.28% 85.34% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 20997924 14.66% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 8576 0.01% 67.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 26183625 18.28% 85.34% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 21001646 14.66% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 143228772 # Type of FU issued
-system.cpu.iq.rate 0.513782 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 22411691 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.156475 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 579854290 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 153977213 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 140119725 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 35585 # Number of floating instruction queue reads
+system.cpu.iq.FU_type_0::total 143268725 # Type of FU issued
+system.cpu.iq.rate 0.513786 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 22412202 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.156435 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 579998115 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 154018366 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 140157777 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 35590 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 13122 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 11367 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 165614781 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 23345 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 322762 # Number of loads that had data forwarded from stores
+system.cpu.iq.int_alu_accesses 165655240 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 23350 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 322841 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1496089 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 504 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 18542 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 704390 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1496212 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 510 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 18521 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 704329 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 87859 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 6368 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 88213 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 6464 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 2597283 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 1242021 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 536402 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 145764225 # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles 2609537 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 1244131 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 534453 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 145804019 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 26394800 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 21292698 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1096198 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 17994 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 502218 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 18542 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 317968 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 471203 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 789171 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 142285969 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 25773594 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 871017 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts 26402053 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 21296304 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1096200 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 17993 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 500261 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 18521 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 317950 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 471174 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 789124 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 142326073 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 25781011 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 870919 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 200933 # number of nop insts executed
-system.cpu.iew.exec_refs 46642596 # number of memory reference insts executed
-system.cpu.iew.exec_branches 26501312 # Number of branches executed
-system.cpu.iew.exec_stores 20869002 # Number of stores executed
-system.cpu.iew.exec_rate 0.510400 # Inst execution rate
-system.cpu.iew.wb_sent 141899463 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 140131092 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 63222174 # num instructions producing a value
-system.cpu.iew.wb_consumers 95712525 # num instructions consuming a value
-system.cpu.iew.wb_rate 0.502671 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.660542 # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts 7607261 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1995849 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 755996 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 267815570 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.512702 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.117847 # Number of insts commited each cycle
+system.cpu.iew.exec_nop 200954 # number of nop insts executed
+system.cpu.iew.exec_refs 46653702 # number of memory reference insts executed
+system.cpu.iew.exec_branches 26511824 # Number of branches executed
+system.cpu.iew.exec_stores 20872691 # Number of stores executed
+system.cpu.iew.exec_rate 0.510405 # Inst execution rate
+system.cpu.iew.wb_sent 141939572 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 140169144 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 63244057 # num instructions producing a value
+system.cpu.iew.wb_consumers 95727511 # num instructions consuming a value
+system.cpu.iew.wb_rate 0.502670 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.660668 # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts 7609153 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1995851 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 755947 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 267866819 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.512747 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.116675 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 194420599 72.59% 72.59% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 43232205 16.14% 88.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 15469123 5.78% 94.51% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 4394347 1.64% 96.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 6341720 2.37% 98.52% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1685703 0.63% 99.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 801057 0.30% 99.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 412110 0.15% 99.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 1058706 0.40% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 194366787 72.56% 72.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 43325916 16.17% 88.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 15476786 5.78% 94.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 4394475 1.64% 96.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 6423634 2.40% 98.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1609805 0.60% 99.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 801244 0.30% 99.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 411295 0.15% 99.61% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 1056877 0.39% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 267815570 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 113234401 # Number of instructions committed
-system.cpu.commit.committedOps 137309647 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 267866819 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 113265756 # Number of instructions committed
+system.cpu.commit.committedOps 137348019 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 45487019 # Number of memory references committed
-system.cpu.commit.loads 24898711 # Number of loads committed
+system.cpu.commit.refs 45497816 # Number of memory references committed
+system.cpu.commit.loads 24905841 # Number of loads committed
system.cpu.commit.membars 814912 # Number of memory barriers committed
-system.cpu.commit.branches 26016004 # Number of branches committed
+system.cpu.commit.branches 26026635 # Number of branches committed
system.cpu.commit.fp_insts 11364 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 120139877 # Number of committed integer instructions.
-system.cpu.commit.function_calls 4881537 # Number of function calls committed.
+system.cpu.commit.int_insts 120174652 # Number of committed integer instructions.
+system.cpu.commit.function_calls 4885050 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu 91701321 66.78% 66.78% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult 112732 0.08% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu 91728853 66.79% 66.79% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult 112775 0.08% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead 24898711 18.13% 85.01% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite 20588308 14.99% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead 24905841 18.13% 85.01% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite 20591975 14.99% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total 137309647 # Class of committed instruction
-system.cpu.commit.bw_lim_events 1058706 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 389516895 # The number of ROB reads
-system.cpu.rob.rob_writes 292765635 # The number of ROB writes
-system.cpu.timesIdled 892830 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 8023428 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 5387011736 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 113079496 # Number of Instructions Simulated
-system.cpu.committedOps 137154742 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 2.465286 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 2.465286 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.405633 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.405633 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 155725818 # number of integer regfile reads
-system.cpu.int_regfile_writes 88564532 # number of integer regfile writes
+system.cpu.commit.op_class_0::total 137348019 # Class of committed instruction
+system.cpu.commit.bw_lim_events 1056877 # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads 389577087 # The number of ROB reads
+system.cpu.rob.rob_writes 292847921 # The number of ROB writes
+system.cpu.timesIdled 893517 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 8035631 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles 5386996546 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts 113110851 # Number of Instructions Simulated
+system.cpu.committedOps 137193114 # Number of Ops (including micro ops) Simulated
+system.cpu.cpi 2.465272 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 2.465272 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.405635 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.405635 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 155766897 # number of integer regfile reads
+system.cpu.int_regfile_writes 88591582 # number of integer regfile writes
system.cpu.fp_regfile_reads 9527 # number of floating regfile reads
system.cpu.fp_regfile_writes 2716 # number of floating regfile writes
-system.cpu.cc_regfile_reads 502646310 # number of cc regfile reads
-system.cpu.cc_regfile_writes 53156218 # number of cc regfile writes
-system.cpu.misc_regfile_reads 348169816 # number of misc regfile reads
-system.cpu.misc_regfile_writes 1521639 # number of misc regfile writes
-system.cpu.dcache.tags.replacements 837355 # number of replacements
-system.cpu.dcache.tags.tagsinuse 511.925653 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 40093288 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 837867 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 47.851614 # Average number of references to valid blocks.
+system.cpu.cc_regfile_reads 502787807 # number of cc regfile reads
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+system.cpu.dcache.tags.sampled_refs 837895 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 47.861899 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 441954500 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.tags.occ_percent::cpu.data 0.999855 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999855 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 369 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 179262934 # Number of tag accesses
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-system.cpu.dcache.WriteReq_hits::total 15545406 # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses 179305026 # Number of tag accesses
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010500 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.177503 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.060387 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 136714.285714 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 122750 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 132862.068966 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68012.862918 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68012.862918 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.455931 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.455931 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010503 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010503 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.024640 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024640 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000403 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000673 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010503 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.177492 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.060383 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000403 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000673 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010503 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.177492 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.060383 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 136113.636364 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 122687.500000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 132533.333333 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68011.760382 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68011.760382 # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69833.333333 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69833.333333 # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 119968.506961 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 119968.506961 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122395.084881 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122395.084881 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125346.958674 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125346.958674 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 136714.285714 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122750 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122395.084881 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120450.668334 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120681.372474 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 136714.285714 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122750 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122395.084881 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120450.668334 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120681.372474 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 119985.985450 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 119985.985450 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122650.388508 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122650.388508 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125393.240303 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125393.240303 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 136113.636364 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122687.500000 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122650.388508 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120470.596541 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120729.053964 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 136113.636364 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122687.500000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122650.388508 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120470.596541 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120729.053964 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113221.371505 # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189122.618780 # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 182442.650807 # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172447.380823 # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172447.380823 # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189135.372161 # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 182454.281780 # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172423.001631 # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172423.001631 # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113221.371505 # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181288.261743 # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177975.242231 # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181283.569506 # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177970.778379 # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests 5483442 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 2758353 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 47114 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 381 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 381 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests 5483800 # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 2758533 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 47116 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops 382 # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops 382 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadReq 128030 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 2556317 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq 128080 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 2556548 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 27585 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 27585 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty 820394 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 1886695 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 149869 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty 820436 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean 1886845 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict 149868 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 2755 # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 2761 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 296967 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 296967 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 1887230 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 541172 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 296964 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 296964 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 1887380 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 541203 # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq 36194 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5667118 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2636221 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31264 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 129096 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 8463699 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 241576384 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98323817 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 47400 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 218452 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 340166053 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 196965 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 3052848 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.025894 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.158818 # Request fanout histogram
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5667569 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2636305 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31377 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 129075 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 8464326 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 241595648 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98327529 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 47536 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 218484 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 340189197 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 196985 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 3053089 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 0.025893 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.158816 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 2973799 97.41% 97.41% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 79049 2.59% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 2974035 97.41% 97.41% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 79054 2.59% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 3052848 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 5399685497 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 3053089 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 5400068497 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy 264877 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 2834668847 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 2834904825 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 1303356559 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 1303398559 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy 19420986 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy 19499986 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy 74535395 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy 74506395 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.trans_dist::ReadReq 30198 # Transaction distribution
system.iobus.trans_dist::ReadResp 30198 # Transaction distribution
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321224 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321224 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2480349 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 43091000 # Layer occupancy (ticks)
+system.iobus.reqLayer0.occupancy 43092000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 99500 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 14500 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer7.occupancy 91000 # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy 91500 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer8.occupancy 648000 # Layer occupancy (ticks)
+system.iobus.reqLayer8.occupancy 654000 # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 21000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 3000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer20.occupancy 9500 # Layer occupancy (ticks)
+system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 8500 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 6193500 # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy 6200500 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer24.occupancy 33084000 # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy 32980000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 187182974 # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy 187207462 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 36770000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 36409 # number of replacements
-system.iocache.tags.tagsinuse 1.005274 # Cycle average of tags in use
+system.iocache.tags.tagsinuse 1.005413 # Cycle average of tags in use
system.iocache.tags.total_refs 30 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 36425 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0.000824 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 256605904000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide 1.005274 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide 0.062830 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.062830 # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle 256609976000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide 1.005413 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide 0.062838 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.062838 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.demand_misses::total 249 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 249 # number of overall misses
system.iocache.overall_misses::total 249 # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide 31308877 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 31308877 # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide 4546803097 # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total 4546803097 # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide 31308877 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 31308877 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide 31308877 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 31308877 # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide 31311877 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 31311877 # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide 4548827585 # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total 4548827585 # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide 31311877 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 31311877 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide 31311877 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 31311877 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide 249 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 125738.461847 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 125738.461847 # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125619.646277 # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 125619.646277 # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 125738.461847 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 125738.461847 # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 125738.461847 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 125738.461847 # average overall miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 125750.510040 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 125750.510040 # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125675.579086 # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 125675.579086 # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 125750.510040 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 125750.510040 # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 125750.510040 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 125750.510040 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.demand_mshr_misses::total 249 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide 249 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 249 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide 18858877 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 18858877 # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2735602611 # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total 2735602611 # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide 18858877 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 18858877 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide 18858877 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 18858877 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide 18861877 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 18861877 # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2737619112 # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total 2737619112 # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide 18861877 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 18861877 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide 18861877 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 18861877 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.999199 # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 75738.461847 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 75738.461847 # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75579.572068 # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75579.572068 # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 75738.461847 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 75738.461847 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 75738.461847 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 75738.461847 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 75750.510040 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 75750.510040 # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75635.284211 # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75635.284211 # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 75750.510040 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 75750.510040 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 75750.510040 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 75750.510040 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 34133 # Transaction distribution
-system.membus.trans_dist::ReadResp 67559 # Transaction distribution
+system.membus.trans_dist::ReadResp 67562 # Transaction distribution
system.membus.trans_dist::WriteReq 27585 # Transaction distribution
system.membus.trans_dist::WriteResp 27585 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 124961 # Transaction distribution
-system.membus.trans_dist::CleanEvict 7937 # Transaction distribution
+system.membus.trans_dist::WritebackDirty 124963 # Transaction distribution
+system.membus.trans_dist::CleanEvict 7938 # Transaction distribution
system.membus.trans_dist::UpgradeReq 4594 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
system.membus.trans_dist::ReadExReq 133523 # Transaction distribution
system.membus.trans_dist::ReadExResp 133523 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 33427 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 33430 # Transaction distribution
system.membus.trans_dist::InvalidateReq 36194 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2076 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 450075 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 557645 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 450084 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 557654 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72868 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 72868 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 630513 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 630522 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4152 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16402076 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16565481 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16402396 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16565801 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2315200 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2315200 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 18880681 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 18881001 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 513 # Total snoops (count)
-system.membus.snoop_fanout::samples 402367 # Request fanout histogram
+system.membus.snoop_fanout::samples 402383 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 402367 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 402383 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 402367 # Request fanout histogram
-system.membus.reqLayer0.occupancy 83710000 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 402383 # Request fanout histogram
+system.membus.reqLayer0.occupancy 83620000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 1748000 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 1745500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 873736629 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 873794635 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 978197500 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 978214250 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 1313623 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm
+boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
+dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
+exit_on_work_items=false
flags_addr=469827632
gic_cpu_addr=738205696
have_large_asid_64=false
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
+readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/work/gem5/dist/disks/linux-aarch32-ael.img
+image_file=/home/stever/m5/aarch-system-2014-10/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=false
hit_latency=50
is_read_only=false
max_miss_count=0
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.toL2Bus.snoop_filter
snoop_response_latency=1
warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4]
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
WARNING: Bank is already active!
-Command: 0, Timestamp: 6880, Bank: 0
+Command: 0, Timestamp: 8288, Bank: 0
WARNING: Bank is already active!
-Command: 0, Timestamp: 8514, Bank: 5
+Command: 0, Timestamp: 6918, Bank: 3
WARNING: Bank is already active!
-Command: 0, Timestamp: 6490, Bank: 3
+Command: 0, Timestamp: 11135, Bank: 1
WARNING: Bank is already active!
-Command: 0, Timestamp: 10863, Bank: 6
+Command: 0, Timestamp: 11139, Bank: 6
warn: CP14 unimplemented crn[6], opc1[5], crm[0], opc2[0]
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
warn: CP14 unimplemented crn[5], opc1[4], crm[12], opc2[4]
-WARNING: Bank is already active!
-Command: 0, Timestamp: 10530, Bank: 6
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: CP14 unimplemented crn[0], opc1[4], crm[12], opc2[2]
warn: CP14 unimplemented crn[7], opc1[0], crm[12], opc2[1]
WARNING: One or more banks are active! REF requires all banks to be precharged.
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: instruction 'mcr dcisw' unimplemented
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full/simout
+Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 4 2015 11:13:17
-gem5 started Dec 4 2015 13:54:35
-gem5 executing on e104799-lin, pid 12868
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full
+gem5 compiled Mar 15 2016 21:26:42
+gem5 started Mar 15 2016 21:52:46
+gem5 executing on phenom, pid 15993
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full
Global frequency set at 1000000000000 ticks per second
---------- Begin Simulation Statistics ----------
-sim_seconds 2.824861 # Number of seconds simulated
-sim_ticks 2824861157500 # Number of ticks simulated
-final_tick 2824861157500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.824888 # Number of seconds simulated
+sim_ticks 2824887572500 # Number of ticks simulated
+final_tick 2824887572500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 318305 # Simulator instruction rate (inst/s)
-host_op_rate 386131 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 7310787662 # Simulator tick rate (ticks/s)
-host_mem_usage 588068 # Number of bytes of host memory used
-host_seconds 386.40 # Real time elapsed on the host
-sim_insts 122991731 # Number of instructions simulated
-sim_ops 149199638 # Number of ops (including micro ops) simulated
+host_inst_rate 216723 # Simulator instruction rate (inst/s)
+host_op_rate 262904 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 4977623525 # Simulator tick rate (ticks/s)
+host_mem_usage 565980 # Number of bytes of host memory used
+host_seconds 567.52 # Real time elapsed on the host
+sim_insts 122993828 # Number of instructions simulated
+sim_ops 149202488 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker 192 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 541668 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 4133796 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 101440 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 929920 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.dtb.walker 2048 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst 334208 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data 1678016 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 541924 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 4139684 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 101376 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 929664 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.dtb.walker 1984 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst 333376 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data 1678720 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.dtb.walker 4352 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.inst 417280 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.data 3020416 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.inst 417152 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.data 3014592 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 11164360 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 541668 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 101440 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst 334208 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu3.inst 417280 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory
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system.physmem.num_reads::cpu0.dtb.walker 3 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu3.dtb.walker 68 # Number of read requests responded to by this memory
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system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
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system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu0.dtb.walker 68 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu3.dtb.walker 1541 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s)
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-system.physmem.bw_inst_read::total 493687 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 2973960 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu0.data 6203 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2980163 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu0.dtb.walker 68 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu3.dtb.walker 1541 # Total bandwidth to/from this memory (bytes/s)
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-system.physmem.bw_total::cpu3.data 1069226 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 6932344 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 101370 # Number of read requests accepted
-system.physmem.writeReqs 69810 # Number of write requests accepted
-system.physmem.readBursts 101370 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 69810 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 6481472 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 6208 # Total number of bytes read from write queue
-system.physmem.bytesWritten 4467008 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 6487680 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 4467840 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 97 # Number of DRAM read bursts serviced by the write queue
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+system.physmem.bytesReadWrQ 6272 # Total number of bytes read from write queue
+system.physmem.bytesWritten 4461760 # Total number of bytes written to DRAM
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+system.physmem.bytesWrittenSys 4462848 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 98 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 6935 # Per bank write bursts
-system.physmem.perBankRdBursts::1 6436 # Per bank write bursts
-system.physmem.perBankRdBursts::2 6583 # Per bank write bursts
-system.physmem.perBankRdBursts::3 6249 # Per bank write bursts
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system.physmem.perBankRdBursts::4 6342 # Per bank write bursts
system.physmem.perBankRdBursts::5 6194 # Per bank write bursts
-system.physmem.perBankRdBursts::6 6523 # Per bank write bursts
-system.physmem.perBankRdBursts::7 6688 # Per bank write bursts
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+system.physmem.perBankRdBursts::7 6694 # Per bank write bursts
system.physmem.perBankRdBursts::8 6445 # Per bank write bursts
-system.physmem.perBankRdBursts::9 6967 # Per bank write bursts
-system.physmem.perBankRdBursts::10 6205 # Per bank write bursts
-system.physmem.perBankRdBursts::11 5540 # Per bank write bursts
-system.physmem.perBankRdBursts::12 5538 # Per bank write bursts
-system.physmem.perBankRdBursts::13 6823 # Per bank write bursts
-system.physmem.perBankRdBursts::14 6219 # Per bank write bursts
+system.physmem.perBankRdBursts::9 6959 # Per bank write bursts
+system.physmem.perBankRdBursts::10 6209 # Per bank write bursts
+system.physmem.perBankRdBursts::11 5533 # Per bank write bursts
+system.physmem.perBankRdBursts::12 5533 # Per bank write bursts
+system.physmem.perBankRdBursts::13 6776 # Per bank write bursts
+system.physmem.perBankRdBursts::14 6216 # Per bank write bursts
system.physmem.perBankRdBursts::15 5586 # Per bank write bursts
-system.physmem.perBankWrBursts::0 4692 # Per bank write bursts
-system.physmem.perBankWrBursts::1 4257 # Per bank write bursts
-system.physmem.perBankWrBursts::2 4659 # Per bank write bursts
-system.physmem.perBankWrBursts::3 4198 # Per bank write bursts
-system.physmem.perBankWrBursts::4 4374 # Per bank write bursts
+system.physmem.perBankWrBursts::0 4691 # Per bank write bursts
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+system.physmem.perBankWrBursts::2 4619 # Per bank write bursts
+system.physmem.perBankWrBursts::3 4200 # Per bank write bursts
+system.physmem.perBankWrBursts::4 4373 # Per bank write bursts
system.physmem.perBankWrBursts::5 4446 # Per bank write bursts
-system.physmem.perBankWrBursts::6 4601 # Per bank write bursts
-system.physmem.perBankWrBursts::7 4285 # Per bank write bursts
+system.physmem.perBankWrBursts::6 4606 # Per bank write bursts
+system.physmem.perBankWrBursts::7 4292 # Per bank write bursts
system.physmem.perBankWrBursts::8 4489 # Per bank write bursts
system.physmem.perBankWrBursts::9 5118 # Per bank write bursts
-system.physmem.perBankWrBursts::10 4303 # Per bank write bursts
-system.physmem.perBankWrBursts::11 3737 # Per bank write bursts
-system.physmem.perBankWrBursts::12 3765 # Per bank write bursts
-system.physmem.perBankWrBursts::13 4849 # Per bank write bursts
+system.physmem.perBankWrBursts::10 4307 # Per bank write bursts
+system.physmem.perBankWrBursts::11 3733 # Per bank write bursts
+system.physmem.perBankWrBursts::12 3760 # Per bank write bursts
+system.physmem.perBankWrBursts::13 4801 # Per bank write bursts
system.physmem.perBankWrBursts::14 4212 # Per bank write bursts
system.physmem.perBankWrBursts::15 3812 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 6 # Number of times write queue was full causing retry
-system.physmem.totGap 2823294888500 # Total gap between requests
+system.physmem.numWrRetry 5 # Number of times write queue was full causing retry
+system.physmem.totGap 2823321303500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 101370 # Read request sizes (log2)
+system.physmem.readPktSize::6 101269 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 69810 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 77482 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 21030 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 2174 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 584 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 69732 # Write request sizes (log2)
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system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::7 67 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 68 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 67 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 67 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 66 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 66 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 65 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 64 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 64 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::16 1607 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::33 388 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 119 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 104 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 44 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 64 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 60 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 48 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::41 26 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 31 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 46 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 34 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 39 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 19 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 28 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 42 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 25 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 28 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 26 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 20 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 14 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 23 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 12 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 11 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 12 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 19 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 11 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 10 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 30 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 14 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 39513 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 277.080657 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 164.075754 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 309.106343 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 16212 41.03% 41.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 9667 24.47% 65.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 3869 9.79% 75.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 2066 5.23% 80.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 1631 4.13% 84.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 996 2.52% 87.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 644 1.63% 88.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 576 1.46% 90.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 3852 9.75% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 39513 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 3600 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 28.123611 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 470.848490 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 3598 99.94% 99.94% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::13 65 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 65 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::16 1613 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::19 3972 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 3735 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::22 3876 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::25 4187 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 4547 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 4146 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 4344 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 4795 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 4080 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 3977 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 3922 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 379 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 165 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 108 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 84 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 90 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 66 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 45 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 44 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 42 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 40 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 40 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44 42 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 45 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 33 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 27 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 21 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 31 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 33 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 31 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 33 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 25 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 44 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 27 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 36 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 30 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 14 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 14 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 17 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 14 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 4 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 39430 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 277.365255 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 164.227213 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 309.241894 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 16179 41.03% 41.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 9599 24.34% 65.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 3886 9.86% 75.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 2087 5.29% 80.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 1608 4.08% 84.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1015 2.57% 87.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 638 1.62% 88.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 547 1.39% 90.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 3871 9.82% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 39430 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 3587 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 28.196264 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 471.698929 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023 3585 99.94% 99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047 1 0.03% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::27648-28671 1 0.03% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 3600 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 3600 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 19.388056 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 18.044932 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 10.866321 # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total 3587 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 3587 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 19.435461 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.049607 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 11.402559 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3 5 0.14% 0.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7 1 0.03% 0.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11 2 0.06% 0.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15 4 0.11% 0.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 3199 88.86% 89.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 88 2.44% 91.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 45 1.25% 92.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 29 0.81% 93.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 26 0.72% 94.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 9 0.25% 94.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 30 0.83% 95.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 4 0.11% 95.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 51 1.42% 97.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 8 0.22% 97.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 6 0.17% 97.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 8 0.22% 97.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 35 0.97% 98.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 2 0.06% 98.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79 15 0.42% 99.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 27 0.75% 99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91 2 0.06% 99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115 1 0.03% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 1 0.03% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147 2 0.06% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 3600 # Writes before turning the bus around for reads
-system.physmem.totQLat 1317228500 # Total ticks spent queuing
-system.physmem.totMemAccLat 3216097250 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 506365000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 13006.71 # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::12-15 3 0.08% 0.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 3190 88.93% 89.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 86 2.40% 91.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 46 1.28% 92.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 29 0.81% 93.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 24 0.67% 94.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 7 0.20% 94.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 31 0.86% 95.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 8 0.22% 95.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 55 1.53% 97.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 9 0.25% 97.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 4 0.11% 97.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 7 0.20% 97.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 27 0.75% 98.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 2 0.06% 98.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 3 0.08% 98.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79 13 0.36% 99.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 26 0.72% 99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87 1 0.03% 99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115 1 0.03% 99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 4 0.11% 99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147 1 0.03% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159 1 0.03% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179 1 0.03% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 3587 # Writes before turning the bus around for reads
+system.physmem.totQLat 1320327750 # Total ticks spent queuing
+system.physmem.totMemAccLat 3217284000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 505855000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 13050.46 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 31756.71 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 31800.46 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 2.29 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 2.30 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 2.29 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 1.58 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 25.92 # Average write queue length when enqueuing
-system.physmem.readRowHits 81828 # Number of row buffer hits during reads
-system.physmem.writeRowHits 49728 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 80.80 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 71.23 # Row buffer hit rate for writes
-system.physmem.avgGap 16493135.23 # Average gap between requests
-system.physmem.pageHitRate 76.90 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 156575160 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 85288500 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 405210000 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 230117760 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 179783588400 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 73297208295 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 1624589512500 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 1878547500615 # Total energy per rank (pJ)
-system.physmem_0.averagePower 667.380132 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 2640349085250 # Time in different power states
-system.physmem_0.memoryStateTime::REF 91913900000 # Time in different power states
+system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 20.00 # Average write queue length when enqueuing
+system.physmem.readRowHits 81754 # Number of row buffer hits during reads
+system.physmem.writeRowHits 49701 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 80.81 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 71.27 # Row buffer hit rate for writes
+system.physmem.avgGap 16510554.34 # Average gap between requests
+system.physmem.pageHitRate 76.92 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 156287880 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 85131750 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 404929200 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 229929840 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 179785114080 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 73278235845 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 1622828751000 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 1876768379595 # Total energy per rank (pJ)
+system.physmem_0.averagePower 667.450508 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 2640406091750 # Time in different power states
+system.physmem_0.memoryStateTime::REF 91914680000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 20348745750 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 20314514250 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 142143120 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 77405625 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 384696000 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 222166800 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 179783588400 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 72817182225 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 1617846694500 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 1871273876670 # Total energy per rank (pJ)
-system.physmem_1.averagePower 667.628012 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 2641092160250 # Time in different power states
-system.physmem_1.memoryStateTime::REF 91913900000 # Time in different power states
+system.physmem_1.actEnergy 141802920 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 77215875 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 384181200 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 221823360 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 179785114080 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 72833545215 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 1617851985750 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 1871295668400 # Total energy per rank (pJ)
+system.physmem_1.averagePower 667.627988 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 2641096901750 # Time in different power states
+system.physmem_1.memoryStateTime::REF 91914680000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 19603403000 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 19627144250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.walks 4961 # Table walker walks requested
-system.cpu0.dtb.walker.walksShort 4961 # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walkWaitTime::samples 4961 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0 4961 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 4961 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walksPending::samples 53085056580 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean 1.356184 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0 -18908069420 -35.62% -35.62% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::1 71993126000 135.62% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 53085056580 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 2703 66.58% 66.58% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M 1357 33.42% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 4060 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 4961 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walks 4962 # Table walker walks requested
+system.cpu0.dtb.walker.walksShort 4962 # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walkWaitTime::samples 4962 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0 4962 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total 4962 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walksPending::samples 53085003580 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean 1.356186 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0 -18908123670 -35.62% -35.62% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::1 71993127250 135.62% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 53085003580 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K 2699 66.41% 66.41% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M 1365 33.59% 100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total 4064 # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 4962 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 4961 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4060 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 4962 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4064 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4060 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 9021 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4064 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total 9026 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 11954071 # DTB read hits
-system.cpu0.dtb.read_misses 4163 # DTB read misses
-system.cpu0.dtb.write_hits 9292740 # DTB write hits
+system.cpu0.dtb.read_hits 11954908 # DTB read hits
+system.cpu0.dtb.read_misses 4164 # DTB read misses
+system.cpu0.dtb.write_hits 9290329 # DTB write hits
system.cpu0.dtb.write_misses 798 # DTB write misses
system.cpu0.dtb.flush_tlb 171 # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva 343 # Number of times TLB was flushed by MVA
+system.cpu0.dtb.flush_tlb_mva 345 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 2861 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries 2862 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 729 # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults 723 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 164 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 11958234 # DTB read accesses
-system.cpu0.dtb.write_accesses 9293538 # DTB write accesses
+system.cpu0.dtb.perms_faults 165 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 11959072 # DTB read accesses
+system.cpu0.dtb.write_accesses 9291127 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 21246811 # DTB hits
-system.cpu0.dtb.misses 4961 # DTB misses
-system.cpu0.dtb.accesses 21251772 # DTB accesses
+system.cpu0.dtb.hits 21245237 # DTB hits
+system.cpu0.dtb.misses 4962 # DTB misses
+system.cpu0.dtb.accesses 21250199 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.walker.walks 2298 # Table walker walks requested
-system.cpu0.itb.walker.walksShort 2298 # Table walker walks initiated with short descriptors
-system.cpu0.itb.walker.walkWaitTime::samples 2298 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0 2298 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total 2298 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walksPending::samples 53085056580 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean 1.356187 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0 -18908211420 -35.62% -35.62% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1 71993268000 135.62% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 53085056580 # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K 1259 73.88% 73.88% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::1M 445 26.12% 100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walks 2303 # Table walker walks requested
+system.cpu0.itb.walker.walksShort 2303 # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.walkWaitTime::samples 2303 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0 2303 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total 2303 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walksPending::samples 53085003580 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean 1.356188 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0 -18908264170 -35.62% -35.62% # Table walker pending requests distribution
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+system.cpu0.itb.walker.walksPending::total 53085003580 # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K 1258 73.83% 73.83% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::1M 446 26.17% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 1704 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2298 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2298 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2303 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2303 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1704 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1704 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total 4002 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 57099385 # ITB inst hits
-system.cpu0.itb.inst_misses 2298 # ITB inst misses
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system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 171 # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva 343 # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb_mva 345 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 1710 # Number of entries that have been flushed from TLB
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 57101683 # ITB inst accesses
-system.cpu0.itb.hits 57099385 # DTB hits
-system.cpu0.itb.misses 2298 # DTB misses
-system.cpu0.itb.accesses 57101683 # DTB accesses
-system.cpu0.numCycles 69056574 # number of cpu cycles simulated
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+system.cpu0.itb.accesses 57103867 # DTB accesses
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system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 3089 # number of quiesce instructions executed
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-system.cpu0.idle_fraction 0.945125 # Percentage of idle cycles
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system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 68628410 # Class of executed instruction
-system.cpu0.dcache.tags.replacements 834050 # number of replacements
+system.cpu0.op_class::total 68628631 # Class of executed instruction
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system.cpu0.dcache.tags.tagsinuse 511.996936 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 46064647 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 834562 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 55.196195 # Average number of references to valid blocks.
+system.cpu0.dcache.tags.total_refs 46068701 # Total number of references to valid blocks.
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+system.cpu0.dcache.tags.avg_refs 55.199069 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit.
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+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3530288000 # number of ReadReq MSHR uncacheable cycles
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+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2761967452 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1098106500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 1930026500 # number of overall MSHR uncacheable cycles
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+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6292255452 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.015223 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018169 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.016894 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.009493 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.011651 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.015490 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.017429 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008544 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.245213 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.213013 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.225987 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.132271 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.013266 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.017933 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.028049 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.011230 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000308 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000063 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.013739 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.016991 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.013735 # mshr miss rate for demand accesses
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system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.017125 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.009080 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.016327 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.019626 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.019366 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.010452 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 16890.339748 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14528.801342 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15530.343603 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15516.715462 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 60124.379964 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 66680.693855 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 72337.063934 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68414.351230 # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13133.129736 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 13900.349498 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 17626.708418 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15255.257438 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15024.366472 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 17139.810427 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 15682.266910 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15964.394807 # average LoadLockedReq mshr miss latency
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+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 13899.568364 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 17317.713231 # average SoftPFReq mshr miss latency
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+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 17217.420662 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 15590.496917 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15940.874525 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 38310.344828 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 38310.344828 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 32114.775153 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 35362.391038 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 40515.108883 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37148.023481 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 28926.616006 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 32230.953838 # average overall mshr miss latency
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-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 198567.958515 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 216137.290733 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202715.044502 # average ReadReq mshr uncacheable latency
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-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 196838.390967 # average WriteReq mshr uncacheable latency
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-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 200958.851281 # average WriteReq mshr uncacheable latency
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system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements 1988229 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.436135 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 93879079 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 1988741 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 47.205282 # Average number of references to valid blocks.
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+system.cpu0.icache.tags.total_refs 93885937 # Total number of references to valid blocks.
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+system.cpu0.icache.tags.avg_refs 47.186285 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 12780860000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 432.331889 # Average occupied blocks per requestor
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system.cpu0.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id
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-system.cpu0.icache.tags.age_task_id_blocks_1024::2 191 # Occupied blocks per task id
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system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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-system.cpu0.icache.demand_misses::total 2032851 # number of demand (read+write) misses
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-system.cpu0.icache.ReadReq_miss_latency::total 18704880483 # number of ReadReq miss cycles
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-system.cpu0.icache.demand_miss_latency::total 18704880483 # number of demand (read+write) miss cycles
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-system.cpu0.icache.overall_accesses::cpu2.inst 10910815 # number of overall (read+write) accesses
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-system.cpu0.icache.overall_accesses::total 95911930 # number of overall (read+write) accesses
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-system.cpu0.icache.ReadReq_miss_rate::total 0.021195 # miss rate for ReadReq accesses
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system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.dtb.walker.walks 1881 # Table walker walks requested
-system.cpu1.dtb.walker.walksShort 1881 # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walks 1864 # Table walker walks requested
+system.cpu1.dtb.walker.walksShort 1864 # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 484 # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1397 # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walkWaitTime::samples 1881 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0 1881 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total 1881 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples 1593 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 14363.151287 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 12650.519591 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 6659.719490 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::4096-6143 280 17.58% 17.58% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::6144-8191 51 3.20% 20.78% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::10240-12287 461 28.94% 49.72% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::12288-14335 64 4.02% 53.74% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::14336-16383 240 15.07% 68.80% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::16384-18431 70 4.39% 73.20% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::22528-24575 406 25.49% 98.68% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::24576-26623 21 1.32% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total 1593 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1380 # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walkWaitTime::samples 1864 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0 1864 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total 1864 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples 1576 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 14376.903553 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 12683.026885 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 6626.503749 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::4096-6143 273 17.32% 17.32% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::6144-8191 48 3.05% 20.37% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::10240-12287 463 29.38% 49.75% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::12288-14335 60 3.81% 53.55% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::14336-16383 242 15.36% 68.91% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::16384-18431 70 4.44% 73.35% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::22528-24575 399 25.32% 98.67% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::24576-26623 21 1.33% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total 1576 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 1000016000 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0 1000016000 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 1000016000 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K 1111 69.74% 69.74% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M 482 30.26% 100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total 1593 # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 1881 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkPageSizes::4K 1094 69.42% 69.42% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M 482 30.58% 100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total 1576 # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 1864 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 1881 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1593 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 1864 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1576 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1593 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total 3474 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1576 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total 3440 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 3874640 # DTB read hits
-system.cpu1.dtb.read_misses 1654 # DTB read misses
-system.cpu1.dtb.write_hits 2733455 # DTB write hits
-system.cpu1.dtb.write_misses 227 # DTB write misses
+system.cpu1.dtb.read_hits 3874336 # DTB read hits
+system.cpu1.dtb.read_misses 1644 # DTB read misses
+system.cpu1.dtb.write_hits 2735867 # DTB write hits
+system.cpu1.dtb.write_misses 220 # DTB write misses
system.cpu1.dtb.flush_tlb 150 # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva 133 # Number of times TLB was flushed by MVA
+system.cpu1.dtb.flush_tlb_mva 124 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 1091 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries 1077 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 239 # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults 240 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 64 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 3876294 # DTB read accesses
-system.cpu1.dtb.write_accesses 2733682 # DTB write accesses
+system.cpu1.dtb.perms_faults 62 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 3875980 # DTB read accesses
+system.cpu1.dtb.write_accesses 2736087 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 6608095 # DTB hits
-system.cpu1.dtb.misses 1881 # DTB misses
-system.cpu1.dtb.accesses 6609976 # DTB accesses
+system.cpu1.dtb.hits 6610203 # DTB hits
+system.cpu1.dtb.misses 1864 # DTB misses
+system.cpu1.dtb.accesses 6612067 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.walker.walks 931 # Table walker walks requested
-system.cpu1.itb.walker.walksShort 931 # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walks 917 # Table walker walks requested
+system.cpu1.itb.walker.walksShort 917 # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1 177 # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksShortTerminationLevel::Level2 754 # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples 931 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0 931 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total 931 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples 674 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 13750.741840 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 12141.602155 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 6305.334498 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::4096-6143 145 21.51% 21.51% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::6144-8191 1 0.15% 21.66% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::10240-12287 171 25.37% 47.03% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::12288-14335 42 6.23% 53.26% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::14336-16383 173 25.67% 78.93% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::22528-24575 137 20.33% 99.26% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::24576-26623 5 0.74% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total 674 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2 740 # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples 917 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0 917 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total 917 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples 666 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 13797.297297 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 12192.351828 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 6305.163791 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::4096-6143 141 21.17% 21.17% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::6144-8191 1 0.15% 21.32% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::10240-12287 171 25.68% 47.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::12288-14335 40 6.01% 53.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::14336-16383 171 25.68% 78.68% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::22528-24575 137 20.57% 99.25% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::24576-26623 5 0.75% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total 666 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K 497 73.74% 73.74% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::1M 177 26.26% 100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total 674 # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::4K 489 73.42% 73.42% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M 177 26.58% 100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total 666 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 931 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total 931 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 917 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total 917 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 674 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total 674 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total 1605 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 18095406 # ITB inst hits
-system.cpu1.itb.inst_misses 931 # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 666 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total 666 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total 1583 # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits 18092232 # ITB inst hits
+system.cpu1.itb.inst_misses 917 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 150 # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva 133 # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb_mva 124 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 705 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 697 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 18096337 # ITB inst accesses
-system.cpu1.itb.hits 18095406 # DTB hits
-system.cpu1.itb.misses 931 # DTB misses
-system.cpu1.itb.accesses 18096337 # DTB accesses
-system.cpu1.numCycles 144011073 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 18093149 # ITB inst accesses
+system.cpu1.itb.hits 18092232 # DTB hits
+system.cpu1.itb.misses 917 # DTB misses
+system.cpu1.itb.accesses 18093149 # DTB accesses
+system.cpu1.numCycles 144011117 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu1.committedInsts 17425922 # Number of instructions committed
-system.cpu1.committedOps 20908303 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 18576861 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 1355 # Number of float alu accesses
-system.cpu1.num_func_calls 1992339 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 2240244 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 18576861 # number of integer instructions
-system.cpu1.num_fp_insts 1355 # number of float instructions
-system.cpu1.num_int_register_reads 34373942 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 13031779 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 1159 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 196 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 76108520 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 7595432 # number of times the CC registers were written
-system.cpu1.num_mem_refs 6800589 # number of memory refs
-system.cpu1.num_load_insts 3916596 # Number of load instructions
-system.cpu1.num_store_insts 2883993 # Number of store instructions
-system.cpu1.num_idle_cycles 136777457.840207 # Number of idle cycles
-system.cpu1.num_busy_cycles 7233615.159793 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.050230 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.949770 # Percentage of idle cycles
-system.cpu1.Branches 4344988 # Number of branches fetched
-system.cpu1.op_class::No_OpClass 22 0.00% 0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu 14692274 68.30% 68.30% # Class of executed instruction
-system.cpu1.op_class::IntMult 16424 0.08% 68.38% # Class of executed instruction
-system.cpu1.op_class::IntDiv 0 0.00% 68.38% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 0 0.00% 68.38% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 0 0.00% 68.38% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 0 0.00% 68.38% # Class of executed instruction
-system.cpu1.op_class::FloatMult 0 0.00% 68.38% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 0 0.00% 68.38% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 68.38% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 68.38% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 68.38% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 68.38% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 68.38% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 68.38% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 68.38% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 68.38% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 68.38% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 68.38% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.38% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 68.38% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.38% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.38% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.38% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.38% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.38% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 958 0.00% 68.38% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 68.38% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.38% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.38% # Class of executed instruction
-system.cpu1.op_class::MemRead 3916596 18.21% 86.59% # Class of executed instruction
-system.cpu1.op_class::MemWrite 2883993 13.41% 100.00% # Class of executed instruction
+system.cpu1.committedInsts 17422083 # Number of instructions committed
+system.cpu1.committedOps 20907241 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 18575942 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 1372 # Number of float alu accesses
+system.cpu1.num_func_calls 1991871 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 2240039 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 18575942 # number of integer instructions
+system.cpu1.num_fp_insts 1372 # number of float instructions
+system.cpu1.num_int_register_reads 34372457 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 13029259 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 1112 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 260 # number of times the floating registers were written
+system.cpu1.num_cc_register_reads 76102433 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 7596638 # number of times the CC registers were written
+system.cpu1.num_mem_refs 6802434 # number of memory refs
+system.cpu1.num_load_insts 3915999 # Number of load instructions
+system.cpu1.num_store_insts 2886435 # Number of store instructions
+system.cpu1.num_idle_cycles 136776220.801950 # Number of idle cycles
+system.cpu1.num_busy_cycles 7234896.198050 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.050238 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.949762 # Percentage of idle cycles
+system.cpu1.Branches 4344241 # Number of branches fetched
+system.cpu1.op_class::No_OpClass 21 0.00% 0.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu 14689053 68.29% 68.29% # Class of executed instruction
+system.cpu1.op_class::IntMult 16409 0.08% 68.37% # Class of executed instruction
+system.cpu1.op_class::IntDiv 0 0.00% 68.37% # Class of executed instruction
+system.cpu1.op_class::FloatAdd 0 0.00% 68.37% # Class of executed instruction
+system.cpu1.op_class::FloatCmp 0 0.00% 68.37% # Class of executed instruction
+system.cpu1.op_class::FloatCvt 0 0.00% 68.37% # Class of executed instruction
+system.cpu1.op_class::FloatMult 0 0.00% 68.37% # Class of executed instruction
+system.cpu1.op_class::FloatDiv 0 0.00% 68.37% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt 0 0.00% 68.37% # Class of executed instruction
+system.cpu1.op_class::SimdAdd 0 0.00% 68.37% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc 0 0.00% 68.37% # Class of executed instruction
+system.cpu1.op_class::SimdAlu 0 0.00% 68.37% # Class of executed instruction
+system.cpu1.op_class::SimdCmp 0 0.00% 68.37% # Class of executed instruction
+system.cpu1.op_class::SimdCvt 0 0.00% 68.37% # Class of executed instruction
+system.cpu1.op_class::SimdMisc 0 0.00% 68.37% # Class of executed instruction
+system.cpu1.op_class::SimdMult 0 0.00% 68.37% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc 0 0.00% 68.37% # Class of executed instruction
+system.cpu1.op_class::SimdShift 0 0.00% 68.37% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.37% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt 0 0.00% 68.37% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.37% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.37% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.37% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.37% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.37% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 960 0.00% 68.37% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult 0 0.00% 68.37% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.37% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.37% # Class of executed instruction
+system.cpu1.op_class::MemRead 3915999 18.21% 86.58% # Class of executed instruction
+system.cpu1.op_class::MemWrite 2886435 13.42% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 21510267 # Class of executed instruction
-system.cpu2.branchPred.lookups 5796775 # Number of BP lookups
-system.cpu2.branchPred.condPredicted 2983658 # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect 509824 # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups 3342660 # Number of BTB lookups
-system.cpu2.branchPred.BTBHits 2404944 # Number of BTB hits
+system.cpu1.op_class::total 21508877 # Class of executed instruction
+system.cpu2.branchPred.lookups 5793612 # Number of BP lookups
+system.cpu2.branchPred.condPredicted 2980826 # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect 510173 # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups 3341090 # Number of BTB lookups
+system.cpu2.branchPred.BTBHits 2404622 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct 71.947012 # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS 1622496 # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect 331360 # Number of incorrect RAS predictions.
+system.cpu2.branchPred.BTBHitPct 71.971183 # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS 1623448 # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect 331512 # Number of incorrect RAS predictions.
system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu2.dtb.walker.walks 13089 # Table walker walks requested
-system.cpu2.dtb.walker.walksShort 13089 # Table walker walks initiated with short descriptors
-system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 8217 # Level at which table walker walks with short descriptors terminate
-system.cpu2.dtb.walker.walksShortTerminationLevel::Level2 4872 # Level at which table walker walks with short descriptors terminate
-system.cpu2.dtb.walker.walkWaitTime::samples 13089 # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::0 13089 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::total 13089 # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkCompletionTime::samples 2190 # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::mean 13303.881279 # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::gmean 11625.278622 # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::stdev 8511.286061 # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::0-32767 2189 99.95% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walks 13179 # Table walker walks requested
+system.cpu2.dtb.walker.walksShort 13179 # Table walker walks initiated with short descriptors
+system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 8247 # Level at which table walker walks with short descriptors terminate
+system.cpu2.dtb.walker.walksShortTerminationLevel::Level2 4932 # Level at which table walker walks with short descriptors terminate
+system.cpu2.dtb.walker.walkWaitTime::samples 13179 # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::0 13179 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::total 13179 # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkCompletionTime::samples 2214 # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::mean 13311.653117 # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::gmean 11619.348750 # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::stdev 8511.573667 # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::0-32767 2213 99.95% 99.95% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::262144-294911 1 0.05% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::total 2190 # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::total 2214 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walksPending::samples 2000052000 # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::0 2000052000 100.00% 100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::total 2000052000 # Table walker pending requests distribution
-system.cpu2.dtb.walker.walkPageSizes::4K 1357 61.96% 61.96% # Table walker page sizes translated
-system.cpu2.dtb.walker.walkPageSizes::1M 833 38.04% 100.00% # Table walker page sizes translated
-system.cpu2.dtb.walker.walkPageSizes::total 2190 # Table walker page sizes translated
-system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 13089 # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkPageSizes::4K 1376 62.15% 62.15% # Table walker page sizes translated
+system.cpu2.dtb.walker.walkPageSizes::1M 838 37.85% 100.00% # Table walker page sizes translated
+system.cpu2.dtb.walker.walkPageSizes::total 2214 # Table walker page sizes translated
+system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 13179 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 13089 # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 2190 # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 13179 # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 2214 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 2190 # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin::total 15279 # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 2214 # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin::total 15393 # Table walker requests started/completed, data/inst
system.cpu2.dtb.inst_hits 0 # ITB inst hits
system.cpu2.dtb.inst_misses 0 # ITB inst misses
-system.cpu2.dtb.read_hits 4658776 # DTB read hits
-system.cpu2.dtb.read_misses 11701 # DTB read misses
-system.cpu2.dtb.write_hits 3572503 # DTB write hits
-system.cpu2.dtb.write_misses 1388 # DTB write misses
-system.cpu2.dtb.flush_tlb 153 # Number of times complete TLB was flushed
-system.cpu2.dtb.flush_tlb_mva 167 # Number of times TLB was flushed by MVA
+system.cpu2.dtb.read_hits 4658745 # DTB read hits
+system.cpu2.dtb.read_misses 11783 # DTB read misses
+system.cpu2.dtb.write_hits 3577519 # DTB write hits
+system.cpu2.dtb.write_misses 1396 # DTB write misses
+system.cpu2.dtb.flush_tlb 154 # Number of times complete TLB was flushed
+system.cpu2.dtb.flush_tlb_mva 176 # Number of times TLB was flushed by MVA
system.cpu2.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu2.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu2.dtb.flush_entries 1490 # Number of entries that have been flushed from TLB
-system.cpu2.dtb.align_faults 207 # Number of TLB faults due to alignment restrictions
-system.cpu2.dtb.prefetch_faults 330 # Number of TLB faults due to prefetch
+system.cpu2.dtb.flush_entries 1514 # Number of entries that have been flushed from TLB
+system.cpu2.dtb.align_faults 206 # Number of TLB faults due to alignment restrictions
+system.cpu2.dtb.prefetch_faults 331 # Number of TLB faults due to prefetch
system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu2.dtb.perms_faults 125 # Number of TLB faults due to permissions restrictions
-system.cpu2.dtb.read_accesses 4670477 # DTB read accesses
-system.cpu2.dtb.write_accesses 3573891 # DTB write accesses
+system.cpu2.dtb.perms_faults 124 # Number of TLB faults due to permissions restrictions
+system.cpu2.dtb.read_accesses 4670528 # DTB read accesses
+system.cpu2.dtb.write_accesses 3578915 # DTB write accesses
system.cpu2.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu2.dtb.hits 8231279 # DTB hits
-system.cpu2.dtb.misses 13089 # DTB misses
-system.cpu2.dtb.accesses 8244368 # DTB accesses
+system.cpu2.dtb.hits 8236264 # DTB hits
+system.cpu2.dtb.misses 13179 # DTB misses
+system.cpu2.dtb.accesses 8249443 # DTB accesses
system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu2.itb.walker.walks 1368 # Table walker walks requested
-system.cpu2.itb.walker.walksShort 1368 # Table walker walks initiated with short descriptors
-system.cpu2.itb.walker.walksShortTerminationLevel::Level1 248 # Level at which table walker walks with short descriptors terminate
-system.cpu2.itb.walker.walksShortTerminationLevel::Level2 1120 # Level at which table walker walks with short descriptors terminate
-system.cpu2.itb.walker.walkWaitTime::samples 1368 # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::0 1368 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::total 1368 # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkCompletionTime::samples 861 # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::mean 13222.996516 # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::gmean 11667.249033 # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::stdev 6172.725517 # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::4096-6143 213 24.74% 24.74% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::6144-8191 1 0.12% 24.85% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::10240-12287 235 27.29% 52.15% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::12288-14335 37 4.30% 56.45% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::14336-16383 216 25.09% 81.53% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::22528-24575 156 18.12% 99.65% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::24576-26623 3 0.35% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::total 861 # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walks 1381 # Table walker walks requested
+system.cpu2.itb.walker.walksShort 1381 # Table walker walks initiated with short descriptors
+system.cpu2.itb.walker.walksShortTerminationLevel::Level1 251 # Level at which table walker walks with short descriptors terminate
+system.cpu2.itb.walker.walksShortTerminationLevel::Level2 1130 # Level at which table walker walks with short descriptors terminate
+system.cpu2.itb.walker.walkWaitTime::samples 1381 # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::0 1381 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::total 1381 # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkCompletionTime::samples 875 # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::mean 13237.714286 # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::gmean 11667.376673 # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::stdev 6208.114147 # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::4096-6143 218 24.91% 24.91% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::6144-8191 1 0.11% 25.03% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::10240-12287 241 27.54% 52.57% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::12288-14335 34 3.89% 56.46% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::14336-16383 216 24.69% 81.14% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::22528-24575 162 18.51% 99.66% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::24576-26623 3 0.34% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::total 875 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walksPending::samples 2000037500 # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::0 2000037500 100.00% 100.00% # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::total 2000037500 # Table walker pending requests distribution
-system.cpu2.itb.walker.walkPageSizes::4K 613 71.20% 71.20% # Table walker page sizes translated
-system.cpu2.itb.walker.walkPageSizes::1M 248 28.80% 100.00% # Table walker page sizes translated
-system.cpu2.itb.walker.walkPageSizes::total 861 # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::4K 624 71.31% 71.31% # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::1M 251 28.69% 100.00% # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::total 875 # Table walker page sizes translated
system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 1368 # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Requested::total 1368 # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 1381 # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Requested::total 1381 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 861 # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Completed::total 861 # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin::total 2229 # Table walker requests started/completed, data/inst
-system.cpu2.itb.inst_hits 10912675 # ITB inst hits
-system.cpu2.itb.inst_misses 1368 # ITB inst misses
+system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 875 # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Completed::total 875 # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin::total 2256 # Table walker requests started/completed, data/inst
+system.cpu2.itb.inst_hits 10914034 # ITB inst hits
+system.cpu2.itb.inst_misses 1381 # ITB inst misses
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.write_hits 0 # DTB write hits
system.cpu2.itb.write_misses 0 # DTB write misses
-system.cpu2.itb.flush_tlb 153 # Number of times complete TLB was flushed
-system.cpu2.itb.flush_tlb_mva 167 # Number of times TLB was flushed by MVA
+system.cpu2.itb.flush_tlb 154 # Number of times complete TLB was flushed
+system.cpu2.itb.flush_tlb_mva 176 # Number of times TLB was flushed by MVA
system.cpu2.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu2.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu2.itb.flush_entries 871 # Number of entries that have been flushed from TLB
+system.cpu2.itb.flush_entries 885 # Number of entries that have been flushed from TLB
system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu2.itb.perms_faults 1750 # Number of TLB faults due to permissions restrictions
+system.cpu2.itb.perms_faults 1797 # Number of TLB faults due to permissions restrictions
system.cpu2.itb.read_accesses 0 # DTB read accesses
system.cpu2.itb.write_accesses 0 # DTB write accesses
-system.cpu2.itb.inst_accesses 10914043 # ITB inst accesses
-system.cpu2.itb.hits 10912675 # DTB hits
-system.cpu2.itb.misses 1368 # DTB misses
-system.cpu2.itb.accesses 10914043 # DTB accesses
-system.cpu2.numCycles 1393518293 # number of cpu cycles simulated
+system.cpu2.itb.inst_accesses 10915415 # ITB inst accesses
+system.cpu2.itb.hits 10914034 # DTB hits
+system.cpu2.itb.misses 1381 # DTB misses
+system.cpu2.itb.accesses 10915415 # DTB accesses
+system.cpu2.numCycles 1393570543 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.committedInsts 20499509 # Number of instructions committed
-system.cpu2.committedOps 24824986 # Number of ops (including micro ops) committed
-system.cpu2.discardedOps 1466668 # Number of ops (including micro ops) which were discarded before commit
-system.cpu2.numFetchSuspends 563 # Number of times Execute suspended instruction fetching
-system.cpu2.quiesceCycles 4256214875 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.cpi 67.978130 # CPI: cycles per instruction
+system.cpu2.committedInsts 20500176 # Number of instructions committed
+system.cpu2.committedOps 24831062 # Number of ops (including micro ops) committed
+system.cpu2.discardedOps 1467933 # Number of ops (including micro ops) which were discarded before commit
+system.cpu2.numFetchSuspends 564 # Number of times Execute suspended instruction fetching
+system.cpu2.quiesceCycles 4256215364 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.cpi 67.978467 # CPI: cycles per instruction
system.cpu2.ipc 0.014711 # IPC: instructions per cycle
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu2.tickCycles 42617577 # Number of cycles that the object actually ticked
-system.cpu2.idleCycles 1350900716 # Total number of cycles that the object has spent stopped
-system.cpu3.branchPred.lookups 13279535 # Number of BP lookups
-system.cpu3.branchPred.condPredicted 7247058 # Number of conditional branches predicted
-system.cpu3.branchPred.condIncorrect 312507 # Number of conditional branches incorrect
-system.cpu3.branchPred.BTBLookups 8265977 # Number of BTB lookups
-system.cpu3.branchPred.BTBHits 6247053 # Number of BTB hits
+system.cpu2.tickCycles 42639934 # Number of cycles that the object actually ticked
+system.cpu2.idleCycles 1350930609 # Total number of cycles that the object has spent stopped
+system.cpu3.branchPred.lookups 13289019 # Number of BP lookups
+system.cpu3.branchPred.condPredicted 7253126 # Number of conditional branches predicted
+system.cpu3.branchPred.condIncorrect 312439 # Number of conditional branches incorrect
+system.cpu3.branchPred.BTBLookups 8263558 # Number of BTB lookups
+system.cpu3.branchPred.BTBHits 6253160 # Number of BTB hits
system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu3.branchPred.BTBHitPct 75.575495 # BTB Hit Percentage
-system.cpu3.branchPred.usedRAS 3099050 # Number of times the RAS was used to get a target.
-system.cpu3.branchPred.RASInCorrect 16324 # Number of incorrect RAS predictions.
+system.cpu3.branchPred.BTBHitPct 75.671521 # BTB Hit Percentage
+system.cpu3.branchPred.usedRAS 3098416 # Number of times the RAS was used to get a target.
+system.cpu3.branchPred.RASInCorrect 16246 # Number of incorrect RAS predictions.
system.cpu3.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu3.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu3.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu3.dtb.walker.walks 33115 # Table walker walks requested
-system.cpu3.dtb.walker.walksShort 33115 # Table walker walks initiated with short descriptors
-system.cpu3.dtb.walker.walksShortTerminationLevel::Level1 11558 # Level at which table walker walks with short descriptors terminate
-system.cpu3.dtb.walker.walksShortTerminationLevel::Level2 7619 # Level at which table walker walks with short descriptors terminate
-system.cpu3.dtb.walker.walksSquashedBefore 13938 # Table walks squashed before starting
-system.cpu3.dtb.walker.walkWaitTime::samples 19177 # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::mean 468.973249 # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::stdev 3138.682305 # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::0-8191 18760 97.83% 97.83% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::8192-16383 261 1.36% 99.19% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::16384-24575 95 0.50% 99.68% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::24576-32767 29 0.15% 99.83% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::32768-40959 11 0.06% 99.89% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walks 32928 # Table walker walks requested
+system.cpu3.dtb.walker.walksShort 32928 # Table walker walks initiated with short descriptors
+system.cpu3.dtb.walker.walksShortTerminationLevel::Level1 11539 # Level at which table walker walks with short descriptors terminate
+system.cpu3.dtb.walker.walksShortTerminationLevel::Level2 7550 # Level at which table walker walks with short descriptors terminate
+system.cpu3.dtb.walker.walksSquashedBefore 13839 # Table walks squashed before starting
+system.cpu3.dtb.walker.walkWaitTime::samples 19089 # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::mean 453.769186 # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::stdev 3060.650979 # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::0-8191 18684 97.88% 97.88% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::8192-16383 255 1.34% 99.21% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::16384-24575 92 0.48% 99.70% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::24576-32767 26 0.14% 99.83% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::32768-40959 12 0.06% 99.90% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::40960-49151 11 0.06% 99.95% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::49152-57343 5 0.03% 99.97% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::49152-57343 5 0.03% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::57344-65535 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::65536-73727 4 0.02% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::total 19177 # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkCompletionTime::samples 6222 # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::mean 13175.506268 # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::gmean 10775.791198 # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::stdev 8313.068780 # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::0-16383 4548 73.10% 73.10% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::16384-32767 1554 24.98% 98.07% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::32768-49151 108 1.74% 99.81% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::49152-65535 9 0.14% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkWaitTime::65536-73727 3 0.02% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::total 19089 # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkCompletionTime::samples 6197 # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::mean 13294.578022 # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::gmean 10885.248950 # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::stdev 8635.189295 # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::0-16383 4539 73.25% 73.25% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::16384-32767 1528 24.66% 97.90% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::32768-49151 104 1.68% 99.58% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::49152-65535 10 0.16% 99.74% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::65536-81919 13 0.21% 99.95% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::81920-98303 1 0.02% 99.97% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::131072-147455 1 0.02% 99.98% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::147456-163839 1 0.02% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::total 6222 # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walksPending::samples -8045387064 # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::mean 1.137184 # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::0-1 -8091405064 100.57% 100.57% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::2-3 33349500 -0.41% 100.16% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::4-5 6720000 -0.08% 100.07% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::6-7 2348000 -0.03% 100.04% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::8-9 1216500 -0.02% 100.03% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::10-11 680000 -0.01% 100.02% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::12-13 415500 -0.01% 100.02% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::14-15 841500 -0.01% 100.01% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::16-17 133000 -0.00% 100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::18-19 159500 -0.00% 100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::20-21 77000 -0.00% 100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::22-23 11000 -0.00% 100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::24-25 34000 -0.00% 100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::26-27 10000 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walkCompletionTime::total 6197 # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walksPending::samples -8048051564 # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::mean 0.976034 # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::0-1 -8093653564 100.57% 100.57% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::2-3 33199000 -0.41% 100.15% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::4-5 6574500 -0.08% 100.07% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::6-7 2215500 -0.03% 100.04% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::8-9 1246000 -0.02% 100.03% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::10-11 692500 -0.01% 100.02% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::12-13 364000 -0.00% 100.02% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::14-15 852000 -0.01% 100.01% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::16-17 153000 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::18-19 182500 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::20-21 65500 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::22-23 10500 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::24-25 20000 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::26-27 4500 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::28-29 3500 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::30-31 19000 -0.00% 100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::total -8045387064 # Table walker pending requests distribution
-system.cpu3.dtb.walker.walkPageSizes::4K 1814 68.95% 68.95% # Table walker page sizes translated
-system.cpu3.dtb.walker.walkPageSizes::1M 817 31.05% 100.00% # Table walker page sizes translated
-system.cpu3.dtb.walker.walkPageSizes::total 2631 # Table walker page sizes translated
-system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 33115 # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walksPending::total -8048051564 # Table walker pending requests distribution
+system.cpu3.dtb.walker.walkPageSizes::4K 1804 69.07% 69.07% # Table walker page sizes translated
+system.cpu3.dtb.walker.walkPageSizes::1M 808 30.93% 100.00% # Table walker page sizes translated
+system.cpu3.dtb.walker.walkPageSizes::total 2612 # Table walker page sizes translated
+system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 32928 # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 33115 # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 2631 # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 32928 # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 2612 # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 2631 # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin::total 35746 # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 2612 # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin::total 35540 # Table walker requests started/completed, data/inst
system.cpu3.dtb.inst_hits 0 # ITB inst hits
system.cpu3.dtb.inst_misses 0 # ITB inst misses
-system.cpu3.dtb.read_hits 7259419 # DTB read hits
-system.cpu3.dtb.read_misses 28704 # DTB read misses
-system.cpu3.dtb.write_hits 5430970 # DTB write hits
-system.cpu3.dtb.write_misses 4411 # DTB write misses
-system.cpu3.dtb.flush_tlb 162 # Number of times complete TLB was flushed
-system.cpu3.dtb.flush_tlb_mva 274 # Number of times TLB was flushed by MVA
+system.cpu3.dtb.read_hits 7260437 # DTB read hits
+system.cpu3.dtb.read_misses 28509 # DTB read misses
+system.cpu3.dtb.write_hits 5425830 # DTB write hits
+system.cpu3.dtb.write_misses 4419 # DTB write misses
+system.cpu3.dtb.flush_tlb 161 # Number of times complete TLB was flushed
+system.cpu3.dtb.flush_tlb_mva 272 # Number of times TLB was flushed by MVA
system.cpu3.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu3.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu3.dtb.flush_entries 1937 # Number of entries that have been flushed from TLB
+system.cpu3.dtb.flush_entries 1914 # Number of entries that have been flushed from TLB
system.cpu3.dtb.align_faults 485 # Number of TLB faults due to alignment restrictions
-system.cpu3.dtb.prefetch_faults 827 # Number of TLB faults due to prefetch
+system.cpu3.dtb.prefetch_faults 810 # Number of TLB faults due to prefetch
system.cpu3.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu3.dtb.perms_faults 313 # Number of TLB faults due to permissions restrictions
-system.cpu3.dtb.read_accesses 7288123 # DTB read accesses
-system.cpu3.dtb.write_accesses 5435381 # DTB write accesses
+system.cpu3.dtb.perms_faults 320 # Number of TLB faults due to permissions restrictions
+system.cpu3.dtb.read_accesses 7288946 # DTB read accesses
+system.cpu3.dtb.write_accesses 5430249 # DTB write accesses
system.cpu3.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu3.dtb.hits 12690389 # DTB hits
-system.cpu3.dtb.misses 33115 # DTB misses
-system.cpu3.dtb.accesses 12723504 # DTB accesses
+system.cpu3.dtb.hits 12686267 # DTB hits
+system.cpu3.dtb.misses 32928 # DTB misses
+system.cpu3.dtb.accesses 12719195 # DTB accesses
system.cpu3.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu3.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu3.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu3.itb.walker.walks 4611 # Table walker walks requested
-system.cpu3.itb.walker.walksShort 4611 # Table walker walks initiated with short descriptors
-system.cpu3.itb.walker.walksShortTerminationLevel::Level1 1576 # Level at which table walker walks with short descriptors terminate
-system.cpu3.itb.walker.walksShortTerminationLevel::Level2 2936 # Level at which table walker walks with short descriptors terminate
-system.cpu3.itb.walker.walksSquashedBefore 99 # Table walks squashed before starting
-system.cpu3.itb.walker.walkWaitTime::samples 4512 # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::mean 1190.824468 # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::stdev 4827.188758 # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::0-8191 4272 94.68% 94.68% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::8192-16383 112 2.48% 97.16% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::16384-24575 85 1.88% 99.05% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::24576-32767 29 0.64% 99.69% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::32768-40959 6 0.13% 99.82% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::40960-49151 4 0.09% 99.91% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::49152-57343 1 0.02% 99.93% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::57344-65535 1 0.02% 99.96% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::65536-73727 1 0.02% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::73728-81919 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::total 4512 # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkCompletionTime::samples 1416 # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::mean 13825.918079 # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::gmean 11456.247028 # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::stdev 8136.352957 # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::0-4095 24 1.69% 1.69% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::4096-8191 390 27.54% 29.24% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::8192-12287 346 24.44% 53.67% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::12288-16383 256 18.08% 71.75% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::16384-20479 18 1.27% 73.02% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::20480-24575 314 22.18% 95.20% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::24576-28671 43 3.04% 98.23% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::28672-32767 4 0.28% 98.52% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::32768-36863 3 0.21% 98.73% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::36864-40959 3 0.21% 98.94% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::40960-45055 8 0.56% 99.51% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::45056-49151 3 0.21% 99.72% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::53248-57343 1 0.07% 99.79% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::57344-61439 2 0.14% 99.93% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::61440-65535 1 0.07% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::total 1416 # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walksPending::samples -3903952768 # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::mean 0.701862 # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::stdev 0.456296 # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::0 -1162140296 29.77% 29.77% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::1 -2743359472 70.27% 100.04% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::2 1351500 -0.03% 100.01% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::3 161000 -0.00% 100.00% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::4 34500 -0.00% 100.00% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::total -3903952768 # Table walker pending requests distribution
-system.cpu3.itb.walker.walkPageSizes::4K 967 73.42% 73.42% # Table walker page sizes translated
-system.cpu3.itb.walker.walkPageSizes::1M 350 26.58% 100.00% # Table walker page sizes translated
-system.cpu3.itb.walker.walkPageSizes::total 1317 # Table walker page sizes translated
+system.cpu3.itb.walker.walks 4959 # Table walker walks requested
+system.cpu3.itb.walker.walksShort 4959 # Table walker walks initiated with short descriptors
+system.cpu3.itb.walker.walksShortTerminationLevel::Level1 1575 # Level at which table walker walks with short descriptors terminate
+system.cpu3.itb.walker.walksShortTerminationLevel::Level2 2956 # Level at which table walker walks with short descriptors terminate
+system.cpu3.itb.walker.walksSquashedBefore 428 # Table walks squashed before starting
+system.cpu3.itb.walker.walkWaitTime::samples 4531 # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::mean 1378.172589 # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::stdev 5474.247381 # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::0-8191 4267 94.17% 94.17% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::8192-16383 125 2.76% 96.93% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::16384-24575 86 1.90% 98.83% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::24576-32767 32 0.71% 99.54% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::32768-40959 9 0.20% 99.74% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::40960-49151 4 0.09% 99.82% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::49152-57343 1 0.02% 99.85% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::57344-65535 2 0.04% 99.89% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::65536-73727 2 0.04% 99.93% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::73728-81919 2 0.04% 99.98% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::81920-90111 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::total 4531 # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkCompletionTime::samples 1743 # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::mean 12810.097533 # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::gmean 10341.257314 # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::stdev 8222.199176 # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::0-4095 24 1.38% 1.38% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::4096-8191 622 35.69% 37.06% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::8192-12287 348 19.97% 57.03% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::12288-16383 324 18.59% 75.62% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::16384-20479 26 1.49% 77.11% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::20480-24575 315 18.07% 95.18% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::24576-28671 50 2.87% 98.05% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::28672-32767 6 0.34% 98.39% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::32768-36863 6 0.34% 98.74% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::36864-40959 6 0.34% 99.08% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::40960-45055 8 0.46% 99.54% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::45056-49151 4 0.23% 99.77% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::53248-57343 1 0.06% 99.83% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::57344-61439 2 0.11% 99.94% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::61440-65535 1 0.06% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::total 1743 # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walksPending::samples -4005171768 # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::mean -0.325586 # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::0 -5306419980 132.49% 132.49% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::1 1298923212 -32.43% 100.06% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::2 1978000 -0.05% 100.01% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::3 238000 -0.01% 100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::4 109000 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::total -4005171768 # Table walker pending requests distribution
+system.cpu3.itb.walker.walkPageSizes::4K 967 73.54% 73.54% # Table walker page sizes translated
+system.cpu3.itb.walker.walkPageSizes::1M 348 26.46% 100.00% # Table walker page sizes translated
+system.cpu3.itb.walker.walkPageSizes::total 1315 # Table walker page sizes translated
system.cpu3.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 4611 # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Requested::total 4611 # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 4959 # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Requested::total 4959 # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 1317 # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Completed::total 1317 # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin::total 5928 # Table walker requests started/completed, data/inst
-system.cpu3.itb.inst_hits 9805675 # ITB inst hits
-system.cpu3.itb.inst_misses 4611 # ITB inst misses
+system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 1315 # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Completed::total 1315 # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin::total 6274 # Table walker requests started/completed, data/inst
+system.cpu3.itb.inst_hits 9813721 # ITB inst hits
+system.cpu3.itb.inst_misses 4959 # ITB inst misses
system.cpu3.itb.read_hits 0 # DTB read hits
system.cpu3.itb.read_misses 0 # DTB read misses
system.cpu3.itb.write_hits 0 # DTB write hits
system.cpu3.itb.write_misses 0 # DTB write misses
-system.cpu3.itb.flush_tlb 162 # Number of times complete TLB was flushed
-system.cpu3.itb.flush_tlb_mva 274 # Number of times TLB was flushed by MVA
+system.cpu3.itb.flush_tlb 161 # Number of times complete TLB was flushed
+system.cpu3.itb.flush_tlb_mva 272 # Number of times TLB was flushed by MVA
system.cpu3.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu3.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu3.itb.flush_entries 1315 # Number of entries that have been flushed from TLB
+system.cpu3.itb.flush_entries 1311 # Number of entries that have been flushed from TLB
system.cpu3.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu3.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu3.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu3.itb.perms_faults 717 # Number of TLB faults due to permissions restrictions
+system.cpu3.itb.perms_faults 728 # Number of TLB faults due to permissions restrictions
system.cpu3.itb.read_accesses 0 # DTB read accesses
system.cpu3.itb.write_accesses 0 # DTB write accesses
-system.cpu3.itb.inst_accesses 9810286 # ITB inst accesses
-system.cpu3.itb.hits 9805675 # DTB hits
-system.cpu3.itb.misses 4611 # DTB misses
-system.cpu3.itb.accesses 9810286 # DTB accesses
-system.cpu3.numCycles 58198080 # number of cpu cycles simulated
+system.cpu3.itb.inst_accesses 9818680 # ITB inst accesses
+system.cpu3.itb.hits 9813721 # DTB hits
+system.cpu3.itb.misses 4959 # DTB misses
+system.cpu3.itb.accesses 9818680 # DTB accesses
+system.cpu3.numCycles 58198977 # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu3.fetch.icacheStallCycles 21004644 # Number of cycles fetch is stalled on an Icache miss
-system.cpu3.fetch.Insts 52275874 # Number of instructions fetch has processed
-system.cpu3.fetch.Branches 13279535 # Number of branches that fetch encountered
-system.cpu3.fetch.predictedBranches 9346103 # Number of branches that fetch has predicted taken
-system.cpu3.fetch.Cycles 34135840 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu3.fetch.SquashCycles 1598180 # Number of cycles fetch has spent squashing
-system.cpu3.fetch.TlbCycles 75752 # Number of cycles fetch has spent waiting for tlb
-system.cpu3.fetch.MiscStallCycles 771 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu3.fetch.PendingDrainCycles 231 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu3.fetch.PendingTrapStallCycles 170446 # Number of stall cycles due to pending traps
-system.cpu3.fetch.PendingQuiesceStallCycles 76408 # Number of stall cycles due to pending quiesce instructions
-system.cpu3.fetch.IcacheWaitRetryStallCycles 496 # Number of stall cycles due to full MSHR
-system.cpu3.fetch.CacheLines 9804624 # Number of cache lines fetched
-system.cpu3.fetch.IcacheSquashes 214264 # Number of outstanding Icache misses that were squashed
-system.cpu3.fetch.ItlbSquashes 2206 # Number of outstanding ITLB misses that were squashed
-system.cpu3.fetch.rateDist::samples 56263657 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::mean 1.123824 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::stdev 2.271758 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.icacheStallCycles 20997510 # Number of cycles fetch is stalled on an Icache miss
+system.cpu3.fetch.Insts 52319874 # Number of instructions fetch has processed
+system.cpu3.fetch.Branches 13289019 # Number of branches that fetch encountered
+system.cpu3.fetch.predictedBranches 9351576 # Number of branches that fetch has predicted taken
+system.cpu3.fetch.Cycles 34146869 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu3.fetch.SquashCycles 1603241 # Number of cycles fetch has spent squashing
+system.cpu3.fetch.TlbCycles 75601 # Number of cycles fetch has spent waiting for tlb
+system.cpu3.fetch.MiscStallCycles 830 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu3.fetch.PendingDrainCycles 252 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu3.fetch.PendingTrapStallCycles 167692 # Number of stall cycles due to pending traps
+system.cpu3.fetch.PendingQuiesceStallCycles 75270 # Number of stall cycles due to pending quiesce instructions
+system.cpu3.fetch.IcacheWaitRetryStallCycles 481 # Number of stall cycles due to full MSHR
+system.cpu3.fetch.CacheLines 9812317 # Number of cache lines fetched
+system.cpu3.fetch.IcacheSquashes 215159 # Number of outstanding Icache misses that were squashed
+system.cpu3.fetch.ItlbSquashes 2588 # Number of outstanding ITLB misses that were squashed
+system.cpu3.fetch.rateDist::samples 56266104 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::mean 1.124866 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::stdev 2.272811 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::0 42100278 74.83% 74.83% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::1 1838046 3.27% 78.09% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::2 1170997 2.08% 80.17% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::3 3679420 6.54% 86.71% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::4 917674 1.63% 88.35% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::5 559385 0.99% 89.34% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::6 2919080 5.19% 94.53% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::7 600185 1.07% 95.59% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::8 2478592 4.41% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::0 42091874 74.81% 74.81% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::1 1838725 3.27% 78.08% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::2 1172268 2.08% 80.16% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::3 3680170 6.54% 86.70% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::4 919176 1.63% 88.33% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::5 559542 0.99% 89.33% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::6 2920436 5.19% 94.52% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::7 600253 1.07% 95.59% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::8 2483660 4.41% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::total 56263657 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.branchRate 0.228178 # Number of branch fetches per cycle
-system.cpu3.fetch.rate 0.898241 # Number of inst fetches per cycle
-system.cpu3.decode.IdleCycles 14695652 # Number of cycles decode is idle
-system.cpu3.decode.BlockedCycles 32129586 # Number of cycles decode is blocked
-system.cpu3.decode.RunCycles 7839305 # Number of cycles decode is running
-system.cpu3.decode.UnblockCycles 889993 # Number of cycles decode is unblocking
-system.cpu3.decode.SquashCycles 708923 # Number of cycles decode is squashing
-system.cpu3.decode.BranchResolved 981902 # Number of times decode resolved a branch
-system.cpu3.decode.BranchMispred 91350 # Number of times decode detected a branch misprediction
-system.cpu3.decode.DecodedInsts 45004399 # Number of instructions handled by decode
-system.cpu3.decode.SquashedInsts 298008 # Number of squashed instructions handled by decode
-system.cpu3.rename.SquashCycles 708923 # Number of cycles rename is squashing
-system.cpu3.rename.IdleCycles 15180574 # Number of cycles rename is idle
-system.cpu3.rename.BlockCycles 3814501 # Number of cycles rename is blocking
-system.cpu3.rename.serializeStallCycles 22072917 # count of cycles rename stalled for serializing inst
-system.cpu3.rename.RunCycles 8236779 # Number of cycles rename is running
-system.cpu3.rename.UnblockCycles 6249745 # Number of cycles rename is unblocking
-system.cpu3.rename.RenamedInsts 43123968 # Number of instructions processed by rename
-system.cpu3.rename.ROBFullEvents 829 # Number of times rename has blocked due to ROB full
-system.cpu3.rename.IQFullEvents 908553 # Number of times rename has blocked due to IQ full
-system.cpu3.rename.LQFullEvents 90362 # Number of times rename has blocked due to LQ full
-system.cpu3.rename.SQFullEvents 4872933 # Number of times rename has blocked due to SQ full
-system.cpu3.rename.RenamedOperands 44747932 # Number of destination operands rename has renamed
-system.cpu3.rename.RenameLookups 198117330 # Number of register rename lookups that rename has made
-system.cpu3.rename.int_rename_lookups 48138419 # Number of integer rename lookups
-system.cpu3.rename.fp_rename_lookups 3926 # Number of floating rename lookups
-system.cpu3.rename.CommittedMaps 37260005 # Number of HB maps that are committed
-system.cpu3.rename.UndoneMaps 7487927 # Number of HB maps that are undone due to squashing
-system.cpu3.rename.serializingInsts 723224 # count of serializing insts renamed
-system.cpu3.rename.tempSerializingInsts 671648 # count of temporary serializing insts renamed
-system.cpu3.rename.skidInsts 5026285 # count of insts added to the skid buffer
-system.cpu3.memDep0.insertedLoads 7752515 # Number of loads inserted to the mem dependence unit.
-system.cpu3.memDep0.insertedStores 6007333 # Number of stores inserted to the mem dependence unit.
-system.cpu3.memDep0.conflictingLoads 1093193 # Number of conflicting loads.
-system.cpu3.memDep0.conflictingStores 1517567 # Number of conflicting stores.
-system.cpu3.iq.iqInstsAdded 41462674 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu3.iq.iqNonSpecInstsAdded 517140 # Number of non-speculative instructions added to the IQ
-system.cpu3.iq.iqInstsIssued 39449683 # Number of instructions issued
-system.cpu3.iq.iqSquashedInstsIssued 52518 # Number of squashed instructions issued
-system.cpu3.iq.iqSquashedInstsExamined 6046914 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu3.iq.iqSquashedOperandsExamined 13857480 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu3.iq.iqSquashedNonSpecRemoved 54926 # Number of squashed non-spec instructions that were removed
-system.cpu3.iq.issued_per_cycle::samples 56263657 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::mean 0.701157 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::stdev 1.409344 # Number of insts issued each cycle
+system.cpu3.fetch.rateDist::total 56266104 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.branchRate 0.228338 # Number of branch fetches per cycle
+system.cpu3.fetch.rate 0.898983 # Number of inst fetches per cycle
+system.cpu3.decode.IdleCycles 14691998 # Number of cycles decode is idle
+system.cpu3.decode.BlockedCycles 32127735 # Number of cycles decode is blocked
+system.cpu3.decode.RunCycles 7847757 # Number of cycles decode is running
+system.cpu3.decode.UnblockCycles 886811 # Number of cycles decode is unblocking
+system.cpu3.decode.SquashCycles 711602 # Number of cycles decode is squashing
+system.cpu3.decode.BranchResolved 982939 # Number of times decode resolved a branch
+system.cpu3.decode.BranchMispred 91189 # Number of times decode detected a branch misprediction
+system.cpu3.decode.DecodedInsts 45025985 # Number of instructions handled by decode
+system.cpu3.decode.SquashedInsts 297573 # Number of squashed instructions handled by decode
+system.cpu3.rename.SquashCycles 711602 # Number of cycles rename is squashing
+system.cpu3.rename.IdleCycles 15176381 # Number of cycles rename is idle
+system.cpu3.rename.BlockCycles 3842485 # Number of cycles rename is blocking
+system.cpu3.rename.serializeStallCycles 22070368 # count of cycles rename stalled for serializing inst
+system.cpu3.rename.RunCycles 8242497 # Number of cycles rename is running
+system.cpu3.rename.UnblockCycles 6222544 # Number of cycles rename is unblocking
+system.cpu3.rename.RenamedInsts 43140081 # Number of instructions processed by rename
+system.cpu3.rename.ROBFullEvents 802 # Number of times rename has blocked due to ROB full
+system.cpu3.rename.IQFullEvents 912982 # Number of times rename has blocked due to IQ full
+system.cpu3.rename.LQFullEvents 87651 # Number of times rename has blocked due to LQ full
+system.cpu3.rename.SQFullEvents 4846837 # Number of times rename has blocked due to SQ full
+system.cpu3.rename.RenamedOperands 44765157 # Number of destination operands rename has renamed
+system.cpu3.rename.RenameLookups 198174110 # Number of register rename lookups that rename has made
+system.cpu3.rename.int_rename_lookups 48152546 # Number of integer rename lookups
+system.cpu3.rename.fp_rename_lookups 3891 # Number of floating rename lookups
+system.cpu3.rename.CommittedMaps 37263168 # Number of HB maps that are committed
+system.cpu3.rename.UndoneMaps 7501989 # Number of HB maps that are undone due to squashing
+system.cpu3.rename.serializingInsts 722657 # count of serializing insts renamed
+system.cpu3.rename.tempSerializingInsts 671168 # count of temporary serializing insts renamed
+system.cpu3.rename.skidInsts 5019030 # count of insts added to the skid buffer
+system.cpu3.memDep0.insertedLoads 7753962 # Number of loads inserted to the mem dependence unit.
+system.cpu3.memDep0.insertedStores 6001781 # Number of stores inserted to the mem dependence unit.
+system.cpu3.memDep0.conflictingLoads 1096461 # Number of conflicting loads.
+system.cpu3.memDep0.conflictingStores 1526920 # Number of conflicting stores.
+system.cpu3.iq.iqInstsAdded 41470903 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu3.iq.iqNonSpecInstsAdded 516515 # Number of non-speculative instructions added to the IQ
+system.cpu3.iq.iqInstsIssued 39452509 # Number of instructions issued
+system.cpu3.iq.iqSquashedInstsIssued 52405 # Number of squashed instructions issued
+system.cpu3.iq.iqSquashedInstsExamined 6056878 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu3.iq.iqSquashedOperandsExamined 13877375 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu3.iq.iqSquashedNonSpecRemoved 54814 # Number of squashed non-spec instructions that were removed
+system.cpu3.iq.issued_per_cycle::samples 56266104 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::mean 0.701177 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::stdev 1.409085 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::0 40631196 72.22% 72.22% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::1 5180458 9.21% 81.42% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::2 3984831 7.08% 88.51% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::3 3217649 5.72% 94.22% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::4 1270759 2.26% 96.48% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::5 778914 1.38% 97.87% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::6 843481 1.50% 99.37% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::7 242828 0.43% 99.80% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::8 113541 0.20% 100.00% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::0 40628428 72.21% 72.21% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::1 5180351 9.21% 81.41% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::2 3993172 7.10% 88.51% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::3 3216769 5.72% 94.23% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::4 1270144 2.26% 96.49% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::5 778707 1.38% 97.87% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::6 841867 1.50% 99.37% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::7 243134 0.43% 99.80% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::8 113532 0.20% 100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::total 56263657 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::total 56266104 # Number of insts issued each cycle
system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntAlu 56843 9.40% 9.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntMult 0 0.00% 9.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntDiv 0 0.00% 9.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatAdd 0 0.00% 9.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCmp 0 0.00% 9.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCvt 0 0.00% 9.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatMult 0 0.00% 9.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatDiv 0 0.00% 9.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 9.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAdd 0 0.00% 9.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 9.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAlu 0 0.00% 9.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCmp 0 0.00% 9.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCvt 0 0.00% 9.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMisc 0 0.00% 9.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMult 0 0.00% 9.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 9.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShift 0 0.00% 9.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 9.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 9.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 9.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 9.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 9.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 9.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 9.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 9.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 9.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 9.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemRead 285724 47.25% 56.65% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemWrite 262185 43.35% 100.00% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntAlu 56907 9.43% 9.43% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntMult 0 0.00% 9.43% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntDiv 0 0.00% 9.43% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatAdd 0 0.00% 9.43% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCmp 0 0.00% 9.43% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCvt 0 0.00% 9.43% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatMult 0 0.00% 9.43% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatDiv 0 0.00% 9.43% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 9.43% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAdd 0 0.00% 9.43% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 9.43% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAlu 0 0.00% 9.43% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCmp 0 0.00% 9.43% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCvt 0 0.00% 9.43% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMisc 0 0.00% 9.43% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMult 0 0.00% 9.43% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 9.43% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShift 0 0.00% 9.43% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 9.43% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 9.43% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 9.43% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 9.43% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 9.43% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 9.43% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 9.43% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 9.43% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 9.43% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.43% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 9.43% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemRead 285269 47.26% 56.69% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemWrite 261388 43.31% 100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu3.iq.FU_type_0::No_OpClass 84 0.00% 0.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntAlu 26236947 66.51% 66.51% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntMult 29772 0.08% 66.58% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 66.58% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 66.58% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 66.58% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 66.58% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 66.58% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 66.58% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 66.58% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 66.58% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 66.58% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 66.58% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 66.58% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 66.58% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 66.58% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 66.58% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 66.58% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 66.58% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.58% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 66.58% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.58% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.58% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.58% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.58% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.58% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMisc 2427 0.01% 66.59% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 66.59% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 66.59% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.59% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemRead 7477838 18.96% 85.54% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemWrite 5702609 14.46% 100.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::No_OpClass 82 0.00% 0.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntAlu 26244378 66.52% 66.52% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntMult 29732 0.08% 66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMisc 2423 0.01% 66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemRead 7478738 18.96% 85.56% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemWrite 5697150 14.44% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::total 39449683 # Type of FU issued
-system.cpu3.iq.rate 0.677852 # Inst issue rate
-system.cpu3.iq.fu_busy_cnt 604752 # FU busy when requested
-system.cpu3.iq.fu_busy_rate 0.015330 # FU busy rate (busy events/executed inst)
-system.cpu3.iq.int_inst_queue_reads 135811723 # Number of integer instruction queue reads
-system.cpu3.iq.int_inst_queue_writes 48051371 # Number of integer instruction queue writes
-system.cpu3.iq.int_inst_queue_wakeup_accesses 38283859 # Number of integer instruction queue wakeup accesses
-system.cpu3.iq.fp_inst_queue_reads 8570 # Number of floating instruction queue reads
-system.cpu3.iq.fp_inst_queue_writes 4586 # Number of floating instruction queue writes
-system.cpu3.iq.fp_inst_queue_wakeup_accesses 3750 # Number of floating instruction queue wakeup accesses
-system.cpu3.iq.int_alu_accesses 40049753 # Number of integer alu accesses
-system.cpu3.iq.fp_alu_accesses 4598 # Number of floating point alu accesses
-system.cpu3.iew.lsq.thread0.forwLoads 172364 # Number of loads that had data forwarded from stores
+system.cpu3.iq.FU_type_0::total 39452509 # Type of FU issued
+system.cpu3.iq.rate 0.677890 # Inst issue rate
+system.cpu3.iq.fu_busy_cnt 603564 # FU busy when requested
+system.cpu3.iq.fu_busy_rate 0.015298 # FU busy rate (busy events/executed inst)
+system.cpu3.iq.int_inst_queue_reads 135818664 # Number of integer instruction queue reads
+system.cpu3.iq.int_inst_queue_writes 48068982 # Number of integer instruction queue writes
+system.cpu3.iq.int_inst_queue_wakeup_accesses 38286246 # Number of integer instruction queue wakeup accesses
+system.cpu3.iq.fp_inst_queue_reads 8427 # Number of floating instruction queue reads
+system.cpu3.iq.fp_inst_queue_writes 4554 # Number of floating instruction queue writes
+system.cpu3.iq.fp_inst_queue_wakeup_accesses 3686 # Number of floating instruction queue wakeup accesses
+system.cpu3.iq.int_alu_accesses 40051464 # Number of integer alu accesses
+system.cpu3.iq.fp_alu_accesses 4527 # Number of floating point alu accesses
+system.cpu3.iew.lsq.thread0.forwLoads 171911 # Number of loads that had data forwarded from stores
system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu3.iew.lsq.thread0.squashedLoads 1182055 # Number of loads squashed
-system.cpu3.iew.lsq.thread0.ignoredResponses 1378 # Number of memory responses ignored because the instruction is squashed
-system.cpu3.iew.lsq.thread0.memOrderViolation 29890 # Number of memory ordering violations
-system.cpu3.iew.lsq.thread0.squashedStores 609761 # Number of stores squashed
+system.cpu3.iew.lsq.thread0.squashedLoads 1183804 # Number of loads squashed
+system.cpu3.iew.lsq.thread0.ignoredResponses 1366 # Number of memory responses ignored because the instruction is squashed
+system.cpu3.iew.lsq.thread0.memOrderViolation 29886 # Number of memory ordering violations
+system.cpu3.iew.lsq.thread0.squashedStores 609084 # Number of stores squashed
system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu3.iew.lsq.thread0.rescheduledLoads 109360 # Number of loads that were rescheduled
-system.cpu3.iew.lsq.thread0.cacheBlocked 44921 # Number of times an access to memory failed due to the cache being blocked
+system.cpu3.iew.lsq.thread0.rescheduledLoads 109633 # Number of loads that were rescheduled
+system.cpu3.iew.lsq.thread0.cacheBlocked 44383 # Number of times an access to memory failed due to the cache being blocked
system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu3.iew.iewSquashCycles 708923 # Number of cycles IEW is squashing
-system.cpu3.iew.iewBlockCycles 3187363 # Number of cycles IEW is blocking
-system.cpu3.iew.iewUnblockCycles 509464 # Number of cycles IEW is unblocking
-system.cpu3.iew.iewDispatchedInsts 42027375 # Number of instructions dispatched to IQ
-system.cpu3.iew.iewDispSquashedInsts 77349 # Number of squashed instructions skipped by dispatch
-system.cpu3.iew.iewDispLoadInsts 7752515 # Number of dispatched load instructions
-system.cpu3.iew.iewDispStoreInsts 6007333 # Number of dispatched store instructions
-system.cpu3.iew.iewDispNonSpecInsts 267430 # Number of dispatched non-speculative instructions
-system.cpu3.iew.iewIQFullEvents 22605 # Number of times the IQ has become full, causing a stall
-system.cpu3.iew.iewLSQFullEvents 480734 # Number of times the LSQ has become full, causing a stall
-system.cpu3.iew.memOrderViolationEvents 29890 # Number of memory order violations
-system.cpu3.iew.predictedTakenIncorrect 141333 # Number of branches that were predicted taken incorrectly
-system.cpu3.iew.predictedNotTakenIncorrect 125701 # Number of branches that were predicted not taken incorrectly
-system.cpu3.iew.branchMispredicts 267034 # Number of branch mispredicts detected at execute
-system.cpu3.iew.iewExecutedInsts 39117599 # Number of executed instructions
-system.cpu3.iew.iewExecLoadInsts 7344612 # Number of load instructions executed
-system.cpu3.iew.iewExecSquashedInsts 299061 # Number of squashed instructions skipped in execute
+system.cpu3.iew.iewSquashCycles 711602 # Number of cycles IEW is squashing
+system.cpu3.iew.iewBlockCycles 3194648 # Number of cycles IEW is blocking
+system.cpu3.iew.iewUnblockCycles 528279 # Number of cycles IEW is unblocking
+system.cpu3.iew.iewDispatchedInsts 42035264 # Number of instructions dispatched to IQ
+system.cpu3.iew.iewDispSquashedInsts 85063 # Number of squashed instructions skipped by dispatch
+system.cpu3.iew.iewDispLoadInsts 7753962 # Number of dispatched load instructions
+system.cpu3.iew.iewDispStoreInsts 6001781 # Number of dispatched store instructions
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+system.cpu3.iew.iewIQFullEvents 22471 # Number of times the IQ has become full, causing a stall
+system.cpu3.iew.iewLSQFullEvents 499621 # Number of times the LSQ has become full, causing a stall
+system.cpu3.iew.memOrderViolationEvents 29886 # Number of memory order violations
+system.cpu3.iew.predictedTakenIncorrect 141382 # Number of branches that were predicted taken incorrectly
+system.cpu3.iew.predictedNotTakenIncorrect 125809 # Number of branches that were predicted not taken incorrectly
+system.cpu3.iew.branchMispredicts 267191 # Number of branch mispredicts detected at execute
+system.cpu3.iew.iewExecutedInsts 39120156 # Number of executed instructions
+system.cpu3.iew.iewExecLoadInsts 7345638 # Number of load instructions executed
+system.cpu3.iew.iewExecSquashedInsts 299518 # Number of squashed instructions skipped in execute
system.cpu3.iew.exec_swp 0 # number of swp insts executed
-system.cpu3.iew.exec_nop 47561 # number of nop insts executed
-system.cpu3.iew.exec_refs 12987668 # number of memory reference insts executed
-system.cpu3.iew.exec_branches 7261479 # Number of branches executed
-system.cpu3.iew.exec_stores 5643056 # Number of stores executed
-system.cpu3.iew.exec_rate 0.672146 # Inst execution rate
-system.cpu3.iew.wb_sent 38828070 # cumulative count of insts sent to commit
-system.cpu3.iew.wb_count 38287609 # cumulative count of insts written-back
-system.cpu3.iew.wb_producers 20013510 # num instructions producing a value
-system.cpu3.iew.wb_consumers 34846989 # num instructions consuming a value
-system.cpu3.iew.wb_rate 0.657884 # insts written-back per cycle
-system.cpu3.iew.wb_fanout 0.574325 # average fanout of values written-back
-system.cpu3.commit.commitSquashedInsts 6062120 # The number of squashed insts skipped by commit
-system.cpu3.commit.commitNonSpecStalls 462214 # The number of times commit has been forced to stall to communicate backwards
-system.cpu3.commit.branchMispredicts 222319 # The number of times a branch was mispredicted
-system.cpu3.commit.committed_per_cycle::samples 54968801 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::mean 0.654162 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::stdev 1.550259 # Number of insts commited each cycle
+system.cpu3.iew.exec_nop 47846 # number of nop insts executed
+system.cpu3.iew.exec_refs 12983277 # number of memory reference insts executed
+system.cpu3.iew.exec_branches 7265357 # Number of branches executed
+system.cpu3.iew.exec_stores 5637639 # Number of stores executed
+system.cpu3.iew.exec_rate 0.672179 # Inst execution rate
+system.cpu3.iew.wb_sent 38830479 # cumulative count of insts sent to commit
+system.cpu3.iew.wb_count 38289932 # cumulative count of insts written-back
+system.cpu3.iew.wb_producers 20020734 # num instructions producing a value
+system.cpu3.iew.wb_consumers 34859038 # num instructions consuming a value
+system.cpu3.iew.wb_rate 0.657914 # insts written-back per cycle
+system.cpu3.iew.wb_fanout 0.574334 # average fanout of values written-back
+system.cpu3.commit.commitSquashedInsts 6072535 # The number of squashed insts skipped by commit
+system.cpu3.commit.commitNonSpecStalls 461701 # The number of times commit has been forced to stall to communicate backwards
+system.cpu3.commit.branchMispredicts 222399 # The number of times a branch was mispredicted
+system.cpu3.commit.committed_per_cycle::samples 54967240 # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::mean 0.654139 # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::stdev 1.550137 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::0 41122825 74.81% 74.81% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::1 6168562 11.22% 86.03% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::2 3091321 5.62% 91.66% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::3 1317611 2.40% 94.05% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::4 712190 1.30% 95.35% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::5 498110 0.91% 96.26% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::6 959967 1.75% 98.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::7 230353 0.42% 98.42% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::8 867862 1.58% 100.00% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::0 41117767 74.80% 74.80% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::1 6171974 11.23% 86.03% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::2 3094219 5.63% 91.66% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::3 1318133 2.40% 94.06% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::4 709863 1.29% 95.35% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::5 496595 0.90% 96.25% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::6 959944 1.75% 98.00% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::7 230664 0.42% 98.42% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::8 868081 1.58% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::total 54968801 # Number of insts commited each cycle
-system.cpu3.commit.committedInsts 29404628 # Number of instructions committed
-system.cpu3.commit.committedOps 35958516 # Number of ops (including micro ops) committed
+system.cpu3.commit.committed_per_cycle::total 54967240 # Number of insts commited each cycle
+system.cpu3.commit.committedInsts 29407542 # Number of instructions committed
+system.cpu3.commit.committedOps 35956198 # Number of ops (including micro ops) committed
system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu3.commit.refs 11968032 # Number of memory references committed
-system.cpu3.commit.loads 6570460 # Number of loads committed
-system.cpu3.commit.membars 179741 # Number of memory barriers committed
-system.cpu3.commit.branches 6849330 # Number of branches committed
-system.cpu3.commit.fp_insts 3728 # Number of committed floating point instructions.
-system.cpu3.commit.int_insts 31415410 # Number of committed integer instructions.
-system.cpu3.commit.function_calls 1242435 # Number of function calls committed.
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system.cpu3.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
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-system.cpu3.quiesceCycles 5160447116 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
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-system.cpu3.committedOps 35932900 # Number of Ops (including micro ops) Simulated
-system.cpu3.cpi 1.980941 # CPI: Cycles Per Instruction
-system.cpu3.cpi_total 1.980941 # CPI: Total CPI of All Threads
-system.cpu3.ipc 0.504811 # IPC: Instructions Per Cycle
-system.cpu3.ipc_total 0.504811 # IPC: Total IPC of All Threads
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system.iobus.trans_dist::ReadResp 30184 # Transaction distribution
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-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 121451.735016 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 119102.893565 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 123921.875000 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 122360.696517 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 117927.341288 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 122919.117647 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 123289.647699 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.data 122881.844896 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 121027.546228 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121451.735016 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 119102.893565 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 123921.875000 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 122360.696517 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 117927.341288 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 122919.117647 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 123289.647699 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.data 122881.844896 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 121027.546228 # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163716.904277 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 186066.593886 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 203635.875973 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 190212.833764 # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 165879.440258 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 185338.038109 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 201856.695497 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 189452.051804 # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 164685.250643 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 185748.845799 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 202850.309455 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 189877.258577 # average overall mshr uncacheable latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 118995.539697 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 117502.900020 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 122584.725697 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 120476.882829 # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 121284.722222 # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 122294.456167 # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 123597.422983 # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 122812.166955 # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 120494.377510 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 122366.483467 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 126553.055898 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 123860.990239 # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 121284.722222 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 119247.351731 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 123919.354839 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 122294.456167 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 117867.153240 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 124639.705882 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 123597.422983 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.data 122936.160234 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 121071.197416 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121284.722222 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 119247.351731 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 123919.354839 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 122294.456167 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 117867.153240 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 124639.705882 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 123597.422983 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.data 122936.160234 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 121071.197416 # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163771.216098 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 186001.180959 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 203635.934921 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 190213.149584 # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 165938.713156 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 185272.321429 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 201857.441098 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 189451.142317 # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 164742.070520 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 185683.350410 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 202850.671583 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 189877.033923 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 40114 # Transaction distribution
-system.membus.trans_dist::ReadResp 76472 # Transaction distribution
+system.membus.trans_dist::ReadResp 76465 # Transaction distribution
system.membus.trans_dist::WriteReq 27565 # Transaction distribution
system.membus.trans_dist::WriteResp 27565 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 131266 # Transaction distribution
-system.membus.trans_dist::CleanEvict 9256 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 4564 # Transaction distribution
+system.membus.trans_dist::WritebackDirty 131262 # Transaction distribution
+system.membus.trans_dist::CleanEvict 9255 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 4560 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 11 # Transaction distribution
system.membus.trans_dist::UpgradeResp 1783 # Transaction distribution
-system.membus.trans_dist::ReadExReq 138006 # Transaction distribution
-system.membus.trans_dist::ReadExResp 138006 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 36358 # Transaction distribution
+system.membus.trans_dist::ReadExReq 138008 # Transaction distribution
+system.membus.trans_dist::ReadExResp 138008 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 36351 # Transaction distribution
system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
system.membus.trans_dist::InvalidateResp 21008 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105436 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2006 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 486411 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 593863 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 486392 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 593844 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94027 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 94027 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 687890 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 687871 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159093 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4012 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17273980 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 17437105 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17273404 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 17436529 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2322624 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2322624 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 19759729 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 19759153 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 308 # Total snoops (count)
-system.membus.snoop_fanout::samples 423370 # Request fanout histogram
+system.membus.snoop_fanout::samples 423355 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 423370 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 423355 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 423370 # Request fanout histogram
-system.membus.reqLayer0.occupancy 54054500 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 423355 # Request fanout histogram
+system.membus.reqLayer0.occupancy 54051500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 683000 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 682000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 487802765 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 487313006 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 583127250 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 582602000 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 785081 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests 5675245 # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests 2851889 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests 45299 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_requests 5677345 # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests 2853013 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests 45306 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 358 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 358 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq 112467 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 2639200 # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq 112463 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 2640157 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 27565 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 27565 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty 761596 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean 1988229 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 147548 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 2816 # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty 761584 # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean 1989175 # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict 147491 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 2813 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 29 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 2845 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 296735 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 296735 # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq 1988790 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 538004 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 2842 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 296749 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 296749 # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq 1989735 # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq 538020 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 15216 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5983726 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2626321 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 26876 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 102356 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 8739279 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 254557176 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97876281 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 44416 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 183100 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 352660973 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 192738 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 4203717 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 0.021388 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.144675 # Request fanout histogram
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5986563 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2626405 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 26917 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 102214 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 8742099 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 254678264 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97882489 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 44408 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 182720 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 352787881 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 192824 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 4204353 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 0.021421 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.144784 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 4113806 97.86% 97.86% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 89911 2.14% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 4114290 97.86% 97.86% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 90063 2.14% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 4203717 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 3488536999 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 4204353 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 3491124499 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 176919 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 1898856602 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 1900767119 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 770188700 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 770214712 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 11632976 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy 11666477 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 48177210 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy 48138206 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu3.kern.inst.arm 0 # number of arm instructions executed
system.cpu3.kern.inst.quiesce 0 # number of quiesce instructions executed
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm
+boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
+dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
+exit_on_work_items=false
flags_addr=469827632
gic_cpu_addr=738205696
have_large_asid_64=false
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
+readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/work/gem5/dist/disks/linux-aarch32-ael.img
+image_file=/home/stever/m5/aarch-system-2014-10/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=false
hit_latency=50
is_read_only=false
max_miss_count=0
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.toL2Bus.snoop_filter
snoop_response_latency=1
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: CP14 unimplemented crn[5], opc1[4], crm[12], opc2[4]
-warn: CP14 unimplemented crn[1], opc1[4], crm[12], opc2[0]
warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4]
warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
warn: CP14 unimplemented crn[6], opc1[5], crm[0], opc2[3]
warn: CP14 unimplemented crn[6], opc1[5], crm[4], opc2[3]
warn: CP14 unimplemented crn[15], opc1[0], crm[8], opc2[0]
+warn: CP14 unimplemented crn[5], opc1[4], crm[12], opc2[0]
warn: CP14 unimplemented crn[2], opc1[2], crm[0], opc2[2]
warn: CP14 unimplemented crn[12], opc1[0], crm[12], opc2[0]
warn: CP14 unimplemented crn[12], opc1[0], crm[12], opc2[1]
warn: CP14 unimplemented crn[12], opc1[0], crm[0], opc2[3]
+warn: instruction 'mcr dcisw' unimplemented
warn: instruction 'mcr bpiall' unimplemented
warn: CP14 unimplemented crn[2], opc1[2], crm[4], opc2[1]
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
+Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3/simout
+Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 4 2015 11:13:17
-gem5 started Dec 4 2015 12:17:01
-gem5 executing on e104799-lin, pid 3291
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3
+gem5 compiled Mar 15 2016 21:26:42
+gem5 started Mar 15 2016 21:34:31
+gem5 executing on phenom, pid 15967
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3
Global frequency set at 1000000000000 ticks per second
---------- Begin Simulation Statistics ----------
-sim_seconds 2.823470 # Number of seconds simulated
-sim_ticks 2823469739500 # Number of ticks simulated
-final_tick 2823469739500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.823493 # Number of seconds simulated
+sim_ticks 2823493079000 # Number of ticks simulated
+final_tick 2823493079000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 118468 # Simulator instruction rate (inst/s)
-host_op_rate 143788 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2861405792 # Simulator tick rate (ticks/s)
-host_mem_usage 590036 # Number of bytes of host memory used
-host_seconds 986.74 # Real time elapsed on the host
-sim_insts 116897717 # Number of instructions simulated
-sim_ops 141881589 # Number of ops (including micro ops) simulated
+host_inst_rate 90172 # Simulator instruction rate (inst/s)
+host_op_rate 109444 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2177949659 # Simulator tick rate (ticks/s)
+host_mem_usage 568424 # Number of bytes of host memory used
+host_seconds 1296.40 # Real time elapsed on the host
+sim_insts 116899487 # Number of instructions simulated
+sim_ops 141883778 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker 3648 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 661824 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 5279456 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 5184 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 711040 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 4517256 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 661248 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 5289056 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 5312 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 712448 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 4516488 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 11179432 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 661824 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 711040 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1372864 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 8427776 # Number of bytes written to this memory
+system.physmem.bytes_read::total 11189224 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 661248 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 712448 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1373696 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 8440896 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory
-system.physmem.bytes_written::total 8445300 # Number of bytes written to this memory
+system.physmem.bytes_written::total 8458420 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 57 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 10341 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 83010 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 81 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 11110 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 70584 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 10332 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 83160 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 83 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 11132 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 70572 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 175199 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 131684 # Number of write requests responded to by this memory
+system.physmem.num_reads::total 175352 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 131889 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 136065 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 136270 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 1292 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 234401 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 1869847 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 1836 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 251832 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 1599895 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 234195 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 1873231 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 1881 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 252329 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 1599610 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 3959466 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 234401 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 251832 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 486233 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 2984900 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 3962901 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 234195 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 252329 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 486524 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 2989522 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 6204 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2991107 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 2984900 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total 2995729 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 2989522 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 1292 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 234401 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 1876051 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 1836 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 251832 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 1599898 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 234195 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 1879435 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 1881 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 252329 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 1599613 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 6950573 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 175200 # Number of read requests accepted
-system.physmem.writeReqs 136065 # Number of write requests accepted
-system.physmem.readBursts 175200 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 136065 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 11204096 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 8704 # Total number of bytes read from write queue
-system.physmem.bytesWritten 8457920 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 11179496 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 8445300 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 136 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::total 6958630 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 175353 # Number of read requests accepted
+system.physmem.writeReqs 136270 # Number of write requests accepted
+system.physmem.readBursts 175353 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 136270 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 11214528 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 8064 # Total number of bytes read from write queue
+system.physmem.bytesWritten 8470656 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 11189288 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 8458420 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 126 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 11402 # Per bank write bursts
-system.physmem.perBankRdBursts::1 10980 # Per bank write bursts
-system.physmem.perBankRdBursts::2 11431 # Per bank write bursts
-system.physmem.perBankRdBursts::3 11297 # Per bank write bursts
+system.physmem.perBankRdBursts::0 11394 # Per bank write bursts
+system.physmem.perBankRdBursts::1 10988 # Per bank write bursts
+system.physmem.perBankRdBursts::2 11451 # Per bank write bursts
+system.physmem.perBankRdBursts::3 11269 # Per bank write bursts
system.physmem.perBankRdBursts::4 11015 # Per bank write bursts
-system.physmem.perBankRdBursts::5 10541 # Per bank write bursts
-system.physmem.perBankRdBursts::6 11443 # Per bank write bursts
-system.physmem.perBankRdBursts::7 11405 # Per bank write bursts
-system.physmem.perBankRdBursts::8 11226 # Per bank write bursts
-system.physmem.perBankRdBursts::9 11073 # Per bank write bursts
-system.physmem.perBankRdBursts::10 10487 # Per bank write bursts
-system.physmem.perBankRdBursts::11 10069 # Per bank write bursts
-system.physmem.perBankRdBursts::12 10629 # Per bank write bursts
-system.physmem.perBankRdBursts::13 11393 # Per bank write bursts
-system.physmem.perBankRdBursts::14 10671 # Per bank write bursts
-system.physmem.perBankRdBursts::15 10002 # Per bank write bursts
-system.physmem.perBankWrBursts::0 8635 # Per bank write bursts
-system.physmem.perBankWrBursts::1 8267 # Per bank write bursts
-system.physmem.perBankWrBursts::2 8885 # Per bank write bursts
-system.physmem.perBankWrBursts::3 8812 # Per bank write bursts
-system.physmem.perBankWrBursts::4 7853 # Per bank write bursts
-system.physmem.perBankWrBursts::5 7875 # Per bank write bursts
-system.physmem.perBankWrBursts::6 8475 # Per bank write bursts
-system.physmem.perBankWrBursts::7 8544 # Per bank write bursts
-system.physmem.perBankWrBursts::8 8488 # Per bank write bursts
-system.physmem.perBankWrBursts::9 8484 # Per bank write bursts
-system.physmem.perBankWrBursts::10 7865 # Per bank write bursts
-system.physmem.perBankWrBursts::11 7711 # Per bank write bursts
-system.physmem.perBankWrBursts::12 8199 # Per bank write bursts
-system.physmem.perBankWrBursts::13 8763 # Per bank write bursts
-system.physmem.perBankWrBursts::14 7974 # Per bank write bursts
+system.physmem.perBankRdBursts::5 10539 # Per bank write bursts
+system.physmem.perBankRdBursts::6 11408 # Per bank write bursts
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+system.physmem.perBankRdBursts::8 11237 # Per bank write bursts
+system.physmem.perBankRdBursts::9 11286 # Per bank write bursts
+system.physmem.perBankRdBursts::10 10494 # Per bank write bursts
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+system.physmem.perBankRdBursts::12 10670 # Per bank write bursts
+system.physmem.perBankRdBursts::13 11521 # Per bank write bursts
+system.physmem.perBankRdBursts::14 10545 # Per bank write bursts
+system.physmem.perBankRdBursts::15 10001 # Per bank write bursts
+system.physmem.perBankWrBursts::0 8622 # Per bank write bursts
+system.physmem.perBankWrBursts::1 8285 # Per bank write bursts
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+system.physmem.perBankWrBursts::5 7876 # Per bank write bursts
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+system.physmem.perBankWrBursts::7 8530 # Per bank write bursts
+system.physmem.perBankWrBursts::8 8484 # Per bank write bursts
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+system.physmem.perBankWrBursts::11 7713 # Per bank write bursts
+system.physmem.perBankWrBursts::12 8237 # Per bank write bursts
+system.physmem.perBankWrBursts::13 8870 # Per bank write bursts
+system.physmem.perBankWrBursts::14 7879 # Per bank write bursts
system.physmem.perBankWrBursts::15 7325 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 9 # Number of times write queue was full causing retry
-system.physmem.totGap 2823469561500 # Total gap between requests
+system.physmem.numWrRetry 11 # Number of times write queue was full causing retry
+system.physmem.totGap 2823492901000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 542 # Read request sizes (log2)
system.physmem.readPktSize::3 14 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 174644 # Read request sizes (log2)
+system.physmem.readPktSize::6 174797 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 4381 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 131684 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 107528 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 59207 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 6570 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 1738 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 131889 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 107608 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 59040 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 6836 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 1721 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 109 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 113 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 99 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 96 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 95 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 96 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 95 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 93 # What write queue length does an incoming req see
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-system.physmem.bytesPerActivate::stdev 322.976570 # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::256-383 6763 10.31% 72.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 3694 5.63% 78.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2894 4.41% 82.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1678 2.56% 85.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1076 1.64% 86.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1118 1.70% 88.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 7501 11.43% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 65621 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 6504 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 26.912515 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 489.223467 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047 6502 99.97% 99.97% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::36864-38911 1 0.02% 100.00% # Reads before turning the bus around for writes
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-system.physmem.wrPerTurnAround::36-39 21 0.32% 92.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 44 0.68% 93.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 8 0.12% 93.70% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::52-55 14 0.22% 96.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 10 0.15% 96.33% # Writes before turning the bus around for reads
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-system.physmem.totQLat 2746267751 # Total ticks spent queuing
-system.physmem.totMemAccLat 6028717751 # Total ticks spent from burst creation until serviced by the DRAM
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-system.physmem.avgQLat 15687.22 # Average queueing delay per DRAM burst
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+system.physmem.wrPerTurnAround::total 6540 # Writes before turning the bus around for reads
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+system.physmem.totBusLat 876135000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 15691.87 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 34437.22 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 34441.87 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 3.97 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 3.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 3.96 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 2.99 # Average system write bandwidth in MiByte/s
+system.physmem.avgWrBWSys 3.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.05 # Data bus utilization in percentage
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.46 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 12.82 # Average write queue length when enqueuing
-system.physmem.readRowHits 144099 # Number of row buffer hits during reads
-system.physmem.writeRowHits 97497 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 82.31 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 73.76 # Row buffer hit rate for writes
-system.physmem.avgGap 9070951.00 # Average gap between requests
-system.physmem.pageHitRate 78.63 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 256253760 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 139821000 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 698209200 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 436402080 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 184415044320 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 80123978880 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 1623795284250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 1889864993490 # Total energy per rank (pJ)
-system.physmem_0.averagePower 669.342266 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 2701214527000 # Time in different power states
-system.physmem_0.memoryStateTime::REF 94281720000 # Time in different power states
+system.physmem.avgWrQLen 13.00 # Average write queue length when enqueuing
+system.physmem.readRowHits 144282 # Number of row buffer hits during reads
+system.physmem.writeRowHits 97631 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 82.34 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 73.75 # Row buffer hit rate for writes
+system.physmem.avgGap 9060604.96 # Average gap between requests
+system.physmem.pageHitRate 78.64 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 255898440 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 139627125 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 697320000 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 436058640 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 184416570000 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 80131577265 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 1623802634250 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 1889879685720 # Total energy per rank (pJ)
+system.physmem_0.averagePower 669.341932 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 2701224800750 # Time in different power states
+system.physmem_0.memoryStateTime::REF 94282500000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 27969560500 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 27981865500 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 239841000 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 130865625 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 667274400 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 419962320 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 184415044320 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 79167823830 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 1624634016750 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 1889674828245 # Total energy per rank (pJ)
-system.physmem_1.averagePower 669.274915 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 2702617863750 # Time in different power states
-system.physmem_1.memoryStateTime::REF 94281720000 # Time in different power states
+system.physmem_1.actEnergy 240544080 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 131249250 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 669442800 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 421595280 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 184416570000 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 79215076260 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 1624606582500 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 1889701060170 # Total energy per rank (pJ)
+system.physmem_1.averagePower 669.278668 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 2702572917000 # Time in different power states
+system.physmem_1.memoryStateTime::REF 94282500000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 26569403250 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 26637651500 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 704 # Number of bytes read from this memory
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
-system.cpu0.branchPred.lookups 26557765 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 13711788 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 500128 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 15985074 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 12420856 # Number of BTB hits
+system.cpu0.branchPred.lookups 26562225 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 13713319 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 500857 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 15697125 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 12422609 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 77.702837 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 6637719 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 27705 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 79.139390 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 6635585 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 27692 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.walks 56410 # Table walker walks requested
-system.cpu0.dtb.walker.walksShort 56410 # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 17224 # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 13674 # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore 25512 # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples 30898 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean 845.750534 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev 5234.094520 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-16383 30449 98.55% 98.55% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::16384-32767 313 1.01% 99.56% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::32768-49151 71 0.23% 99.79% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::49152-65535 28 0.09% 99.88% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::65536-81919 18 0.06% 99.94% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walks 56581 # Table walker walks requested
+system.cpu0.dtb.walker.walksShort 56581 # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 17171 # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 13789 # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore 25621 # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples 30960 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean 892.441860 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev 5515.724394 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-16383 30478 98.44% 98.44% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::16384-32767 319 1.03% 99.47% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::32768-49151 90 0.29% 99.76% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::49152-65535 32 0.10% 99.87% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::65536-81919 19 0.06% 99.93% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::81920-98303 5 0.02% 99.95% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::98304-114687 5 0.02% 99.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::114688-131071 5 0.02% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::98304-114687 6 0.02% 99.96% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::114688-131071 6 0.02% 99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::131072-147455 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::147456-163839 4 0.01% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 30898 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples 12695 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 13609.491926 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 11056.421088 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 9278.462681 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-16383 9267 73.00% 73.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::16384-32767 3157 24.87% 97.87% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::32768-49151 251 1.98% 99.84% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::49152-65535 4 0.03% 99.87% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-147455 12 0.09% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkWaitTime::total 30960 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples 12756 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 13625.744748 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 11059.152446 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 9336.432793 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-16383 9266 72.64% 72.64% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::16384-32767 3226 25.29% 97.93% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::32768-49151 240 1.88% 99.81% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::49152-65535 4 0.03% 99.84% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-81919 2 0.02% 99.86% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::81920-98303 1 0.01% 99.87% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-147455 13 0.10% 99.97% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::147456-163839 3 0.02% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total 12695 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples 96164849040 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean 0.577862 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::stdev 0.515354 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0-1 96082852540 99.91% 99.91% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::2-3 55229500 0.06% 99.97% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::4-5 12746000 0.01% 99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::6-7 5020500 0.01% 99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::8-9 2459000 0.00% 99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::10-11 1673000 0.00% 99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::12-13 1038500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::14-15 2619500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::16-17 401000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::18-19 384500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::20-21 78000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::22-23 35000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::24-25 82500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::26-27 33000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::28-29 25000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::30-31 171500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 96164849040 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 3408 68.65% 68.65% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M 1556 31.35% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 4964 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 56410 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total 12756 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples 91893354244 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean 0.629728 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev 0.506061 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0-1 91810040244 99.91% 99.91% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::2-3 56305000 0.06% 99.97% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::4-5 12880500 0.01% 99.98% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::6-7 5151500 0.01% 99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::8-9 2494500 0.00% 99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::10-11 1674000 0.00% 99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::12-13 953500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::14-15 2585000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::16-17 396500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::18-19 403500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::20-21 80000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::22-23 39000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::24-25 135500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::26-27 32000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::28-29 29000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::30-31 154500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 91893354244 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K 3474 69.45% 69.45% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M 1528 30.55% 100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total 5002 # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 56581 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 56410 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4964 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 56581 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5002 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4964 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 61374 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5002 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total 61583 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 13949693 # DTB read hits
-system.cpu0.dtb.read_misses 47052 # DTB read misses
-system.cpu0.dtb.write_hits 10497167 # DTB write hits
-system.cpu0.dtb.write_misses 9358 # DTB write misses
-system.cpu0.dtb.flush_tlb 179 # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva 469 # Number of times TLB was flushed by MVA
+system.cpu0.dtb.read_hits 13951355 # DTB read hits
+system.cpu0.dtb.read_misses 47293 # DTB read misses
+system.cpu0.dtb.write_hits 10502243 # DTB write hits
+system.cpu0.dtb.write_misses 9288 # DTB write misses
+system.cpu0.dtb.flush_tlb 177 # Number of times complete TLB was flushed
+system.cpu0.dtb.flush_tlb_mva 479 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 3271 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 792 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.flush_entries 3270 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 756 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 1257 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 589 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 13996745 # DTB read accesses
-system.cpu0.dtb.write_accesses 10506525 # DTB write accesses
+system.cpu0.dtb.perms_faults 577 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 13998648 # DTB read accesses
+system.cpu0.dtb.write_accesses 10511531 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 24446860 # DTB hits
-system.cpu0.dtb.misses 56410 # DTB misses
-system.cpu0.dtb.accesses 24503270 # DTB accesses
+system.cpu0.dtb.hits 24453598 # DTB hits
+system.cpu0.dtb.misses 56581 # DTB misses
+system.cpu0.dtb.accesses 24510179 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.walker.walks 7368 # Table walker walks requested
-system.cpu0.itb.walker.walksShort 7368 # Table walker walks initiated with short descriptors
-system.cpu0.itb.walker.walksShortTerminationLevel::Level1 2261 # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksShortTerminationLevel::Level2 4959 # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksSquashedBefore 148 # Table walks squashed before starting
-system.cpu0.itb.walker.walkWaitTime::samples 7220 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::mean 1816.274238 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::stdev 7833.781399 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0-16383 6926 95.93% 95.93% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::16384-32767 219 3.03% 98.96% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::32768-49151 37 0.51% 99.47% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::49152-65535 15 0.21% 99.68% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::65536-81919 11 0.15% 99.83% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walks 8148 # Table walker walks requested
+system.cpu0.itb.walker.walksShort 8148 # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.walksShortTerminationLevel::Level1 2287 # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksShortTerminationLevel::Level2 5071 # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksSquashedBefore 790 # Table walks squashed before starting
+system.cpu0.itb.walker.walkWaitTime::samples 7358 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::mean 1843.571623 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::stdev 7891.595546 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0-16383 7065 96.02% 96.02% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::16384-32767 220 2.99% 99.01% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::32768-49151 36 0.49% 99.50% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::49152-65535 18 0.24% 99.74% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::65536-81919 7 0.10% 99.84% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::81920-98303 3 0.04% 99.88% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::98304-114687 3 0.04% 99.92% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::114688-131071 3 0.04% 99.96% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::131072-147455 2 0.03% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::147456-163839 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total 7220 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples 2362 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 14046.570703 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 11793.338706 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 8758.063441 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-16383 1730 73.24% 73.24% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::16384-32767 589 24.94% 98.18% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-49151 40 1.69% 99.87% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::49152-65535 1 0.04% 99.92% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.04% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::163840-180223 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total 2362 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples 14560346416 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean 0.888625 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::stdev 0.316568 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0 1627388500 11.18% 11.18% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1 12929178416 88.80% 99.97% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::2 2653000 0.02% 99.99% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::3 688000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::4 200500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::5 118000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::6 93000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::7 27000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 14560346416 # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K 1654 74.71% 74.71% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::1M 560 25.29% 100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total 2214 # Table walker page sizes translated
+system.cpu0.itb.walker.walkWaitTime::98304-114687 4 0.05% 99.93% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::114688-131071 1 0.01% 99.95% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::131072-147455 2 0.03% 99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::147456-163839 2 0.03% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total 7358 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples 3026 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 13026.107072 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 10729.463375 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 8131.043208 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-16383 2342 77.40% 77.40% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::16384-32767 631 20.85% 98.25% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-49151 50 1.65% 99.90% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::49152-65535 1 0.03% 99.93% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-81919 1 0.03% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.03% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total 3026 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples 23173609508 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean 0.733481 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::stdev 0.443211 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0 6183538408 26.68% 26.68% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1 16984817600 73.29% 99.98% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::2 4062000 0.02% 99.99% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::3 741500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::4 212000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::5 115000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::6 49000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::7 74000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total 23173609508 # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K 1678 75.04% 75.04% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::1M 558 24.96% 100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total 2236 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 7368 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total 7368 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 8148 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total 8148 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2214 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2214 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total 9582 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 20130827 # ITB inst hits
-system.cpu0.itb.inst_misses 7368 # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2236 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2236 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total 10384 # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits 20133708 # ITB inst hits
+system.cpu0.itb.inst_misses 8148 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
-system.cpu0.itb.flush_tlb 179 # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva 469 # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb 177 # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb_mva 479 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 2134 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries 2160 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 1230 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 1247 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 20138195 # ITB inst accesses
-system.cpu0.itb.hits 20130827 # DTB hits
-system.cpu0.itb.misses 7368 # DTB misses
-system.cpu0.itb.accesses 20138195 # DTB accesses
-system.cpu0.numCycles 111738620 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 20141856 # ITB inst accesses
+system.cpu0.itb.hits 20133708 # DTB hits
+system.cpu0.itb.misses 8148 # DTB misses
+system.cpu0.itb.accesses 20141856 # DTB accesses
+system.cpu0.numCycles 111776852 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles 39370893 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 103893622 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 26557765 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 19058575 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 67178812 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 3103708 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles 121878 # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles 4445 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingDrainCycles 455 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu0.fetch.PendingTrapStallCycles 181503 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 118118 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 630 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 20129808 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 348342 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes 3505 # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples 108528550 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 1.150700 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.270125 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles 39403190 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 103921497 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 26562225 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 19058194 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 67156695 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 3114917 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles 123726 # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles 4268 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingDrainCycles 480 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu0.fetch.PendingTrapStallCycles 186283 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 122357 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 649 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 20132007 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 351323 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes 4252 # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples 108555069 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 1.151171 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.270996 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 79971422 73.69% 73.69% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 3809838 3.51% 77.20% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 2395726 2.21% 79.40% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 8000248 7.37% 86.78% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 1536985 1.42% 88.19% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 1087405 1.00% 89.19% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 6042952 5.57% 94.76% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 1032695 0.95% 95.71% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 4651279 4.29% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 79990801 73.69% 73.69% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 3808874 3.51% 77.20% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 2395058 2.21% 79.40% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 7998029 7.37% 86.77% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 1538152 1.42% 88.19% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 1084902 1.00% 89.19% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 6043071 5.57% 94.75% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 1032645 0.95% 95.70% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 4663537 4.30% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 108528550 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.237678 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.929792 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 26850691 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 63349616 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 15400515 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 1518743 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 1408634 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 1870918 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 145274 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 86265723 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 468688 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 1408634 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 27702966 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 6709898 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 45858480 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 16063551 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 10784636 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 82553580 # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents 2255 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 1112646 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents 250108 # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents 8658376 # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands 84742438 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 381431947 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 92563624 # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups 5398 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 72236094 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 12506336 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 1563816 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 1466607 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 8828288 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 14723258 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 11669783 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 2112846 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 2835315 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 79509095 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 1118195 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 76512604 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 87402 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 10382395 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 23148584 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 102807 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 108528550 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.705000 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.405850 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 108555069 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.237636 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 0.929723 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 26882807 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 63335776 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 15412280 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 1509994 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 1413858 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 1870073 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 145529 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 86268020 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 470270 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 1413858 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 27733992 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 6692590 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 45841615 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 16067408 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 10805241 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 82544618 # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents 2042 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 1112195 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents 256310 # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents 8681649 # Number of times rename has blocked due to SQ full
+system.cpu0.rename.RenamedOperands 84728075 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 381395863 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 92554269 # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups 5536 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 72228631 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 12499436 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 1563164 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 1465809 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 8810200 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 14722968 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 11667187 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 2112375 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 2825425 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 79486771 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 1117550 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 76500149 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 87453 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 10367122 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 23085587 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 102592 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples 108555069 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 0.704713 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 1.405532 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 77845712 71.73% 71.73% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 10446148 9.63% 81.35% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 7706696 7.10% 88.45% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 6443833 5.94% 94.39% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 2340710 2.16% 96.55% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 1522105 1.40% 97.95% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 1475778 1.36% 99.31% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7 487012 0.45% 99.76% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8 260556 0.24% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 77869372 71.73% 71.73% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 10452853 9.63% 81.36% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 7709491 7.10% 88.46% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 6441479 5.93% 94.40% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 2337672 2.15% 96.55% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 1520744 1.40% 97.95% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 1474811 1.36% 99.31% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7 488573 0.45% 99.76% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8 260074 0.24% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 108528550 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 108555069 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 112196 9.79% 9.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 1 0.00% 9.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 9.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 9.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 9.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 9.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 9.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 9.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 9.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 9.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 9.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 9.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 9.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 9.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 9.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 9.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 9.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 9.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 9.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 9.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 9.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 9.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 9.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 9.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 9.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 9.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 9.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 9.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 526196 45.92% 55.72% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 507404 44.28% 100.00% # attempts to use FU when none available
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+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 9.78% # attempts to use FU when none available
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+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 9.78% # attempts to use FU when none available
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+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 9.78% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 9.78% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 9.78% # attempts to use FU when none available
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+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 9.78% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 9.78% # attempts to use FU when none available
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+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 9.78% # attempts to use FU when none available
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+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 9.78% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 527304 45.92% 55.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 508852 44.31% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass 229 0.00% 0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 50972770 66.62% 66.62% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 56817 0.07% 66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 4037 0.01% 66.70% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.70% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 66.70% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.70% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 14339886 18.74% 85.44% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 11138856 14.56% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass 223 0.00% 0.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 50954579 66.61% 66.61% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 56909 0.07% 66.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 3 0.00% 66.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 4066 0.01% 66.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 66.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 14340871 18.75% 85.43% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 11143495 14.57% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 76512604 # Type of FU issued
-system.cpu0.iq.rate 0.684746 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 1145797 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.014975 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 262775124 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 91056518 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 74263785 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 11833 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 6292 # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses 5221 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 77651808 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 6364 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 356016 # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total 76500149 # Type of FU issued
+system.cpu0.iq.rate 0.684401 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 1148434 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.015012 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 262779006 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 91017673 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 74252791 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads 12248 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 6548 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses 5441 # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses 77641803 # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses 6557 # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads 356027 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 1994121 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 2352 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 54275 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 1081195 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 1992322 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 2344 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 53958 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 1074198 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 202898 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 121276 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads 201819 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 121524 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 1408634 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 5278024 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 1213431 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 80756832 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts 118260 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 14723258 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 11669783 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 571666 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 45870 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 1155376 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 54275 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 221116 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 201841 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 422957 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 75956383 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 14119834 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 499950 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles 1413858 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 5274994 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 1203442 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 80734208 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts 135083 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts 14722968 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 11667187 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 571297 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents 46146 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents 1145124 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents 53958 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 220662 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 202640 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 423302 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 75944815 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 14120955 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 498889 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 129542 # number of nop insts executed
-system.cpu0.iew.exec_refs 25156609 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 14059078 # Number of branches executed
-system.cpu0.iew.exec_stores 11036775 # Number of stores executed
-system.cpu0.iew.exec_rate 0.679768 # Inst execution rate
-system.cpu0.iew.wb_sent 75400529 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 74269006 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 38924107 # num instructions producing a value
-system.cpu0.iew.wb_consumers 68260827 # num instructions consuming a value
-system.cpu0.iew.wb_rate 0.664667 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.570226 # average fanout of values written-back
-system.cpu0.commit.commitSquashedInsts 10419079 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 1015388 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 356870 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 106130883 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 0.662591 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 1.560067 # Number of insts commited each cycle
+system.cpu0.iew.exec_nop 129887 # number of nop insts executed
+system.cpu0.iew.exec_refs 25162401 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 14058004 # Number of branches executed
+system.cpu0.iew.exec_stores 11041446 # Number of stores executed
+system.cpu0.iew.exec_rate 0.679432 # Inst execution rate
+system.cpu0.iew.wb_sent 75389517 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 74258232 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 38914565 # num instructions producing a value
+system.cpu0.iew.wb_consumers 68266536 # num instructions consuming a value
+system.cpu0.iew.wb_rate 0.664344 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.570039 # average fanout of values written-back
+system.cpu0.commit.commitSquashedInsts 10404302 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls 1014958 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts 357219 # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples 106153750 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 0.662378 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 1.559927 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 78790716 74.24% 74.24% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 12390417 11.67% 85.91% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 6092521 5.74% 91.65% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 2656832 2.50% 94.16% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 1363229 1.28% 95.44% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 834290 0.79% 96.23% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 1725699 1.63% 97.85% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 420589 0.40% 98.25% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 1856590 1.75% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 78810789 74.24% 74.24% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 12397271 11.68% 85.92% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 6093008 5.74% 91.66% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 2657069 2.50% 94.16% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 1361434 1.28% 95.45% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 829942 0.78% 96.23% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 1724502 1.62% 97.85% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 420914 0.40% 98.25% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 1858821 1.75% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 106130883 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 57976816 # Number of instructions committed
-system.cpu0.commit.committedOps 70321358 # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total 106153750 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 57962859 # Number of instructions committed
+system.cpu0.commit.committedOps 70313918 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 23317725 # Number of memory references committed
-system.cpu0.commit.loads 12729137 # Number of loads committed
-system.cpu0.commit.membars 416530 # Number of memory barriers committed
-system.cpu0.commit.branches 13368661 # Number of branches committed
-system.cpu0.commit.fp_insts 5158 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 61739692 # Number of committed integer instructions.
-system.cpu0.commit.function_calls 2627704 # Number of function calls committed.
+system.cpu0.commit.refs 23323635 # Number of memory references committed
+system.cpu0.commit.loads 12730646 # Number of loads committed
+system.cpu0.commit.membars 416255 # Number of memory barriers committed
+system.cpu0.commit.branches 13367689 # Number of branches committed
+system.cpu0.commit.fp_insts 5418 # Number of committed floating point instructions.
+system.cpu0.commit.int_insts 61732949 # Number of committed integer instructions.
+system.cpu0.commit.function_calls 2627340 # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu 46944316 66.76% 66.76% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult 55281 0.08% 66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc 4036 0.01% 66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead 12729137 18.10% 84.94% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite 10588588 15.06% 100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu 46930865 66.74% 66.74% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult 55353 0.08% 66.82% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.82% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.82% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.82% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.82% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.82% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.82% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.82% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.82% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.82% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.82% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.82% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.82% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.82% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.82% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.82% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.82% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.82% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.82% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.82% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.82% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.82% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.82% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.82% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc 4065 0.01% 66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead 12730646 18.11% 84.93% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite 10592989 15.07% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total 70321358 # Class of committed instruction
-system.cpu0.commit.bw_lim_events 1856590 # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads 172663195 # The number of ROB reads
-system.cpu0.rob.rob_writes 163882503 # The number of ROB writes
-system.cpu0.timesIdled 381139 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles 3210070 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles 2095442854 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts 57900349 # Number of Instructions Simulated
-system.cpu0.committedOps 70244891 # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi 1.929844 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 1.929844 # CPI: Total CPI of All Threads
-system.cpu0.ipc 0.518177 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 0.518177 # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads 82925717 # number of integer regfile reads
-system.cpu0.int_regfile_writes 47305162 # number of integer regfile writes
-system.cpu0.fp_regfile_reads 16275 # number of floating regfile reads
-system.cpu0.fp_regfile_writes 13170 # number of floating regfile writes
-system.cpu0.cc_regfile_reads 268288985 # number of cc regfile reads
-system.cpu0.cc_regfile_writes 27711504 # number of cc regfile writes
-system.cpu0.misc_regfile_reads 149937912 # number of misc regfile reads
-system.cpu0.misc_regfile_writes 778798 # number of misc regfile writes
-system.cpu0.dcache.tags.replacements 855446 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 511.968774 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 42352962 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 855958 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 49.480187 # Average number of references to valid blocks.
+system.cpu0.commit.op_class_0::total 70313918 # Class of committed instruction
+system.cpu0.commit.bw_lim_events 1858821 # number cycles where commit BW limit reached
+system.cpu0.rob.rob_reads 172659175 # The number of ROB reads
+system.cpu0.rob.rob_writes 163836244 # The number of ROB writes
+system.cpu0.timesIdled 382209 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles 3221783 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles 2095451919 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts 57886136 # Number of Instructions Simulated
+system.cpu0.committedOps 70237195 # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi 1.930978 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 1.930978 # CPI: Total CPI of All Threads
+system.cpu0.ipc 0.517872 # IPC: Instructions Per Cycle
+system.cpu0.ipc_total 0.517872 # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads 82912613 # number of integer regfile reads
+system.cpu0.int_regfile_writes 47294039 # number of integer regfile writes
+system.cpu0.fp_regfile_reads 16301 # number of floating regfile reads
+system.cpu0.fp_regfile_writes 13368 # number of floating regfile writes
+system.cpu0.cc_regfile_reads 268256269 # number of cc regfile reads
+system.cpu0.cc_regfile_writes 27711258 # number of cc regfile writes
+system.cpu0.misc_regfile_reads 150058010 # number of misc regfile reads
+system.cpu0.misc_regfile_writes 778660 # number of misc regfile writes
+system.cpu0.dcache.tags.replacements 855157 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 511.968827 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 42356538 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 855669 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 49.501078 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 186702500 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 248.778719 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data 263.190055 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.485896 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data 0.514043 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 253.928302 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data 258.040525 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data 0.495954 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data 0.503985 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.999939 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 301 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 189257101 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 189257101 # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data 12292677 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data 12889220 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 25181897 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 7937758 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data 7960928 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 15898686 # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data 184092 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data 180023 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total 364115 # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 230395 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 215508 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 445903 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 236843 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data 222450 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 459293 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 20230435 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data 20850148 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 41080583 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 20414527 # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data 21030171 # number of overall hits
-system.cpu0.dcache.overall_hits::total 41444698 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 435537 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data 405293 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 840830 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 1875767 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data 1821477 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 3697244 # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data 117122 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data 67245 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total 184367 # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13669 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 14208 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 27877 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data 34 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu1.data 32 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 66 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 2311304 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data 2226770 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 4538074 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 2428426 # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data 2294015 # number of overall misses
-system.cpu0.dcache.overall_misses::total 4722441 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 7243575000 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 7414080000 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 14657655000 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 137609322451 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 115018271250 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 252627593701 # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 217997500 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 196866000 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total 414863500 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 871500 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 1111000 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total 1982500 # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 144852897451 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data 122432351250 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 267285248701 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 144852897451 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data 122432351250 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 267285248701 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 12728214 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data 13294513 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 26022727 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 9813525 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data 9782405 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 19595930 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 301214 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 247268 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total 548482 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 244064 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 229716 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 473780 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 236877 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 222482 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 459359 # number of StoreCondReq accesses(hits+misses)
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-system.cpu0.dcache.overall_accesses::total 46167139 # number of overall (read+write) accesses
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-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.061850 # miss rate for LoadLockedReq accesses
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-system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000144 # miss rate for StoreCondReq accesses
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-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 18293.136077 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 17432.364449 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 73361.628844 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 63145.607246 # average WriteReq miss latency
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-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13855.996622 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14881.927754 # average LoadLockedReq miss latency
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-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 34718.750000 # average StoreCondReq miss latency
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system.cpu0.dcache.fast_writes 0 # number of fast writes performed
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system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31129 # number of ReadReq MSHR uncacheable
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system.cpu0.dcache.WriteReq_mshr_uncacheable::total 27588 # number of WriteReq MSHR uncacheable
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system.cpu0.dcache.overall_mshr_uncacheable_misses::total 58717 # number of overall MSHR uncacheable misses
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-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 3393296500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6725374000 # number of ReadReq MSHR miss cycles
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-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 9853624962 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 21038511346 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1108891500 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 759475500 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1868367000 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 93281500 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 59417500 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 152699000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 837500 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 1079000 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1916500 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 14516963884 # number of demand (read+write) MSHR miss cycles
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-system.cpu0.dcache.demand_mshr_miss_latency::total 27763885346 # number of demand (read+write) MSHR miss cycles
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-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 14006396962 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 29632252346 # number of overall MSHR miss cycles
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-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3337097500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6301062000 # number of ReadReq MSHR uncacheable cycles
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-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5084194876 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5557492924 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5827763952 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11385256876 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016407 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.016405 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016406 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015425 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015159 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015293 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.245410 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.199063 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224516 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.019130 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.019137 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.019133 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000144 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000144 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000144 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.015980 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.015877 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.015928 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.019005 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.017819 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.018406 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15955.398229 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15559.085428 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15752.946633 # average ReadReq mshr miss latency
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-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 66446.999939 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 70205.363035 # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15001.034889 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15429.594490 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15172.336227 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 19978.903405 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13516.264786 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16844.897959 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24632.352941 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 33718.750000 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 29037.878788 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 40300.831126 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 36155.840490 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 38210.739825 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35992.996167 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 33701.142337 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 34872.058044 # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200824.208957 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 203854.459377 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202417.745511 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 170279.589259 # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 201559.152869 # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184290.085399 # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 185311.534645 # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 202867.126814 # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 193900.520735 # average overall mshr uncacheable latency
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+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 753142000 # number of SoftPFReq MSHR miss cycles
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+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 58899500 # number of LoadLockedReq MSHR miss cycles
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+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 1074500 # number of StoreCondReq MSHR miss cycles
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+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 13985190455 # number of overall MSHR miss cycles
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+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2963154000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3337800500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6300954500 # number of ReadReq MSHR uncacheable cycles
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+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5830677952 # number of overall MSHR uncacheable cycles
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+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016426 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.016383 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016404 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015439 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015133 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015286 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.245839 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.197790 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224206 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.019405 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.018986 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.019202 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000148 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000166 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000157 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.015997 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.015853 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.015924 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.019030 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.017780 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.018399 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15943.187850 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15561.974211 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15748.719216 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 73948.080558 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 66523.491738 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 70280.746403 # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15011.964014 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15418.072388 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15173.262215 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 20188.860706 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13487.405542 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16972.191690 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 26200 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 29040.540541 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27659.722222 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 40320.352181 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 36179.531120 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 38235.631508 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 36005.452157 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 33733.312561 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 34896.492398 # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200837.332249 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 203835.145038 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202414.292139 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 170247.482031 # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 201574.953667 # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184290.792229 # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 185304.117565 # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 202862.638369 # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 193899.022021 # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements 1935383 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.471478 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 38825027 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 1935895 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 20.055337 # Average number of references to valid blocks.
+system.cpu0.icache.tags.replacements 1936583 # number of replacements
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+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13490.158162 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13446.120560 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13399.059614 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13490.158162 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 13446.120560 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13399.059614 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13490.158162 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 13446.120560 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 129500.748503 # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 129500.748503 # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 129500.748503 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 129500.748503 # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups 27845769 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 14562032 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 548670 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 17327416 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 13125788 # Number of BTB hits
+system.cpu1.branchPred.lookups 27851239 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 14560281 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 547901 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 17369720 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 13131935 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 75.751560 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 6844508 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 29088 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 75.602456 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 6845775 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 28937 # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.dtb.walker.walks 58263 # Table walker walks requested
-system.cpu1.dtb.walker.walksShort 58263 # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19122 # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 13746 # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore 25395 # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples 32868 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean 735.822076 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev 5166.451241 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-16383 32439 98.69% 98.69% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::16384-32767 307 0.93% 99.63% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::32768-49151 56 0.17% 99.80% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::49152-65535 28 0.09% 99.88% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::65536-81919 13 0.04% 99.92% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walks 58134 # Table walker walks requested
+system.cpu1.dtb.walker.walksShort 58134 # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19184 # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 13709 # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore 25241 # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples 32893 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean 754.218223 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev 5187.950869 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-16383 32437 98.61% 98.61% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::16384-32767 325 0.99% 99.60% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::32768-49151 66 0.20% 99.80% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::49152-65535 27 0.08% 99.88% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::65536-81919 14 0.04% 99.93% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::81920-98303 5 0.02% 99.94% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::98304-114687 7 0.02% 99.96% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::114688-131071 6 0.02% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::131072-147455 3 0.01% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::98304-114687 6 0.02% 99.96% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::114688-131071 7 0.02% 99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::131072-147455 2 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::147456-163839 4 0.01% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total 32868 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples 13303 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 14575.358942 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 12191.227269 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 8603.178174 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-32767 12998 97.71% 97.71% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-65535 295 2.22% 99.92% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkWaitTime::total 32893 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples 13323 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 14712.226976 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 12353.172902 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 8523.936722 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-32767 13006 97.62% 97.62% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-65535 308 2.31% 99.93% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-98303 7 0.05% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-163839 2 0.02% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-163839 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total 13303 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples 91468436244 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean 0.768300 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev 0.445212 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0-1 91380739744 99.90% 99.90% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::2-3 61381000 0.07% 99.97% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::4-5 13682000 0.01% 99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::6-7 4674500 0.01% 99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::8-9 2423500 0.00% 99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::10-11 1725000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::12-13 730000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::14-15 2073000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::16-17 390500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::18-19 252000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::20-21 85000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::22-23 23000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::24-25 127500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::26-27 26000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::28-29 16000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::30-31 87500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total 91468436244 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K 3764 68.66% 68.66% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M 1718 31.34% 100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total 5482 # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 58263 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkCompletionTime::total 13323 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples 91468552244 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean 0.754474 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev 0.453530 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0-1 91381383244 99.90% 99.90% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::2-3 60460000 0.07% 99.97% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::4-5 14228500 0.02% 99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::6-7 4319000 0.00% 99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::8-9 2420500 0.00% 99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::10-11 1621000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::12-13 756000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::14-15 2345500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::16-17 509500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::18-19 194000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::20-21 44500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::22-23 92500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::24-25 69000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::26-27 14000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::28-29 16500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::30-31 78500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total 91468552244 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K 3728 68.30% 68.30% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M 1730 31.70% 100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total 5458 # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 58134 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 58263 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5482 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 58134 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5458 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5482 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total 63745 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5458 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total 63592 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 14429074 # DTB read hits
-system.cpu1.dtb.read_misses 50206 # DTB read misses
-system.cpu1.dtb.write_hits 10478740 # DTB write hits
-system.cpu1.dtb.write_misses 8057 # DTB write misses
-system.cpu1.dtb.flush_tlb 185 # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva 448 # Number of times TLB was flushed by MVA
+system.cpu1.dtb.read_hits 14422090 # DTB read hits
+system.cpu1.dtb.read_misses 50182 # DTB read misses
+system.cpu1.dtb.write_hits 10473943 # DTB write hits
+system.cpu1.dtb.write_misses 7952 # DTB write misses
+system.cpu1.dtb.flush_tlb 187 # Number of times complete TLB was flushed
+system.cpu1.dtb.flush_tlb_mva 438 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 3590 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 793 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 1278 # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries 3617 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 774 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 1261 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 676 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 14479280 # DTB read accesses
-system.cpu1.dtb.write_accesses 10486797 # DTB write accesses
+system.cpu1.dtb.perms_faults 668 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 14472272 # DTB read accesses
+system.cpu1.dtb.write_accesses 10481895 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 24907814 # DTB hits
-system.cpu1.dtb.misses 58263 # DTB misses
-system.cpu1.dtb.accesses 24966077 # DTB accesses
+system.cpu1.dtb.hits 24896033 # DTB hits
+system.cpu1.dtb.misses 58134 # DTB misses
+system.cpu1.dtb.accesses 24954167 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.walker.walks 7966 # Table walker walks requested
-system.cpu1.itb.walker.walksShort 7966 # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walks 8670 # Table walker walks requested
+system.cpu1.itb.walker.walksShort 8670 # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2733 # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksShortTerminationLevel::Level2 5041 # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksSquashedBefore 192 # Table walks squashed before starting
-system.cpu1.itb.walker.walkWaitTime::samples 7774 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::mean 1441.214304 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::stdev 6187.766292 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0-8191 7329 94.28% 94.28% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::8192-16383 184 2.37% 96.64% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::16384-24575 160 2.06% 98.70% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::24576-32767 32 0.41% 99.11% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::32768-40959 22 0.28% 99.40% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::40960-49151 15 0.19% 99.59% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::49152-57343 13 0.17% 99.76% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::57344-65535 10 0.13% 99.88% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::65536-73727 5 0.06% 99.95% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::73728-81919 2 0.03% 99.97% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::81920-90111 2 0.03% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total 7774 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples 2664 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 14886.824324 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 12507.436482 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 8471.321316 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-8191 630 23.65% 23.65% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::8192-16383 1227 46.06% 69.71% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::16384-24575 650 24.40% 94.11% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::24576-32767 95 3.57% 97.67% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-40959 18 0.68% 98.35% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::40960-49151 35 1.31% 99.66% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::49152-57343 4 0.15% 99.81% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::57344-65535 3 0.11% 99.92% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::81920-90111 1 0.04% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total 2664 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples 31323904600 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::mean 0.850464 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::stdev 0.357128 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0 4688399000 14.97% 14.97% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::1 26632295600 85.02% 99.99% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::2 2300000 0.01% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::3 720500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::4 157500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::5 32000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total 31323904600 # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K 1884 76.21% 76.21% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::1M 588 23.79% 100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total 2472 # Table walker page sizes translated
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2 5073 # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksSquashedBefore 864 # Table walks squashed before starting
+system.cpu1.itb.walker.walkWaitTime::samples 7806 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::mean 1475.083269 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::stdev 5979.271301 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0-8191 7339 94.02% 94.02% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::8192-16383 201 2.57% 96.59% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::16384-24575 162 2.08% 98.67% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::24576-32767 41 0.53% 99.19% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::32768-40959 20 0.26% 99.45% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::40960-49151 18 0.23% 99.68% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::49152-57343 11 0.14% 99.82% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::57344-65535 7 0.09% 99.91% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::65536-73727 6 0.08% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::81920-90111 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total 7806 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples 3293 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 13788.642575 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 11489.093660 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 8040.901956 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-8191 943 28.64% 28.64% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::8192-16383 1544 46.89% 75.52% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::16384-24575 636 19.31% 94.84% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::24576-32767 109 3.31% 98.15% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-40959 26 0.79% 98.94% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::40960-49151 30 0.91% 99.85% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::49152-57343 2 0.06% 99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::57344-65535 1 0.03% 99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::81920-90111 1 0.03% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::90112-98303 1 0.03% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total 3293 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples 39929935692 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::mean 0.810654 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::stdev 0.392199 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0 7566087000 18.95% 18.95% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::1 32359225692 81.04% 99.99% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::2 3801500 0.01% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::3 739500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::4 82000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total 39929935692 # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K 1840 75.75% 75.75% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M 589 24.25% 100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total 2429 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 7966 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total 7966 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 8670 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total 8670 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2472 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2472 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total 10438 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 20781807 # ITB inst hits
-system.cpu1.itb.inst_misses 7966 # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2429 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2429 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total 11099 # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits 20800432 # ITB inst hits
+system.cpu1.itb.inst_misses 8670 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
-system.cpu1.itb.flush_tlb 185 # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva 448 # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb 187 # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb_mva 438 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 2418 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 2396 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 1467 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 1452 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 20789773 # ITB inst accesses
-system.cpu1.itb.hits 20781807 # DTB hits
-system.cpu1.itb.misses 7966 # DTB misses
-system.cpu1.itb.accesses 20789773 # DTB accesses
-system.cpu1.numCycles 114304919 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 20809102 # ITB inst accesses
+system.cpu1.itb.hits 20800432 # DTB hits
+system.cpu1.itb.misses 8670 # DTB misses
+system.cpu1.itb.accesses 20809102 # DTB accesses
+system.cpu1.numCycles 114311171 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles 41262739 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 107285498 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 27845769 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 19970296 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 67416194 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 3259780 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles 133608 # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles 6817 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingDrainCycles 414 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu1.fetch.PendingTrapStallCycles 250513 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 129856 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles 415 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 20779736 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 377856 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes 3597 # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples 110830408 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 1.164170 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 2.274550 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles 41255732 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 107366172 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 27851239 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 19977710 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 67431456 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 3269763 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles 132240 # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles 6802 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingDrainCycles 490 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu1.fetch.PendingTrapStallCycles 244886 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 129624 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 516 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 20797736 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 380485 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes 4341 # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples 110836590 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 1.165245 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 2.275623 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 81247279 73.31% 73.31% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 3969752 3.58% 76.89% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 2463714 2.22% 79.11% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 8233608 7.43% 86.54% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 1683058 1.52% 88.06% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 1119193 1.01% 89.07% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 6323043 5.71% 94.78% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 1165134 1.05% 95.83% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 4625627 4.17% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 81231588 73.29% 73.29% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 3970288 3.58% 76.87% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 2467097 2.23% 79.10% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 8234974 7.43% 86.53% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 1686085 1.52% 88.05% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 1118021 1.01% 89.06% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 6327387 5.71% 94.77% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 1165631 1.05% 95.82% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 4635519 4.18% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 110830408 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.243610 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 0.938590 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 28323614 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 63478712 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 15848046 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 1704488 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 1475224 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 1967997 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 156746 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 89079205 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 507140 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 1475224 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 29256624 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 7018147 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 46666766 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 16607219 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 9806111 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 85232877 # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents 3842 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 1674461 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents 301333 # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents 7083529 # Number of times rename has blocked due to SQ full
-system.cpu1.rename.RenamedOperands 88409572 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 391941986 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 94718838 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 6483 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 74424798 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 13984774 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 1569429 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 1471935 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 9797660 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 15298042 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 11560096 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 2146916 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 2735796 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 82036026 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 1094252 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 78550725 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 92381 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 11493580 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 25147781 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 115638 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 110830408 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.708747 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.399658 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 110836590 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.243644 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 0.939245 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 28312223 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 63485769 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 15857940 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 1699967 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 1480365 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 1967991 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 156560 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 89109002 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 506529 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 1480365 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 29245196 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 7030025 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 46679858 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 16613031 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 9787785 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 85253260 # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents 3942 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 1676107 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents 305456 # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents 7062303 # Number of times rename has blocked due to SQ full
+system.cpu1.rename.RenamedOperands 88411129 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 392062369 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 94760881 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 6288 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 74434583 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 13976546 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 1569925 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 1472475 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 9793304 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 15295862 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 11556895 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 2150664 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 2742502 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 82043962 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 1094941 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 78552222 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 91402 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 11492320 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 25159173 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 115830 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 110836590 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 0.708721 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 1.399471 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 79265861 71.52% 71.52% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 10536379 9.51% 81.03% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 8138054 7.34% 88.37% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 6692872 6.04% 94.41% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 2461657 2.22% 96.63% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 1496595 1.35% 97.98% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 1550739 1.40% 99.38% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 480423 0.43% 99.81% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8 207828 0.19% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 79260307 71.51% 71.51% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 10548653 9.52% 81.03% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 8143333 7.35% 88.38% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 6690324 6.04% 94.41% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 2458107 2.22% 96.63% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 1498250 1.35% 97.98% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 1549439 1.40% 99.38% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 479797 0.43% 99.81% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8 208380 0.19% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 110830408 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 110836590 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 101678 9.04% 9.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 6 0.00% 9.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 527402 46.88% 55.91% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 496001 44.09% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 101010 9.00% 9.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 6 0.00% 9.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 525539 46.85% 55.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 495241 44.15% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass 2108 0.00% 0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 52628627 67.00% 67.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 59575 0.08% 67.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 67.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 67.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 67.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 67.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 67.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 67.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 67.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 67.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 67.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 2 0.00% 67.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 67.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 67.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 1 0.00% 67.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 67.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 67.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 67.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 67.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 4540 0.01% 67.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 67.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 67.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 14828760 18.88% 85.96% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 11027108 14.04% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass 2114 0.00% 0.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 52641439 67.01% 67.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 59500 0.08% 67.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 67.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 67.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 67.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 67.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 67.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 67.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 67.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 67.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 67.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 1 0.00% 67.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 67.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 67.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 1 0.00% 67.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 67.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 67.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 67.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 67.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 4515 0.01% 67.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 67.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 67.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 14821785 18.87% 85.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 11022863 14.03% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 78550725 # Type of FU issued
-system.cpu1.iq.rate 0.687203 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 1125087 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.014323 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 269134534 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 94666903 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 76208953 # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads 14792 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 7758 # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses 6343 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 79665710 # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses 7994 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 356293 # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total 78552222 # Type of FU issued
+system.cpu1.iq.rate 0.687179 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 1121796 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.014281 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 269139975 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 94675085 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 76216531 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads 14257 # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes 7438 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 6100 # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses 79664197 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 7707 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 356033 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 2229171 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 2454 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 52006 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 1113437 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 2227814 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 2318 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 52493 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 1114040 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 210295 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 83250 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads 209025 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 78912 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 1475224 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 5653041 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 1062018 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 83263917 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 132733 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 15298042 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 11560096 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 563089 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 44760 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 1004107 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 52006 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 252720 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 221535 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 474255 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 77947224 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 14588142 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 545356 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles 1480365 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 5648229 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 1078467 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 83272482 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 147374 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 15295862 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 11556895 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 563425 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 44942 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 1020454 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 52493 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 252230 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 220958 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 473188 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 77949376 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 14581691 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 544828 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 133639 # number of nop insts executed
-system.cpu1.iew.exec_refs 25509801 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 14792912 # Number of branches executed
-system.cpu1.iew.exec_stores 10921659 # Number of stores executed
-system.cpu1.iew.exec_rate 0.681924 # Inst execution rate
-system.cpu1.iew.wb_sent 77399015 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 76215296 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 39901204 # num instructions producing a value
-system.cpu1.iew.wb_consumers 69370380 # num instructions consuming a value
-system.cpu1.iew.wb_rate 0.666772 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.575191 # average fanout of values written-back
-system.cpu1.commit.commitSquashedInsts 11469424 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 978614 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 393966 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 108251669 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.662485 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.545489 # Number of insts commited each cycle
+system.cpu1.iew.exec_nop 133579 # number of nop insts executed
+system.cpu1.iew.exec_refs 25499167 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 14792050 # Number of branches executed
+system.cpu1.iew.exec_stores 10917476 # Number of stores executed
+system.cpu1.iew.exec_rate 0.681905 # Inst execution rate
+system.cpu1.iew.wb_sent 77406308 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 76222631 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 39922690 # num instructions producing a value
+system.cpu1.iew.wb_consumers 69416540 # num instructions consuming a value
+system.cpu1.iew.wb_rate 0.666799 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.575118 # average fanout of values written-back
+system.cpu1.commit.commitSquashedInsts 11468538 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 979111 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 393347 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 108253443 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 0.662563 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 1.545359 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 80229014 74.11% 74.11% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 12491692 11.54% 85.65% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 6522560 6.03% 91.68% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 2655731 2.45% 94.13% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 1400574 1.29% 95.43% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 922085 0.85% 96.28% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 1916585 1.77% 98.05% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 408524 0.38% 98.43% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 1704904 1.57% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 80221800 74.11% 74.11% # Number of insts commited each cycle
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system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
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-system.cpu1.commit.committedInsts 59075806 # Number of instructions committed
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system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
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-system.cpu1.commit.loads 13068871 # Number of loads committed
-system.cpu1.commit.membars 397484 # Number of memory barriers committed
-system.cpu1.commit.branches 14003876 # Number of branches committed
-system.cpu1.commit.fp_insts 6270 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 62677784 # Number of committed integer instructions.
-system.cpu1.commit.function_calls 2707088 # Number of function calls committed.
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system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
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-system.cpu1.commit.bw_lim_events 1704904 # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads 176979703 # The number of ROB reads
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-system.cpu1.timesIdled 412631 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 3474511 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 3325420537 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 58997368 # Number of Instructions Simulated
-system.cpu1.committedOps 71636698 # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi 1.937458 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 1.937458 # CPI: Total CPI of All Threads
-system.cpu1.ipc 0.516140 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.516140 # IPC: Total IPC of All Threads
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+system.cpu1.cpi_total 1.937039 # CPI: Total CPI of All Threads
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+system.cpu1.ipc_total 0.516252 # IPC: Total IPC of All Threads
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system.iobus.trans_dist::ReadReq 30172 # Transaction distribution
system.iobus.trans_dist::ReadResp 30172 # Transaction distribution
system.iobus.trans_dist::WriteReq 59014 # Transaction distribution
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321016 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.pkt_size::total 2480141 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 28500 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 36718000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
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system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 236543521000 # Cycle when the warmup percentage was hit.
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system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.overall_misses::total 223 # number of overall misses
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system.iocache.ReadReq_avg_miss_latency::realview.ide 126046.533632 # average ReadReq miss latency
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system.iocache.overall_mshr_misses::total 223 # number of overall MSHR misses
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system.iocache.demand_mshr_miss_latency::total 16958377 # number of demand (read+write) MSHR miss cycles
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system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
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system.iocache.demand_avg_mshr_miss_latency::realview.ide 76046.533632 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 76046.533632 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 76046.533632 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 76046.533632 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.tags.replacements 104258 # number of replacements
-system.l2c.tags.tagsinuse 65109.968422 # Cycle average of tags in use
-system.l2c.tags.total_refs 5143670 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 169575 # Sample count of references to valid blocks.
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-system.l2c.tags.warmup_cycle 74702530500 # Cycle when the warmup percentage was hit.
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system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000314 # Average occupied blocks per requestor
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+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011126 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.171732 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.061224 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001657 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000132 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.010336 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data 0.190902 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.002251 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011126 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.171732 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.061224 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 129271.929825 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 122500 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 126037.037037 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 129737.410072 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 68016.335227 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 68012.849584 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 68014.646650 # average UpgradeReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 130361.445783 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 129865.248227 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 68022.503516 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 68022.831050 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 68022.660819 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 68500 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 68350 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 68406.250000 # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 123472.485592 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 123695.372647 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 123575.488551 # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 123282.440797 # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122975.562736 # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 123118.502957 # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 125652.447577 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128291.012981 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 126869.072157 # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 135122.807018 # average overall mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 68444.444444 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 68468.750000 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 123588.533668 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 123625.407695 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 123605.560123 # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 123537.508060 # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 123103.934783 # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 123305.574483 # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 125187.234772 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 127916.809402 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 126444.146146 # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 129271.929825 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 122500 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 123282.440797 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 123686.385502 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 126037.037037 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122975.562736 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 124144.606230 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 123810.661044 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 135122.807018 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 123537.508060 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 123745.752562 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 130361.445783 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123103.934783 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 124045.493871 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 123820.613689 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 129271.929825 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 122500 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 123282.440797 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 123686.385502 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 126037.037037 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122975.562736 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 124144.606230 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 123810.661044 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 123537.508060 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 123745.752562 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 130361.445783 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123103.934783 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 124045.493871 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 123820.613689 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113784.426647 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 188322.718341 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 191352.962737 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 188316.853697 # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 158640.699888 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 190053.330096 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172710.798173 # average WriteReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 188336.146130 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 191333.801527 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 188313.693021 # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 158608.534262 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 190068.852592 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172711.396259 # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113784.426647 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 173248.132711 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 190793.922094 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 181066.877107 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 173240.767306 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 190789.524041 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 181065.462608 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 31797 # Transaction distribution
-system.membus.trans_dist::ReadResp 68158 # Transaction distribution
+system.membus.trans_dist::ReadResp 68215 # Transaction distribution
system.membus.trans_dist::WriteReq 27588 # Transaction distribution
system.membus.trans_dist::WriteResp 27588 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 131684 # Transaction distribution
-system.membus.trans_dist::CleanEvict 8987 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 4621 # Transaction distribution
+system.membus.trans_dist::WritebackDirty 131889 # Transaction distribution
+system.membus.trans_dist::CleanEvict 8934 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 4627 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 16 # Transaction distribution
system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
-system.membus.trans_dist::ReadExReq 138118 # Transaction distribution
-system.membus.trans_dist::ReadExResp 138118 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 36362 # Transaction distribution
+system.membus.trans_dist::ReadExReq 138214 # Transaction distribution
+system.membus.trans_dist::ReadExResp 138214 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 36419 # Transaction distribution
system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 22 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2082 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 468311 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 575893 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 468775 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 576357 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72875 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 72875 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 648768 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 649232 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 704 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4164 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17307612 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 17471605 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17330524 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 17494517 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 19788725 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 19811637 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 495 # Total snoops (count)
-system.membus.snoop_fanout::samples 415409 # Request fanout histogram
+system.membus.snoop_fanout::samples 415722 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 415409 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 415722 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 415409 # Request fanout histogram
-system.membus.reqLayer0.occupancy 95443000 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 415722 # Request fanout histogram
+system.membus.reqLayer0.occupancy 95416500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 17812 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 1716000 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 1712500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 922132455 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 923381363 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 1008187748 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 1008957748 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 1182123 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests 5622550 # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests 2830625 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests 48155 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops 418 # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops 418 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.tot_requests 5624778 # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests 2831936 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests 48182 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops 419 # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops 419 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq 147977 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 2643178 # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq 148456 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 2644699 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 27588 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 27588 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty 836971 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean 1935383 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 159154 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 2818 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 66 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 2884 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 296889 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 296889 # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq 1935963 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 559323 # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty 836907 # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean 1936583 # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict 159084 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 2829 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 72 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 2901 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 296764 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 296764 # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq 1937168 # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq 559160 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5808360 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2690765 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 40688 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 162297 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 8702110 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 247790656 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 100113141 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 62776 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 284444 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 348251017 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 206924 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 3147531 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 0.027177 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.162600 # Request fanout histogram
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5811959 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2689934 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41086 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 162624 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 8705603 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 247943872 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 100077301 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 63112 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 285092 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 348369377 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 207323 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 3149099 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 0.027296 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.162945 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 3061989 97.28% 97.28% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 85542 2.72% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 3063141 97.27% 97.27% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 85958 2.73% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 3147531 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 5535076493 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 3149099 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 5537165495 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 269377 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 2906930517 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 2908738015 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 1330817051 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 1330413513 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 25031921 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy 25349416 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 91623614 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy 91789111 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 3037 # number of quiesce instructions executed
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm64
+boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm64
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb
+dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch64.20140821.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
+exit_on_work_items=false
flags_addr=469827632
gic_cpu_addr=738205696
have_large_asid_64=false
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821
+kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch64.20140821
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
+readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img
+image_file=/home/stever/m5/aarch-system-2014-10/disks/linaro-minimal-aarch64.img
read_only=true
[system.clk_domain]
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=false
hit_latency=1
is_read_only=true
max_miss_count=0
clusivity=mostly_excl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=12
is_read_only=false
max_miss_count=0
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.cpu0.toL2Bus.snoop_filter
snoop_response_latency=1
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=false
hit_latency=1
is_read_only=true
max_miss_count=0
clusivity=mostly_excl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=12
is_read_only=false
max_miss_count=0
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.cpu1.toL2Bus.snoop_filter
snoop_response_latency=1
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=false
hit_latency=50
is_read_only=false
max_miss_count=0
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.toL2Bus.snoop_filter
snoop_response_latency=1
+Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual/simout
+Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 4 2015 11:13:17
-gem5 started Dec 4 2015 12:36:35
-gem5 executing on e104799-lin, pid 5221
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual
+gem5 compiled Mar 15 2016 21:26:42
+gem5 started Mar 15 2016 21:34:31
+gem5 executing on phenom, pid 15970
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual
Selected 64-bit ARM architecture, updating default disk image...
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch64.20140821
+info: kernel located at: /home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch64.20140821
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80080000
-info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
+info: Loading DTB file: /home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 47381683294000 because m5_exit instruction encountered
+Exiting @ tick 47454492026000 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 47.496138 # Number of seconds simulated
-sim_ticks 47496138032000 # Number of ticks simulated
-final_tick 47496138032000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 47.454492 # Number of seconds simulated
+sim_ticks 47454492026000 # Number of ticks simulated
+final_tick 47454492026000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 287392 # Simulator instruction rate (inst/s)
-host_op_rate 338020 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 15163142641 # Simulator tick rate (ticks/s)
-host_mem_usage 759192 # Number of bytes of host memory used
-host_seconds 3132.34 # Real time elapsed on the host
-sim_insts 900209792 # Number of instructions simulated
-sim_ops 1058792792 # Number of ops (including micro ops) simulated
+host_inst_rate 169815 # Simulator instruction rate (inst/s)
+host_op_rate 199687 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 8468561033 # Simulator tick rate (ticks/s)
+host_mem_usage 764912 # Number of bytes of host memory used
+host_seconds 5603.61 # Real time elapsed on the host
+sim_insts 951575519 # Number of instructions simulated
+sim_ops 1118968402 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker 123968 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 99904 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 7981184 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 13323912 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher 15275072 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 135168 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker 122048 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 3081152 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 10821968 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher 12736320 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 446656 # Number of bytes read from this memory
-system.physmem.bytes_read::total 64147352 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 7981184 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 3081152 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 11062336 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 76613760 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker 233088 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 210624 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 7916672 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 17537736 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher 18153728 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 166400 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker 132160 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 3894272 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 12497872 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher 21171968 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 432064 # Number of bytes read from this memory
+system.physmem.bytes_read::total 82346584 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 7916672 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 3894272 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 11810944 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 92922304 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
-system.physmem.bytes_written::total 76634344 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker 1937 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 1561 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 124706 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 208199 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher 238673 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 2112 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker 1907 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 48143 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 169106 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher 199005 # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide 6979 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1002328 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1197090 # Number of write requests responded to by this memory
+system.physmem.bytes_written::total 92942888 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker 3642 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 3291 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 123698 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 274040 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher 283652 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 2600 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker 2065 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 60848 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 195292 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher 330812 # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide 6751 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 1286691 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1451911 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1199664 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker 2610 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 2103 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 168039 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 280526 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher 321607 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 2846 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker 2570 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 64872 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 227849 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher 268155 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 9404 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1350580 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 168039 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 64872 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 232910 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1613052 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 1454485 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker 4912 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 4438 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 166827 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 369570 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher 382550 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 3507 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker 2785 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 82063 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 263365 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher 446153 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide 9105 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1735275 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 166827 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 82063 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 248890 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1958135 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1613486 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1613052 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 2610 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 2103 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 168039 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 280960 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher 321607 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 2846 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker 2570 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 64872 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 227850 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher 268155 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 9404 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2964066 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 1002328 # Number of read requests accepted
-system.physmem.writeReqs 1199664 # Number of write requests accepted
-system.physmem.readBursts 1002328 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 1199664 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 64118976 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 30016 # Total number of bytes read from write queue
-system.physmem.bytesWritten 76632896 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 64147352 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 76634344 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 469 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_write::total 1958569 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1958135 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 4912 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 4438 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 166827 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 370003 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher 382550 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 3507 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker 2785 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 82063 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 263365 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher 446153 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 9105 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 3693844 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 1286691 # Number of read requests accepted
+system.physmem.writeReqs 1454485 # Number of write requests accepted
+system.physmem.readBursts 1286691 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 1454485 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 82317440 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 30784 # Total number of bytes read from write queue
+system.physmem.bytesWritten 92941888 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 82346584 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 92942888 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 481 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 52312 # Per bank write bursts
-system.physmem.perBankRdBursts::1 66235 # Per bank write bursts
-system.physmem.perBankRdBursts::2 59334 # Per bank write bursts
-system.physmem.perBankRdBursts::3 65978 # Per bank write bursts
-system.physmem.perBankRdBursts::4 61446 # Per bank write bursts
-system.physmem.perBankRdBursts::5 69476 # Per bank write bursts
-system.physmem.perBankRdBursts::6 59128 # Per bank write bursts
-system.physmem.perBankRdBursts::7 60480 # Per bank write bursts
-system.physmem.perBankRdBursts::8 57677 # Per bank write bursts
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system.physmem.rdPerTurnAround::29696-30719 1 0.00% 100.00% # Reads before turning the bus around for writes
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-system.physmem.wrPerTurnAround::156-159 2 0.00% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163 1 0.00% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179 4 0.01% 100.00% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total 77530 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 77530 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 18.731033 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.088703 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 7.268543 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 64617 83.34% 83.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 6035 7.78% 91.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 3056 3.94% 95.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 1620 2.09% 97.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 474 0.61% 97.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 277 0.36% 98.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 269 0.35% 98.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 83 0.11% 98.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 290 0.37% 98.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 69 0.09% 99.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 30 0.04% 99.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 52 0.07% 99.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 249 0.32% 99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 33 0.04% 99.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 40 0.05% 99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79 110 0.14% 99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 167 0.22% 99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87 1 0.00% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91 2 0.00% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95 2 0.00% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99 1 0.00% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103 1 0.00% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107 2 0.00% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111 1 0.00% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115 2 0.00% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123 3 0.00% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 15 0.02% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135 1 0.00% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139 1 0.00% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143 5 0.01% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147 13 0.02% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159 3 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163 2 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179 2 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-243 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 62276 # Writes before turning the bus around for reads
-system.physmem.totQLat 32552700191 # Total ticks spent queuing
-system.physmem.totMemAccLat 51337556441 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 5009295000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 32492.30 # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::208-211 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 77530 # Writes before turning the bus around for reads
+system.physmem.totQLat 47048753044 # Total ticks spent queuing
+system.physmem.totMemAccLat 71165190544 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 6431050000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 36579.37 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 51242.30 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1.35 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 1.61 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1.35 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 1.61 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 55329.37 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1.73 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 1.96 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1.74 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 1.96 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.02 # Data bus utilization in percentage
+system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.13 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 23.36 # Average write queue length when enqueuing
-system.physmem.readRowHits 748874 # Number of row buffer hits during reads
-system.physmem.writeRowHits 456536 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 74.75 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 38.13 # Row buffer hit rate for writes
-system.physmem.avgGap 21569622.38 # Average gap between requests
-system.physmem.pageHitRate 54.81 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 3877765920 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 2115844500 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 3856171800 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 3970542240 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 3102216508560 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 1199773763640 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 27445246701750 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 31761057298410 # Total energy per rank (pJ)
-system.physmem_0.averagePower 668.708277 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 45657180846254 # Time in different power states
-system.physmem_0.memoryStateTime::REF 1586000260000 # Time in different power states
+system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 24.33 # Average write queue length when enqueuing
+system.physmem.readRowHits 962295 # Number of row buffer hits during reads
+system.physmem.writeRowHits 551527 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 74.82 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 37.98 # Row buffer hit rate for writes
+system.physmem.avgGap 17311726.76 # Average gap between requests
+system.physmem.pageHitRate 55.28 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 4656869280 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 2540950500 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 4884235200 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 4726421280 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 3099496729680 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 1219171959180 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 27403246221750 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 31738723386870 # Total energy per rank (pJ)
+system.physmem_0.averagePower 668.824424 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 45587152483743 # Time in different power states
+system.physmem_0.memoryStateTime::REF 1584609520000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 252951953746 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 282729931257 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 3635634240 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 1983729000 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 3958266000 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 3788538480 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 3102216508560 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 1194664304160 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 27449728675500 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 31759975655940 # Total energy per rank (pJ)
-system.physmem_1.averagePower 668.685504 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 45664625089280 # Time in different power states
-system.physmem_1.memoryStateTime::REF 1586000260000 # Time in different power states
+system.physmem_1.actEnergy 4601144520 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 2510545125 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 5148202800 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 4683944880 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 3099496729680 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 1221460881390 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 27401238395250 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 31739139843645 # Total energy per rank (pJ)
+system.physmem_1.averagePower 668.833200 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 45583769039323 # Time in different power states
+system.physmem_1.memoryStateTime::REF 1584609520000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 245507696970 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 286113375677 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1674 # Number of DMA write transactions.
-system.cpu0.branchPred.lookups 138061860 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 98120507 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 6229967 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 103103324 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 75422199 # Number of BTB hits
+system.cpu0.branchPred.lookups 147959066 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 105493690 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 6448516 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 111296242 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 81329533 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 73.152054 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 16055942 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 1103312 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 73.074824 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 17161750 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 1109253 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.walks 287097 # Table walker walks requested
-system.cpu0.dtb.walker.walksLong 287097 # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9253 # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 79328 # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walkWaitTime::samples 287097 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0 287097 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 287097 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples 88581 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 23354.082704 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 21377.049680 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 19303.806083 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535 87487 98.76% 98.76% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071 212 0.24% 99.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607 756 0.85% 99.86% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143 30 0.03% 99.89% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-327679 31 0.03% 99.93% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-393215 18 0.02% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::393216-458751 29 0.03% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::458752-524287 10 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::524288-589823 5 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total 88581 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walks 300034 # Table walker walks requested
+system.cpu0.dtb.walker.walksLong 300034 # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 11904 # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 91094 # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walkWaitTime::samples 300034 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0 300034 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total 300034 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples 102998 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 24703.863182 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 21663.255890 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 26203.116698 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-65535 100872 97.94% 97.94% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071 180 0.17% 98.11% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-196607 1639 1.59% 99.70% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-262143 73 0.07% 99.77% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-327679 76 0.07% 99.85% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-393215 46 0.04% 99.89% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-458751 69 0.07% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::458752-524287 28 0.03% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::524288-589823 6 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::589824-655359 7 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total 102998 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples -909613592 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0 -909613592 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total -909613592 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 79328 89.55% 89.55% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M 9253 10.45% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 88581 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 287097 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkPageSizes::4K 91094 88.44% 88.44% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M 11904 11.56% 100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total 102998 # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 300034 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 287097 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 88581 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 300034 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 102998 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 88581 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 375678 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 102998 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total 403032 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 87655759 # DTB read hits
-system.cpu0.dtb.read_misses 237615 # DTB read misses
-system.cpu0.dtb.write_hits 78096829 # DTB write hits
-system.cpu0.dtb.write_misses 49482 # DTB write misses
-system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
+system.cpu0.dtb.read_hits 94891169 # DTB read hits
+system.cpu0.dtb.read_misses 247198 # DTB read misses
+system.cpu0.dtb.write_hits 84318368 # DTB write hits
+system.cpu0.dtb.write_misses 52836 # DTB write misses
+system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 42183 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 36184 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 2196 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 9698 # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_tlb_mva_asid 47226 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 1094 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 40307 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 1747 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 9392 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 11726 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 87893374 # DTB read accesses
-system.cpu0.dtb.write_accesses 78146311 # DTB write accesses
+system.cpu0.dtb.perms_faults 12141 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 95138367 # DTB read accesses
+system.cpu0.dtb.write_accesses 84371204 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 165752588 # DTB hits
-system.cpu0.dtb.misses 287097 # DTB misses
-system.cpu0.dtb.accesses 166039685 # DTB accesses
+system.cpu0.dtb.hits 179209537 # DTB hits
+system.cpu0.dtb.misses 300034 # DTB misses
+system.cpu0.dtb.accesses 179509571 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.walker.walks 66101 # Table walker walks requested
-system.cpu0.itb.walker.walksLong 66101 # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2 650 # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3 56681 # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples 66101 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0 66101 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total 66101 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples 57331 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 26460.544906 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 23886.492389 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 21943.926110 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-65535 56305 98.21% 98.21% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-131071 11 0.02% 98.23% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-196607 903 1.58% 99.80% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-262143 44 0.08% 99.88% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-327679 42 0.07% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-393215 14 0.02% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-458751 8 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::458752-524287 3 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total 57331 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walks 71231 # Table walker walks requested
+system.cpu0.itb.walker.walksLong 71231 # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2 667 # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3 60897 # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples 71231 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0 71231 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total 71231 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples 61564 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 29116.975830 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 24576.932577 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 30900.488305 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-65535 59287 96.30% 96.30% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-131071 14 0.02% 96.32% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-196607 2011 3.27% 99.59% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-262143 94 0.15% 99.74% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-327679 85 0.14% 99.88% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-393215 46 0.07% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-458751 21 0.03% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::458752-524287 4 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total 61564 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples -910742092 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 -910742092 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total -910742092 # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K 56681 98.87% 98.87% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M 650 1.13% 100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total 57331 # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::4K 60897 98.92% 98.92% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M 667 1.08% 100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total 61564 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 66101 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total 66101 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 71231 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total 71231 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 57331 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total 57331 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total 123432 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 246672238 # ITB inst hits
-system.cpu0.itb.inst_misses 66101 # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 61564 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total 61564 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total 132795 # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits 264582301 # ITB inst hits
+system.cpu0.itb.inst_misses 71231 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
-system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 42183 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 25870 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid 47226 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 1094 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 28772 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 211969 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 223649 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 246738339 # ITB inst accesses
-system.cpu0.itb.hits 246672238 # DTB hits
-system.cpu0.itb.misses 66101 # DTB misses
-system.cpu0.itb.accesses 246738339 # DTB accesses
-system.cpu0.numCycles 1042581150 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 264653532 # ITB inst accesses
+system.cpu0.itb.hits 264582301 # DTB hits
+system.cpu0.itb.misses 71231 # DTB misses
+system.cpu0.itb.accesses 264653532 # DTB accesses
+system.cpu0.numCycles 1106984671 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 455270721 # Number of instructions committed
-system.cpu0.committedOps 534899361 # Number of ops (including micro ops) committed
-system.cpu0.discardedOps 47095692 # Number of ops (including micro ops) which were discarded before commit
-system.cpu0.numFetchSuspends 4288 # Number of times Execute suspended instruction fetching
-system.cpu0.quiesceCycles 93950410811 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.cpi 2.290025 # CPI: cycles per instruction
-system.cpu0.ipc 0.436677 # IPC: instructions per cycle
+system.cpu0.committedInsts 488099503 # Number of instructions committed
+system.cpu0.committedOps 574418730 # Number of ops (including micro ops) committed
+system.cpu0.discardedOps 50785821 # Number of ops (including micro ops) which were discarded before commit
+system.cpu0.numFetchSuspends 5453 # Number of times Execute suspended instruction fetching
+system.cpu0.quiesceCycles 93802885102 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.cpi 2.267949 # CPI: cycles per instruction
+system.cpu0.ipc 0.440927 # IPC: instructions per cycle
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 13221 # number of quiesce instructions executed
-system.cpu0.tickCycles 736979138 # Number of cycles that the object actually ticked
-system.cpu0.idleCycles 305602012 # Total number of cycles that the object has spent stopped
-system.cpu0.dcache.tags.replacements 5679788 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 503.382728 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 157129733 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 5680300 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 27.662224 # Average number of references to valid blocks.
+system.cpu0.kern.inst.quiesce 5643 # number of quiesce instructions executed
+system.cpu0.tickCycles 789747765 # Number of cycles that the object actually ticked
+system.cpu0.idleCycles 317236906 # Total number of cycles that the object has spent stopped
+system.cpu0.dcache.tags.replacements 6140209 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 501.783411 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 169967706 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 6140721 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 27.678787 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 7690769000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 503.382728 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.983169 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.983169 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 501.783411 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data 0.980046 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total 0.980046 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 439 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 14 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0 153 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1 346 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 334387337 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 334387337 # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data 80268736 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 80268736 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 72233903 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 72233903 # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data 277349 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total 277349 # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data 251788 # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total 251788 # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1785654 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 1785654 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1744754 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 1744754 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 152502639 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 152502639 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 152779988 # number of overall hits
-system.cpu0.dcache.overall_hits::total 152779988 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 3412741 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 3412741 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 2489296 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 2489296 # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data 686937 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total 686937 # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data 801634 # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total 801634 # number of WriteLineReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 154902 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 154902 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data 194385 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 194385 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 5902037 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 5902037 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 6588974 # number of overall misses
-system.cpu0.dcache.overall_misses::total 6588974 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 58848858500 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 58848858500 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 63605542500 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 63605542500 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 48599001500 # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::total 48599001500 # number of WriteLineReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2502004000 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total 2502004000 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5451875000 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total 5451875000 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 6380500 # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total 6380500 # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 122454401000 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 122454401000 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 122454401000 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 122454401000 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 83681477 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 83681477 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 74723199 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 74723199 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 964286 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total 964286 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1053422 # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::total 1053422 # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1940556 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 1940556 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1939139 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 1939139 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 158404676 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 158404676 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 159368962 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 159368962 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.040783 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.040783 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.033314 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.033314 # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.712379 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total 0.712379 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.760981 # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::total 0.760981 # miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.079824 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.079824 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.100243 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total 0.100243 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.037259 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.037259 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.041344 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.041344 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17243.868931 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 17243.868931 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25551.618811 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 25551.618811 # average WriteReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 60624.925465 # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 60624.925465 # average WriteLineReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16152.173632 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16152.173632 # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28046.788590 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28046.788590 # average StoreCondReq miss latency
+system.cpu0.dcache.tags.tag_accesses 361643482 # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses 361643482 # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data 86800691 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 86800691 # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data 78258675 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 78258675 # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data 268918 # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total 268918 # number of SoftPFReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu0.data 127943 # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::total 127943 # number of WriteLineReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1971519 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total 1971519 # number of LoadLockedReq hits
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system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
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system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
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+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 27069.479384 # average SoftPFReq mshr miss latency
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system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
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-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18631.349667 # average overall mshr miss latency
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system.cpu0.icache.tags.warmup_cycle 33055106000 # Cycle when the warmup percentage was hit.
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system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 141746.678392 # average overall mshr uncacheable latency
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-system.cpu0.l2cache.demand_mshr_miss_rate::total 0.136913 # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.022671 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.049440 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.078878 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.263805 # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.236376 # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.236376 # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.078301 # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.078301 # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.270406 # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.270406 # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.746562 # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.746562 # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.024128 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.052279 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.078301 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.262462 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total 0.138559 # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.024128 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.052279 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.078301 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.262462 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total 0.189379 # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 37816.241730 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 39677.704070 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 38593.949643 # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59689.287295 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 59689.287295 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 29753.284535 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 29753.284535 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19514.559909 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19514.559909 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 782714.142857 # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 782714.142857 # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 55350.794047 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 55350.794047 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 32787.400786 # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32787.400786 # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 34527.480263 # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 34527.480263 # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 69680.907566 # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69680.907566 # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 37816.241730 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 39677.704070 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 32787.400786 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 39107.955826 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 36823.924881 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 37816.241730 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 39677.704070 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 32787.400786 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 39107.955826 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59689.287295 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 43158.674848 # average overall mshr miss latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total 0.193923 # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 51149.320787 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 59453.022795 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 54608.053996 # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 61741.289726 # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 61741.289726 # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 29925.451776 # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 29925.451776 # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19653.868363 # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19653.868363 # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 557499.727273 # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 557499.727273 # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57548.640546 # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57548.640546 # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 32489.756980 # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32489.756980 # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 39651.911728 # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 39651.911728 # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 68676.397845 # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 68676.397845 # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 51149.320787 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 59453.022795 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 32489.756980 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 43414.679931 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 39758.098096 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 51149.320787 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 59453.022795 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 32489.756980 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 43414.679931 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 61741.289726 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46034.137306 # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182530.348754 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 152314.071899 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 180475.390613 # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 180475.390613 # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167006.529232 # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 141191.713035 # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164452.679019 # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 164452.679019 # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 181512.386963 # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 159973.863196 # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 165693.017191 # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 145649.104605 # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.toL2Bus.snoop_filter.tot_requests 31336515 # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16003499 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2764 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops 2238925 # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2238443 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 482 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.trans_dist::ReadReq 888197 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp 14329408 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq 31554 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp 31553 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackDirty 5463883 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackClean 11447979 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict 3030252 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq 1046563 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq 472775 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 352055 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp 529438 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 72 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 135 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq 1230630 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp 1206068 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9550052 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4850843 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq 854414 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateResp 799200 # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 28754250 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18474160 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 377323 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1153011 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total 48758744 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1225720896 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 689935275 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1439168 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4373560 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total 1921468899 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops 7541383 # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples 23989921 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean 0.106643 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev 0.308724 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_filter.tot_requests 32897508 # Total number of requests made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16815136 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2581 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.snoop_filter.tot_snoops 2403341 # Total number of snoops made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2402836 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 505 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.trans_dist::ReadReq 933618 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp 15066373 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq 15977 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp 15976 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackDirty 5804347 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackClean 11960956 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict 3276888 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq 1153420 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq 478642 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 376774 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp 550943 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 90 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 166 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq 1307095 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp 1283776 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9846192 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5335526 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq 825564 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateResp 772295 # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 29642681 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19817496 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 405752 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1239273 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total 51105202 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1263627520 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 749575419 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1544024 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4686408 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total 2019433371 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops 8071773 # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples 25329179 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean 0.108588 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev 0.311185 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0 21432051 89.34% 89.34% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1 2557388 10.66% 100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2 482 0.00% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0 22579246 89.14% 89.14% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1 2749428 10.85% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2 505 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total 23989921 # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy 31215182485 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total 25329179 # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy 32745453976 # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy 206081920 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy 192728655 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy 14406948660 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy 14851397186 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy 8156637515 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy 8851946898 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy 197502349 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy 212824349 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy 606443243 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy 653582276 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu1.branchPred.lookups 134798362 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 95816419 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 6051956 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 100961028 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 73848042 # Number of BTB hits
+system.cpu1.branchPred.lookups 143060728 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 103431257 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 6108949 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 108043566 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 80039888 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 73.145097 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 15861028 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 1023147 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 74.081124 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 15973583 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 1078136 # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.dtb.walker.walks 282723 # Table walker walks requested
-system.cpu1.dtb.walker.walksLong 282723 # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10766 # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 86594 # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walkWaitTime::samples 282723 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0 282723 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total 282723 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples 97360 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 23363.804437 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 21328.911362 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 20585.456118 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535 96095 98.70% 98.70% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-131071 182 0.19% 98.89% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-196607 912 0.94% 99.82% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-262143 29 0.03% 99.85% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-327679 42 0.04% 99.90% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-393215 31 0.03% 99.93% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-458751 49 0.05% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::458752-524287 15 0.02% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walks 316205 # Table walker walks requested
+system.cpu1.dtb.walker.walksLong 316205 # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 13111 # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 102055 # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walkWaitTime::samples 316205 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0 316205 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total 316205 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples 115166 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 23006.933470 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 21361.362420 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 17841.956140 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535 114056 99.04% 99.04% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071 145 0.13% 99.16% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607 815 0.71% 99.87% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143 40 0.03% 99.90% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679 38 0.03% 99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215 18 0.02% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-458751 32 0.03% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::458752-524287 14 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::524288-589823 5 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total 97360 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total 115166 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 1788277352 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0 1788277352 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 1788277352 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K 86594 88.94% 88.94% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M 10766 11.06% 100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total 97360 # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 282723 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkPageSizes::4K 102056 88.62% 88.62% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M 13111 11.38% 100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total 115167 # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 316205 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 282723 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 97360 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 316205 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 115167 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 97360 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total 380083 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 115167 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total 431372 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 88221750 # DTB read hits
-system.cpu1.dtb.read_misses 234611 # DTB read misses
-system.cpu1.dtb.write_hits 76459163 # DTB write hits
-system.cpu1.dtb.write_misses 48112 # DTB write misses
-system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
+system.cpu1.dtb.read_hits 90416501 # DTB read hits
+system.cpu1.dtb.read_misses 263668 # DTB read misses
+system.cpu1.dtb.write_hits 78865175 # DTB write hits
+system.cpu1.dtb.write_misses 52537 # DTB write misses
+system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 42183 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 39871 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 1240 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 8073 # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_tlb_mva_asid 47226 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 1094 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 39779 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 1900 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 9673 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 11018 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 88456361 # DTB read accesses
-system.cpu1.dtb.write_accesses 76507275 # DTB write accesses
+system.cpu1.dtb.perms_faults 11862 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 90680169 # DTB read accesses
+system.cpu1.dtb.write_accesses 78917712 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 164680913 # DTB hits
-system.cpu1.dtb.misses 282723 # DTB misses
-system.cpu1.dtb.accesses 164963636 # DTB accesses
+system.cpu1.dtb.hits 169281676 # DTB hits
+system.cpu1.dtb.misses 316205 # DTB misses
+system.cpu1.dtb.accesses 169597881 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.walker.walks 64693 # Table walker walks requested
-system.cpu1.itb.walker.walksLong 64693 # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2 526 # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3 55247 # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples 64693 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0 64693 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total 64693 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples 55773 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 26679.495455 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 23706.173761 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 24561.580376 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-65535 54531 97.77% 97.77% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-131071 9 0.02% 97.79% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-196607 1101 1.97% 99.76% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-262143 35 0.06% 99.83% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-327679 52 0.09% 99.92% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-393215 31 0.06% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-458751 6 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::458752-524287 6 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walks 61623 # Table walker walks requested
+system.cpu1.itb.walker.walksLong 61623 # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2 682 # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3 51951 # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples 61623 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0 61623 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total 61623 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples 52633 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 26809.463644 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 23734.871548 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 24762.364644 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-65535 51446 97.74% 97.74% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-131071 9 0.02% 97.76% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-196607 1035 1.97% 99.73% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-262143 54 0.10% 99.83% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-327679 44 0.08% 99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-393215 33 0.06% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-458751 9 0.02% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total 55773 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total 52633 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 1787261852 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 1787261852 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 1787261852 # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K 55247 99.06% 99.06% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M 526 0.94% 100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total 55773 # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::4K 51951 98.70% 98.70% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M 682 1.30% 100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total 52633 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 64693 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total 64693 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 61623 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total 61623 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55773 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55773 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total 120466 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 241355329 # ITB inst hits
-system.cpu1.itb.inst_misses 64693 # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 52633 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total 52633 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total 114256 # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits 255703249 # ITB inst hits
+system.cpu1.itb.inst_misses 61623 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
-system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 42183 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 28782 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid 47226 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 1094 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 28254 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 214506 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 225386 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 241420022 # ITB inst accesses
-system.cpu1.itb.hits 241355329 # DTB hits
-system.cpu1.itb.misses 64693 # DTB misses
-system.cpu1.itb.accesses 241420022 # DTB accesses
-system.cpu1.numCycles 943222184 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 255764872 # ITB inst accesses
+system.cpu1.itb.hits 255703249 # DTB hits
+system.cpu1.itb.misses 61623 # DTB misses
+system.cpu1.itb.accesses 255764872 # DTB accesses
+system.cpu1.numCycles 1013399126 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 444939071 # Number of instructions committed
-system.cpu1.committedOps 523893431 # Number of ops (including micro ops) committed
-system.cpu1.discardedOps 46484386 # Number of ops (including micro ops) which were discarded before commit
-system.cpu1.numFetchSuspends 5697 # Number of times Execute suspended instruction fetching
-system.cpu1.quiesceCycles 94049904755 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.cpi 2.119891 # CPI: cycles per instruction
-system.cpu1.ipc 0.471722 # IPC: instructions per cycle
+system.cpu1.committedInsts 463476016 # Number of instructions committed
+system.cpu1.committedOps 544549672 # Number of ops (including micro ops) committed
+system.cpu1.discardedOps 51973590 # Number of ops (including micro ops) which were discarded before commit
+system.cpu1.numFetchSuspends 4681 # Number of times Execute suspended instruction fetching
+system.cpu1.quiesceCycles 93896343891 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.cpi 2.186519 # CPI: cycles per instruction
+system.cpu1.ipc 0.457348 # IPC: instructions per cycle
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 5760 # number of quiesce instructions executed
-system.cpu1.tickCycles 722277565 # Number of cycles that the object actually ticked
-system.cpu1.idleCycles 220944619 # Total number of cycles that the object has spent stopped
-system.cpu1.dcache.tags.replacements 5315264 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 430.485039 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 156623393 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 5315774 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 29.463892 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 8391021559000 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 430.485039 # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data 0.840791 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total 0.840791 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1 221 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2 267 # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses 332053228 # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses 332053228 # Number of data accesses
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-system.cpu1.dcache.ReadReq_hits::total 80890555 # number of ReadReq hits
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-system.cpu1.dcache.SoftPFReq_hits::total 230003 # number of SoftPFReq hits
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-system.cpu1.dcache.ReadReq_misses::total 3470383 # number of ReadReq misses
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-system.cpu1.dcache.demand_misses::total 5726848 # number of demand (read+write) misses
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-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5779500 # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5779500 # number of StoreCondFailReq miss cycles
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-system.cpu1.dcache.SoftPFReq_accesses::total 859040 # number of SoftPFReq accesses(hits+misses)
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-system.cpu1.dcache.overall_accesses::total 158871827 # number of overall (read+write) accesses
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-system.cpu1.dcache.ReadReq_miss_rate::total 0.041137 # miss rate for ReadReq accesses
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-system.cpu1.dcache.SoftPFReq_miss_rate::total 0.732256 # miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.865217 # miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::total 0.865217 # miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.091162 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.091162 # miss rate for LoadLockedReq accesses
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-system.cpu1.dcache.StoreCondReq_miss_rate::total 0.101372 # miss rate for StoreCondReq accesses
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-system.cpu1.dcache.demand_miss_rate::total 0.036243 # miss rate for demand accesses
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-system.cpu1.dcache.overall_miss_rate::total 0.040006 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16623.959517 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 16623.959517 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22230.110372 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 22230.110372 # average WriteReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 37723.815921 # average WriteLineReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 37723.815921 # average WriteLineReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16651.322884 # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16651.322884 # average LoadLockedReq miss latency
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-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27895.298372 # average StoreCondReq miss latency
+system.cpu1.kern.inst.quiesce 13591 # number of quiesce instructions executed
+system.cpu1.tickCycles 759435347 # Number of cycles that the object actually ticked
+system.cpu1.idleCycles 253963779 # Total number of cycles that the object has spent stopped
+system.cpu1.dcache.tags.replacements 5640902 # number of replacements
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+system.cpu1.dcache.tags.total_refs 160682361 # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs 5641413 # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs 28.482645 # Average number of references to valid blocks.
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+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16883.295079 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 16883.295079 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 23244.765692 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 23244.765692 # average WriteReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 45191.877418 # average WriteLineReq miss latency
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system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
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-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16968.993696 # average overall miss latency
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system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 5315289 # number of writebacks
-system.cpu1.dcache.writebacks::total 5315289 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 392143 # number of ReadReq MSHR hits
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-system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 454787 # number of WriteLineReq MSHR misses
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-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 198802 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total 198802 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 4414209 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 4414209 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data 5042943 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 5042943 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 6731 # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total 6731 # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 7202 # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total 7202 # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 13933 # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total 13933 # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 46218671000 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 46218671000 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 29907223500 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 29907223500 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14916352500 # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14916352500 # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 16698306500 # number of WriteLineReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 16698306500 # number of WriteLineReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1935752000 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1935752000 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5344630000 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5344630000 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 5479500 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 5479500 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 76125894500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 76125894500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 91042247000 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 91042247000 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 839317500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 839317500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1016449500 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1016449500 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1855767000 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1855767000 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036489 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036489 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018139 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018139 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.731903 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.731903 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.865103 # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.865103 # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.068448 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.068448 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.101350 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.101350 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027936 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.027936 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031742 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.031742 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15014.641808 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15014.641808 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22386.165772 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22386.165772 # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23724.424796 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23724.424796 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 36716.763012 # average WriteLineReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 36716.763012 # average WriteLineReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14405.810691 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14405.810691 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26884.186276 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26884.186276 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks 5640935 # number of writebacks
+system.cpu1.dcache.writebacks::total 5640935 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 429416 # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total 429416 # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1043359 # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total 1043359 # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 74 # number of WriteLineReq MSHR hits
+system.cpu1.dcache.WriteLineReq_mshr_hits::total 74 # number of WriteLineReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 42170 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total 42170 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 72 # number of StoreCondReq MSHR hits
+system.cpu1.dcache.StoreCondReq_mshr_hits::total 72 # number of StoreCondReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data 1472775 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total 1472775 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data 1472775 # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total 1472775 # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3155827 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total 3155827 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1480375 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total 1480375 # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 738082 # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total 738082 # number of SoftPFReq MSHR misses
+system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 486914 # number of WriteLineReq MSHR misses
+system.cpu1.dcache.WriteLineReq_mshr_misses::total 486914 # number of WriteLineReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 120140 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 120140 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 206366 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total 206366 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data 4636202 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total 4636202 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data 5374284 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total 5374284 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 23242 # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total 23242 # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 22236 # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total 22236 # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 45478 # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total 45478 # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 47412877500 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 47412877500 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 34746994000 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 34746994000 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 19660408500 # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 19660408500 # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 21514132500 # number of WriteLineReq MSHR miss cycles
+system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 21514132500 # number of WriteLineReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1774236500 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1774236500 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5529988500 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5529988500 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 6729000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 6729000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 82159871500 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 82159871500 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 101820280000 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 101820280000 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4292810500 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4292810500 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 4172773000 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 4172773000 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 8465583500 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 8465583500 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036575 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036575 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.019539 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.019539 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.741090 # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.741090 # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.711473 # mshr miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.711473 # mshr miss rate for WriteLineReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058217 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.058217 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100070 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100070 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028610 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.028610 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032962 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.032962 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15023.915284 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15023.915284 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23471.751414 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23471.751414 # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 26637.160234 # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 26637.160234 # average SoftPFReq mshr miss latency
+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 44184.666081 # average WriteLineReq mshr miss latency
+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 44184.666081 # average WriteLineReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14768.074746 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14768.074746 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26796.994175 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26796.994175 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17245.647975 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17245.647975 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18053.396003 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18053.396003 # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 124694.324766 # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 124694.324766 # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 141134.337684 # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 141134.337684 # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 133192.205555 # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 133192.205555 # average overall mshr uncacheable latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17721.374414 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17721.374414 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18945.831668 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18945.831668 # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 184700.563635 # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184700.563635 # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 187658.436769 # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 187658.436769 # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 186146.785259 # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 186146.785259 # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements 9419212 # number of replacements
-system.cpu1.icache.tags.tagsinuse 506.776997 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 231714815 # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs 9419724 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 24.598896 # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle 8379179578000 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst 506.776997 # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst 0.989799 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total 0.989799 # Average percentage of cache occupancy
+system.cpu1.icache.tags.replacements 9253909 # number of replacements
+system.cpu1.icache.tags.tagsinuse 506.772073 # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs 246217857 # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs 9254421 # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs 26.605431 # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle 8381293063000 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst 506.772073 # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst 0.989789 # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total 0.989789 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1 220 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2 98 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1 353 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2 60 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses 491688802 # Number of tag accesses
-system.cpu1.icache.tags.data_accesses 491688802 # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst 231714815 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 231714815 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 231714815 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 231714815 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 231714815 # number of overall hits
-system.cpu1.icache.overall_hits::total 231714815 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 9419724 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 9419724 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 9419724 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 9419724 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 9419724 # number of overall misses
-system.cpu1.icache.overall_misses::total 9419724 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 96182532500 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total 96182532500 # number of ReadReq miss cycles
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-system.cpu1.icache.ReadReq_avg_miss_latency::total 10210.759094 # average ReadReq miss latency
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-system.cpu1.icache.demand_avg_miss_latency::total 10210.759094 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10210.759094 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 10210.759094 # average overall miss latency
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+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10569.994463 # average overall miss latency
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system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu1.icache.writebacks::total 9419212 # number of writebacks
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system.cpu1.icache.ReadReq_mshr_uncacheable::total 93 # number of ReadReq MSHR uncacheable
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-system.cpu1.icache.demand_mshr_miss_latency::total 91472670500 # number of demand (read+write) MSHR miss cycles
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system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 13081000 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total 13081000 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.039064 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.039064 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.039064 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total 0.039064 # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.039064 # mshr miss rate for overall accesses
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-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9710.759094 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9710.759094 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9710.759094 # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 9710.759094 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9710.759094 # average overall mshr miss latency
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+system.cpu1.icache.demand_mshr_miss_rate::total 0.036225 # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.036225 # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total 0.036225 # mshr miss rate for overall accesses
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+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10069.994517 # average ReadReq mshr miss latency
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+system.cpu1.icache.demand_avg_mshr_miss_latency::total 10069.994517 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10069.994517 # average overall mshr miss latency
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system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 140655.913978 # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 140655.913978 # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 140655.913978 # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 140655.913978 # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.l2cache.prefetcher.num_hwpf_issued 7256046 # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified 7256259 # number of prefetch candidates identified
-system.cpu1.l2cache.prefetcher.pfBufferHit 183 # number of redundant prefetches already in prefetch queue
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+system.cpu1.l2cache.prefetcher.pfIdentified 7973767 # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.pfBufferHit 1132 # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage 925773 # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.replacements 2304751 # number of replacements
-system.cpu1.l2cache.tags.tagsinuse 13454.881705 # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs 23669466 # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs 2320587 # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs 10.199775 # Average number of references to valid blocks.
-system.cpu1.l2cache.tags.warmup_cycle 9853632359500 # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks 12618.151234 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 61.761915 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 57.964405 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 717.004151 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks 0.770151 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003770 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003538 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.043762 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total 0.821221 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1043 # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023 71 # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14722 # Occupied blocks per task id
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-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 319 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 650 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 71 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 45 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 24 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 391 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5507 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8143 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 659 # Occupied blocks per task id
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-system.cpu1.l2cache.tags.tag_accesses 496871809 # Number of tag accesses
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-system.cpu1.l2cache.WritebackDirty_hits::total 3295376 # number of WritebackDirty hits
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-system.cpu1.l2cache.WritebackClean_hits::total 11437109 # number of WritebackClean hits
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-system.cpu1.l2cache.UpgradeReq_hits::total 567 # number of UpgradeReq hits
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-system.cpu1.l2cache.ReadCleanReq_hits::total 8732847 # number of ReadCleanReq hits
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-system.cpu1.l2cache.ReadSharedReq_hits::total 2873391 # number of ReadSharedReq hits
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-system.cpu1.l2cache.InvalidateReq_hits::total 191011 # number of InvalidateReq hits
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-system.cpu1.l2cache.UpgradeReq_misses::total 222957 # number of UpgradeReq misses
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-system.cpu1.l2cache.overall_misses::cpu1.inst 686877 # number of overall misses
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-system.cpu1.l2cache.UpgradeReq_miss_latency::total 3348912000 # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1915512500 # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1915512500 # number of SCUpgradeReq miss cycles
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system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12337000 # number of ReadReq MSHR uncacheable cycles
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system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12337000 # number of overall MSHR uncacheable cycles
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-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.027630 # mshr miss rate for ReadReq accesses
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system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
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system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
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-system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.578401 # mshr miss rate for InvalidateReq accesses
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-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.244056 # mshr miss rate for demand accesses
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-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.048333 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.072919 # mshr miss rate for overall accesses
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system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
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-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 45791.982922 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 42291.337811 # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 53304.865332 # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 53304.865332 # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31396.571949 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31396.571949 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19362.414921 # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19362.414921 # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 998200 # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 998200 # average SCUpgradeFailReq mshr miss latency
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-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 47276.636115 # average ReadExReq mshr miss latency
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-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29777.775756 # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 33589.328536 # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33589.328536 # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 49894.194371 # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 49894.194371 # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 39824.768112 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 45791.982922 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29777.775756 # average overall mshr miss latency
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+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 30690.875696 # average UpgradeReq mshr miss latency
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system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 132655.913978 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116683.405140 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 116901.084408 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 133624.618162 # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 133624.618162 # average WriteReq mshr uncacheable latency
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system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132655.913978 # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 125440.357425 # average overall mshr uncacheable latency
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+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 178295.209673 # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.toL2Bus.snoop_filter.tot_requests 30305906 # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests 15477606 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 2013 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops 2090955 # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2090626 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 329 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.trans_dist::ReadReq 826390 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp 14176907 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq 7202 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp 7202 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackDirty 4434109 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackClean 11439122 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict 2886028 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq 940232 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq 438079 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 353355 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp 486110 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 75 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 135 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq 1143505 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp 1120857 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq 9419724 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4894979 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateReq 500608 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateResp 453070 # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 28258846 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17165188 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 367696 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1190168 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total 46981898 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1205697856 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 663528133 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1395656 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4510728 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total 1875132373 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops 6705692 # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples 22548909 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean 0.107052 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev 0.309227 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_filter.tot_requests 30687781 # Total number of requests made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_requests 15695228 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 2622 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.snoop_filter.tot_snoops 2305562 # Total number of snoops made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2305078 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 484 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.trans_dist::ReadReq 905031 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp 14265709 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq 22236 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp 22236 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackDirty 4974934 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackClean 11314728 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict 3212624 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq 1143576 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq 456570 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 371810 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 515155 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 96 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 166 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq 1270102 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp 1247161 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq 9254432 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq 5086529 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateReq 540215 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateResp 484636 # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 27762958 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18273152 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 349398 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1329953 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total 47715461 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1184539712 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 703787179 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1323840 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 5057400 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total 1894708131 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops 7537959 # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples 23658040 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean 0.112405 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.315929 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0 20135326 89.30% 89.30% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1 2413254 10.70% 100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2 329 0.00% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0 20999234 88.76% 88.76% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1 2658322 11.24% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2 484 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total 22548909 # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy 30147553476 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total 23658040 # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy 30538190977 # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy 176219861 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy 182787124 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy 14133264904 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy 13885672200 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy 7885730738 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy 8385983653 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy 193298381 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy 183975884 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy 626482687 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy 697921212 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 40387 # Transaction distribution
-system.iobus.trans_dist::ReadResp 40387 # Transaction distribution
+system.iobus.trans_dist::ReadReq 40434 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40434 # Transaction distribution
system.iobus.trans_dist::WriteReq 136979 # Transaction distribution
system.iobus.trans_dist::WriteResp 136979 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47868 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47874 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29756 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 122958 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231694 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 231694 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 122964 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231782 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 231782 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 354732 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47888 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total 354826 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47894 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17674 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 155996 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355128 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 7355128 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 156002 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355480 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 7355480 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 7513210 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 47188500 # Layer occupancy (ticks)
+system.iobus.pkt_size::total 7513568 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 47273505 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 327500 # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy 324000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer4.occupancy 9000 # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy 8500 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks)
+system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 15000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 26264003 # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy 26273501 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer24.occupancy 36399000 # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy 36398000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 568799211 # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy 568842992 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 92966000 # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy 92972000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer3.occupancy 148134000 # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy 148222000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.replacements 115828 # number of replacements
-system.iocache.tags.tagsinuse 11.305227 # Cycle average of tags in use
+system.iocache.tags.replacements 115872 # number of replacements
+system.iocache.tags.tagsinuse 11.252872 # Cycle average of tags in use
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 115844 # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs 115888 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 9138950806000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet 3.834041 # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide 7.471186 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet 0.239628 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide 0.466949 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.706577 # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle 9138217056000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet 3.833219 # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide 7.419652 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet 0.239576 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide 0.463728 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.703304 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 1042980 # Number of tag accesses
-system.iocache.tags.data_accesses 1042980 # Number of data accesses
+system.iocache.tags.tag_accesses 1043376 # Number of tag accesses
+system.iocache.tags.data_accesses 1043376 # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide 8863 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 8900 # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide 8907 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 8944 # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide 8863 # number of demand (read+write) misses
-system.iocache.demand_misses::total 8903 # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide 8907 # number of demand (read+write) misses
+system.iocache.demand_misses::total 8947 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
-system.iocache.overall_misses::realview.ide 8863 # number of overall misses
-system.iocache.overall_misses::total 8903 # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet 5197000 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide 1710789963 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 1715986963 # number of ReadReq miss cycles
+system.iocache.overall_misses::realview.ide 8907 # number of overall misses
+system.iocache.overall_misses::total 8947 # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet 5277000 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide 1705079977 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 1710356977 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide 13562248248 # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total 13562248248 # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet 5566000 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide 1710789963 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 1716355963 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet 5566000 # number of overall miss cycles
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+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.226122 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.236223 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.230886 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.573251 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.549054 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.562606 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.322586 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.397560 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.092611 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.213527 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.452612 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.275687 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.341605 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.081075 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.162635 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.522701 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total 0.239318 # mshr miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.745352 # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.563953 # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::total 0.681658 # mshr miss rate for InvalidateReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.322586 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.397560 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst 0.092611 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data 0.267207 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.452612 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.275687 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.341605 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.081075 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.213268 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.522701 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.258011 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.322586 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.397560 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.092611 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data 0.267207 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.452612 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.275687 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.341605 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.081075 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.213268 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.522701 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.258011 # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70758.339917 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70359.930821 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70566.394621 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 73641.009191 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73548.748351 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 73596.483261 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 127912.406083 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 128004.597362 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 127951.987161 # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 130627.550522 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 131006.999696 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 125916.416541 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 131423.037819 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 162111.922712 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 131497.893462 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 134389.597094 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 125525.953290 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 134145.307792 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 167680.055773 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 150265.373892 # average ReadSharedReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 70087.808865 # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69270.608839 # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::total 69850.417852 # average InvalidateReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 130627.550522 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 131006.999696 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 125916.416541 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 130299.138826 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 162111.922712 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 131497.893462 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 134389.597094 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125525.953290 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 132073.816824 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 167680.055773 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 147452.086842 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 130627.550522 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 131006.999696 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 125916.416541 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 130299.138826 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 162111.922712 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 131497.893462 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 134389.597094 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125525.953290 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 132073.816824 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 167680.055773 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 147452.086842 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 164525.170581 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 148992.246785 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 111650.537634 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 98704.194085 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 129944.590793 # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 163469.575571 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 116608.102749 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 154761.116604 # average WriteReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 158707.724699 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 130545.300866 # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 147439.379444 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 163149.942166 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 156581.535643 # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 164002.261932 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 148193.566448 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 111650.537634 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 107960.094609 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 137341.128933 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 160879.796728 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 138261.266457 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 91274 # Transaction distribution
-system.membus.trans_dist::ReadResp 916539 # Transaction distribution
-system.membus.trans_dist::WriteReq 38755 # Transaction distribution
-system.membus.trans_dist::WriteResp 38755 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 1197090 # Transaction distribution
-system.membus.trans_dist::CleanEvict 262945 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 440993 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 308067 # Transaction distribution
+system.membus.trans_dist::ReadReq 90728 # Transaction distribution
+system.membus.trans_dist::ReadResp 1177835 # Transaction distribution
+system.membus.trans_dist::WriteReq 38212 # Transaction distribution
+system.membus.trans_dist::WriteResp 38212 # Transaction distribution
+system.membus.trans_dist::WritebackDirty 1451911 # Transaction distribution
+system.membus.trans_dist::CleanEvict 312799 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 438732 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 328709 # Transaction distribution
system.membus.trans_dist::UpgradeResp 23 # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution
-system.membus.trans_dist::ReadExReq 144406 # Transaction distribution
-system.membus.trans_dist::ReadExResp 127298 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 825265 # Transaction distribution
-system.membus.trans_dist::InvalidateReq 666679 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122958 # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution
+system.membus.trans_dist::ReadExReq 166722 # Transaction distribution
+system.membus.trans_dist::ReadExResp 150087 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 1087107 # Transaction distribution
+system.membus.trans_dist::InvalidateReq 695373 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122964 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27076 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4666640 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 4816726 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238694 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 238694 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 5055420 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155996 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24892 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5587054 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 5734962 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238554 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 238554 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 5973516 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156002 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 54152 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 133490240 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 133701712 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7291456 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 7291456 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 140993168 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 609728 # Total snoops (count)
-system.membus.snoop_fanout::samples 3975535 # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 49784 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 168012608 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 168219718 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7276864 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 7276864 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 175496582 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 622390 # Total snoops (count)
+system.membus.snoop_fanout::samples 4610336 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 3975535 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 4610336 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 3975535 # Request fanout histogram
-system.membus.reqLayer0.occupancy 110272997 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 4610336 # Request fanout histogram
+system.membus.reqLayer0.occupancy 110366494 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 33984 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 22907496 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 20951999 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 8443265855 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 10147074149 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 5364054651 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 6858565377 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 45386996 # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy 45617493 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests 12590063 # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests 6816351 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests 2112405 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops 136080 # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops 123352 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops 12728 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq 91276 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 4889046 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 38755 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 38755 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty 4006843 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 3033326 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 740212 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 393009 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 1133221 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq 135 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp 135 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 301958 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 301958 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 4804997 # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq 940884 # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateResp 833900 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10292862 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8190937 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 18483799 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 255537947 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 200300853 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 455838800 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 3066288 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 8826957 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 0.357421 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.482240 # Request fanout histogram
+system.toL2Bus.snoop_filter.tot_requests 13817515 # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests 7477037 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests 2215935 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops 187202 # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops 169247 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops 17955 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.trans_dist::ReadReq 90730 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 5393978 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 38212 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 38212 # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty 4613586 # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict 3368394 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 769711 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 415575 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 1185286 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq 166 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp 166 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 331620 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 331620 # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq 5310492 # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq 975909 # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateResp 868925 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10817825 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 9492092 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 20309917 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 274107435 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 237950875 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 512058310 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 3424368 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 9784683 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 0.340448 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.477717 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 5684742 64.40% 64.40% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 3129487 35.45% 99.86% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 12728 0.14% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 6471464 66.14% 66.14% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 3295264 33.68% 99.82% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 17955 0.18% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 8826957 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 9586281743 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 9784683 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 10614903907 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 2585661 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy 2624417 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 4723415116 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 5004390482 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 4064152578 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 4630478453 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4\r
[ 0.000000] NR_IRQS:64 nr_irqs:64 0\r
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).\r
-[ 0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns\r
+[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns\r
[ 0.000028] Console: colour dummy device 80x25\r
[ 0.000031] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
-[ 0.000033] pid_max: default: 32768 minimum: 301\r
-[ 0.000046] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000047] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000219] hw perfevents: no hardware support available\r
-[ 0.060056] CPU1: Booted secondary processor\r
+[ 0.000032] pid_max: default: 32768 minimum: 301\r
+[ 0.000045] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
+[ 0.000046] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
+[ 0.000199] hw perfevents: no hardware support available\r
+[ 0.060051] CPU1: Booted secondary processor\r
[ 1.080085] CPU2: failed to come online\r
-[ 2.100162] CPU3: failed to come online\r
-[ 2.100165] Brought up 2 CPUs\r
-[ 2.100166] SMP: Total of 2 processors activated.\r
-[ 2.100236] devtmpfs: initialized\r
-[ 2.100755] atomic64_test: passed\r
-[ 2.100809] regulator-dummy: no parameters\r
-[ 2.101182] NET: Registered protocol family 16\r
-[ 2.101326] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
-[ 2.101335] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
-[ 2.102656] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
-[ 2.102660] Serial: AMBA PL011 UART driver\r
-[ 2.102871] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
-[ 2.102913] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
-[ 2.103488] console [ttyAMA0] enabled\r
-[ 2.103636] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
-[ 2.103696] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
-[ 2.103756] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
-[ 2.103816] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
-[ 2.140419] 3V3: 3300 mV \r
-[ 2.140469] vgaarb: loaded\r
-[ 2.140516] SCSI subsystem initialized\r
-[ 2.140554] libata version 3.00 loaded.\r
-[ 2.140615] usbcore: registered new interface driver usbfs\r
-[ 2.140634] usbcore: registered new interface driver hub\r
-[ 2.140657] usbcore: registered new device driver usb\r
-[ 2.140684] pps_core: LinuxPPS API ver. 1 registered\r
-[ 2.140693] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
-[ 2.140713] PTP clock support registered\r
-[ 2.140852] Switched to clocksource arch_sys_counter\r
-[ 2.141883] NET: Registered protocol family 2\r
-[ 2.141966] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
-[ 2.141983] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
-[ 2.142000] TCP: Hash tables configured (established 2048 bind 2048)\r
-[ 2.142036] TCP: reno registered\r
-[ 2.142043] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 2.142056] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 2.142093] NET: Registered protocol family 1\r
-[ 2.142147] RPC: Registered named UNIX socket transport module.\r
-[ 2.142158] RPC: Registered udp transport module.\r
-[ 2.142166] RPC: Registered tcp transport module.\r
-[ 2.142175] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
-[ 2.142187] PCI: CLS 0 bytes, default 64\r
-[ 2.142348] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
-[ 2.142446] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
-[ 2.144602] fuse init (API version 7.23)\r
-[ 2.144721] msgmni has been set to 469\r
-[ 2.144831] io scheduler noop registered\r
-[ 2.144882] io scheduler cfq registered (default)\r
-[ 2.145442] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
-[ 2.145456] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
-[ 2.145468] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
-[ 2.145481] pci_bus 0000:00: root bus resource [bus 00-ff]\r
-[ 2.145491] pci_bus 0000:00: scanning bus\r
-[ 2.145502] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
-[ 2.145516] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
-[ 2.145531] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 2.145568] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
-[ 2.145580] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
-[ 2.145591] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
-[ 2.145601] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
-[ 2.145612] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
-[ 2.145623] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
-[ 2.145635] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 2.145670] pci_bus 0000:00: fixups for bus\r
-[ 2.145678] pci_bus 0000:00: bus scan returning with max=00\r
-[ 2.145690] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
-[ 2.145712] pci 0000:00:00.0: fixup irq: got 33\r
-[ 2.145720] pci 0000:00:00.0: assigning IRQ 33\r
-[ 2.145731] pci 0000:00:01.0: fixup irq: got 34\r
-[ 2.145740] pci 0000:00:01.0: assigning IRQ 34\r
-[ 2.145752] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
-[ 2.145765] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
-[ 2.145778] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
-[ 2.145791] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
-[ 2.145803] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
-[ 2.145814] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
-[ 2.145826] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
-[ 2.145838] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
-[ 2.146509] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
-[ 2.146789] ata_piix 0000:00:01.0: version 2.13\r
-[ 2.146800] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
-[ 2.146833] ata_piix 0000:00:01.0: enabling bus mastering\r
-[ 2.147105] scsi0 : ata_piix\r
-[ 2.147189] scsi1 : ata_piix\r
-[ 2.147233] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
-[ 2.147246] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
-[ 2.147373] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
-[ 2.147386] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
-[ 2.147401] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
-[ 2.147412] e1000 0000:00:00.0: enabling bus mastering\r
-[ 2.290899] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
-[ 2.290910] ata1.00: 2096640 sectors, multi 0: LBA \r
-[ 2.290939] ata1.00: configured for UDMA/33\r
-[ 2.291006] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
-[ 2.291132] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
-[ 2.291158] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
-[ 2.291199] sd 0:0:0:0: [sda] Write Protect is off\r
-[ 2.291208] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
-[ 2.291229] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
-[ 2.291366] sda: sda1\r
-[ 2.291489] sd 0:0:0:0: [sda] Attached SCSI disk\r
-[ 2.411161] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
-[ 2.411175] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
-[ 2.411196] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
-[ 2.411207] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
-[ 2.411229] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
-[ 2.411241] igb: Copyright (c) 2007-2014 Intel Corporation.\r
-[ 2.411314] usbcore: registered new interface driver usb-storage\r
-[ 2.411382] mousedev: PS/2 mouse device common for all mice\r
-[ 2.411554] usbcore: registered new interface driver usbhid\r
-[ 2.411564] usbhid: USB HID core driver\r
-[ 2.411599] TCP: cubic registered\r
-[ 2.411606] NET: Registered protocol family 17\r
-\0[ 2.412053] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
-[ 2.412104] devtmpfs: mounted\r
-[ 2.412177] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
+[ 2.100161] CPU3: failed to come online\r
+[ 2.100164] Brought up 2 CPUs\r
+[ 2.100165] SMP: Total of 2 processors activated.\r
+[ 2.100234] devtmpfs: initialized\r
+[ 2.100742] atomic64_test: passed\r
+[ 2.100794] regulator-dummy: no parameters\r
+[ 2.101157] NET: Registered protocol family 16\r
+[ 2.101296] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
+[ 2.101304] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
+[ 2.102113] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
+[ 2.102117] Serial: AMBA PL011 UART driver\r
+[ 2.102318] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
+[ 2.102358] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
+[ 2.102933] console [ttyAMA0] enabled\r
+[ 2.103072] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
+[ 2.103132] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
+[ 2.103192] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
+[ 2.103250] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
+[ 2.140336] 3V3: 3300 mV \r
+[ 2.140383] vgaarb: loaded\r
+[ 2.140429] SCSI subsystem initialized\r
+[ 2.140466] libata version 3.00 loaded.\r
+[ 2.140524] usbcore: registered new interface driver usbfs\r
+[ 2.140543] usbcore: registered new interface driver hub\r
+[ 2.140567] usbcore: registered new device driver usb\r
+[ 2.140593] pps_core: LinuxPPS API ver. 1 registered\r
+[ 2.140602] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
+[ 2.140621] PTP clock support registered\r
+[ 2.140762] Switched to clocksource arch_sys_counter\r
+[ 2.141783] NET: Registered protocol family 2\r
+[ 2.141863] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
+[ 2.141880] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
+[ 2.141897] TCP: Hash tables configured (established 2048 bind 2048)\r
+[ 2.141925] TCP: reno registered\r
+[ 2.141932] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
+[ 2.141945] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
+[ 2.141981] NET: Registered protocol family 1\r
+[ 2.142034] RPC: Registered named UNIX socket transport module.\r
+[ 2.142044] RPC: Registered udp transport module.\r
+[ 2.142052] RPC: Registered tcp transport module.\r
+[ 2.142061] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
+[ 2.142073] PCI: CLS 0 bytes, default 64\r
+[ 2.142235] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
+[ 2.142334] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
+[ 2.144468] fuse init (API version 7.23)\r
+[ 2.144588] msgmni has been set to 469\r
+[ 2.144697] io scheduler noop registered\r
+[ 2.144749] io scheduler cfq registered (default)\r
+[ 2.145214] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
+[ 2.145228] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
+[ 2.145239] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
+[ 2.145252] pci_bus 0000:00: root bus resource [bus 00-ff]\r
+[ 2.145262] pci_bus 0000:00: scanning bus\r
+[ 2.145274] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
+[ 2.145288] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
+[ 2.145302] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[ 2.145340] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
+[ 2.145352] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
+[ 2.145363] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
+[ 2.145373] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
+[ 2.145384] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
+[ 2.145395] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
+[ 2.145406] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[ 2.145441] pci_bus 0000:00: fixups for bus\r
+[ 2.145450] pci_bus 0000:00: bus scan returning with max=00\r
+[ 2.145462] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
+[ 2.145483] pci 0000:00:00.0: fixup irq: got 33\r
+[ 2.145492] pci 0000:00:00.0: assigning IRQ 33\r
+[ 2.145502] pci 0000:00:01.0: fixup irq: got 34\r
+[ 2.145511] pci 0000:00:01.0: assigning IRQ 34\r
+[ 2.145524] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
+[ 2.145538] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
+[ 2.145551] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
+[ 2.145564] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
+[ 2.145576] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
+[ 2.145587] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
+[ 2.145599] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
+[ 2.145610] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
+[ 2.146274] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
+[ 2.146553] ata_piix 0000:00:01.0: version 2.13\r
+[ 2.146565] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
+[ 2.146593] ata_piix 0000:00:01.0: enabling bus mastering\r
+[ 2.146864] scsi0 : ata_piix\r
+[ 2.146948] scsi1 : ata_piix\r
+[ 2.146979] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
+[ 2.146991] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
+[ 2.147095] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
+[ 2.147108] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
+[ 2.147123] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
+[ 2.147134] e1000 0000:00:00.0: enabling bus mastering\r
+[ 2.290805] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
+[ 2.290816] ata1.00: 2096640 sectors, multi 0: LBA \r
+[ 2.290846] ata1.00: configured for UDMA/33\r
+[ 2.290909] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
+[ 2.291028] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
+[ 2.291029] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
+[ 2.291056] sd 0:0:0:0: [sda] Write Protect is off\r
+[ 2.291067] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
+[ 2.291092] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
+[ 2.291248] sda: sda1\r
+[ 2.291370] sd 0:0:0:0: [sda] Attached SCSI disk\r
+[ 2.411068] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
+[ 2.411082] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
+[ 2.411104] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
+[ 2.411115] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
+[ 2.411135] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
+[ 2.411147] igb: Copyright (c) 2007-2014 Intel Corporation.\r
+[ 2.411217] usbcore: registered new interface driver usb-storage\r
+[ 2.411286] mousedev: PS/2 mouse device common for all mice\r
+[ 2.411453] usbcore: registered new interface driver usbhid\r
+[ 2.411463] usbhid: USB HID core driver\r
+[ 2.411495] TCP: cubic registered\r
+[ 2.411502] NET: Registered protocol family 17\r
+\0[ 2.411926] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
+[ 2.411975] devtmpfs: mounted\r
+[ 2.412025] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
\0\0\rINIT: \0version 2.88 booting\0\r\r
\0Starting udev\r
-[ 2.450669] udevd[609]: starting version 182\r
+[ 2.460540] udevd[609]: starting version 182\r
Starting Bootlog daemon: bootlogd.\r\r
-[ 2.523747] random: dd urandom read with 17 bits of entropy available\r
+[ 2.553667] random: dd urandom read with 18 bits of entropy available\r
Populating dev cache\r\r
net.ipv4.conf.default.rp_filter = 1\r\r
net.ipv4.conf.all.rp_filter = 1\r\r
hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
\rINIT: Entering runlevel: 5\r\r\r
Configuring network interfaces... udhcpc (v1.21.1) started\r\r
-[ 2.651088] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
+[ 2.680995] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
Sending discover...\r\r
Sending discover...\r\r
Sending discover...\r\r
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm64
+boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm64
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb
+dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch64.20140821.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
+exit_on_work_items=false
flags_addr=469827632
gic_cpu_addr=738205696
have_large_asid_64=false
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821
+kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch64.20140821
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
+readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img
+image_file=/home/stever/m5/aarch-system-2014-10/disks/linaro-minimal-aarch64.img
read_only=true
[system.clk_domain]
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=false
hit_latency=1
is_read_only=true
max_miss_count=0
clusivity=mostly_excl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=12
is_read_only=false
max_miss_count=0
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.cpu0.toL2Bus.snoop_filter
snoop_response_latency=1
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=false
hit_latency=1
is_read_only=true
max_miss_count=0
clusivity=mostly_excl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=12
is_read_only=false
max_miss_count=0
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.cpu1.toL2Bus.snoop_filter
snoop_response_latency=1
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=false
hit_latency=50
is_read_only=false
max_miss_count=0
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.toL2Bus.snoop_filter
snoop_response_latency=1
+Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual/simout
+Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 4 2015 11:13:17
-gem5 started Dec 4 2015 11:53:35
-gem5 executing on e104799-lin, pid 548
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual
+gem5 compiled Mar 15 2016 21:26:42
+gem5 started Mar 15 2016 21:52:28
+gem5 executing on phenom, pid 15986
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual
Selected 64-bit ARM architecture, updating default disk image...
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch64.20140821
+info: kernel located at: /home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch64.20140821
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80080000
-info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
+info: Loading DTB file: /home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 47593744171500 because m5_exit instruction encountered
+Exiting @ tick 47460623015500 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 47.579919 # Number of seconds simulated
-sim_ticks 47579919171500 # Number of ticks simulated
-final_tick 47579919171500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 47.460623 # Number of seconds simulated
+sim_ticks 47460623015500 # Number of ticks simulated
+final_tick 47460623015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 994477 # Simulator instruction rate (inst/s)
-host_op_rate 1169790 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 52043300787 # Simulator tick rate (ticks/s)
-host_mem_usage 760992 # Number of bytes of host memory used
-host_seconds 914.24 # Real time elapsed on the host
-sim_insts 909188095 # Number of instructions simulated
-sim_ops 1069465904 # Number of ops (including micro ops) simulated
+host_inst_rate 557401 # Simulator instruction rate (inst/s)
+host_op_rate 655644 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 30226773681 # Simulator tick rate (ticks/s)
+host_mem_usage 730476 # Number of bytes of host memory used
+host_seconds 1570.15 # Real time elapsed on the host
+sim_insts 875204273 # Number of instructions simulated
+sim_ops 1029460892 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker 95808 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 82560 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 3301172 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 14310344 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher 18775424 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 218368 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker 230464 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 3000056 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 12646096 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher 13033600 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 427520 # Number of bytes read from this memory
-system.physmem.bytes_read::total 66121412 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 3301172 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 3000056 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 6301228 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 84303296 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker 81920 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 78144 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 3183732 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 11874696 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher 12415040 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 115712 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker 117120 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 2511992 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 9752208 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher 13330752 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 455552 # Number of bytes read from this memory
+system.physmem.bytes_read::total 53916868 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 3183732 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 2511992 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 5695724 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 73320768 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
-system.physmem.bytes_written::total 84323880 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker 1497 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 1290 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 91988 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 223612 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher 293366 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 3412 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker 3601 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 46964 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 197608 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher 203650 # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide 6680 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1073668 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1317239 # Number of write requests responded to by this memory
+system.physmem.bytes_written::total 73341352 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker 1280 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 1221 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 90153 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 185555 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher 193985 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 1808 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker 1830 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 39338 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 152391 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher 208293 # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide 7118 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 882972 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1145637 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1319813 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker 2014 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 1735 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 69382 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 300764 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher 394608 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 4589 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker 4844 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 63053 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 265786 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher 273931 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 8985 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1389692 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 69382 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 63053 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 132435 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1771825 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 1148211 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker 1726 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 1647 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 67082 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 250201 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher 261586 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 2438 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker 2468 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 52928 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 205480 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher 280880 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide 9599 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1136034 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 67082 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 52928 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 120009 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1544876 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1772258 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1771825 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 2014 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 1735 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 69382 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 301197 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher 394608 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 4589 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker 4844 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 63053 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 265786 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher 273931 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 8985 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 3161949 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 1073668 # Number of read requests accepted
-system.physmem.writeReqs 1319813 # Number of write requests accepted
-system.physmem.readBursts 1073668 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 1319813 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 68691008 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 23744 # Total number of bytes read from write queue
-system.physmem.bytesWritten 84321664 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 66121412 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 84323880 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 371 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 2261 # Number of DRAM write bursts merged with an existing one
+system.physmem.bw_write::total 1545310 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1544876 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 1726 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 1647 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 67082 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 250635 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher 261586 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 2438 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker 2468 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 52928 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 205480 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher 280880 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 9599 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 2681343 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 882972 # Number of read requests accepted
+system.physmem.writeReqs 1148211 # Number of write requests accepted
+system.physmem.readBursts 882972 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 1148211 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 56486656 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 23552 # Total number of bytes read from write queue
+system.physmem.bytesWritten 73339968 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 53916868 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 73341352 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 368 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 2256 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 64017 # Per bank write bursts
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system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes
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+system.physmem.wrPerTurnAround::36-39 124 0.20% 97.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 218 0.36% 98.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 91 0.15% 98.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 270 0.44% 98.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 61 0.10% 98.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 30 0.05% 98.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 50 0.08% 98.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 255 0.42% 99.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 52 0.09% 99.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 24 0.04% 99.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79 99 0.16% 99.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 170 0.28% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87 3 0.00% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91 2 0.00% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 2 0.00% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103 4 0.01% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107 3 0.00% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115 3 0.00% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119 2 0.00% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123 1 0.00% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127 4 0.01% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 14 0.02% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103 1 0.00% 99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107 2 0.00% 99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115 3 0.00% 99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127 1 0.00% 99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 22 0.04% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135 1 0.00% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143 5 0.01% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147 8 0.01% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159 1 0.00% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163 1 0.00% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175 1 0.00% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179 8 0.01% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191 2 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::212-215 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 70958 # Writes before turning the bus around for reads
-system.physmem.totQLat 35332291342 # Total ticks spent queuing
-system.physmem.totMemAccLat 55456610092 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 5366485000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 32919.40 # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::136-139 1 0.00% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143 2 0.00% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147 13 0.02% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151 3 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159 1 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179 3 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::204-207 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 60779 # Writes before turning the bus around for reads
+system.physmem.totQLat 27990688881 # Total ticks spent queuing
+system.physmem.totMemAccLat 44539513881 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 4413020000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 31713.76 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 51669.40 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1.44 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 1.77 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1.39 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 1.77 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 50463.76 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1.19 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 1.55 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1.14 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 1.55 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.03 # Data bus utilization in percentage
+system.physmem.busUtil 0.02 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.40 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 23.48 # Average write queue length when enqueuing
-system.physmem.readRowHits 793862 # Number of row buffer hits during reads
-system.physmem.writeRowHits 489250 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 73.96 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 37.13 # Row buffer hit rate for writes
-system.physmem.avgGap 19878961.15 # Average gap between requests
-system.physmem.pageHitRate 53.67 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 4296030480 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 2344064250 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 4145606400 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 4335450480 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 3107688614160 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 1225363115070 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 27473067932250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 31821240813090 # Total energy per rank (pJ)
-system.physmem_0.averagePower 668.795690 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 45703113685218 # Time in different power states
-system.physmem_0.memoryStateTime::REF 1588797860000 # Time in different power states
+system.physmem.avgRdQLen 1.60 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 24.42 # Average write queue length when enqueuing
+system.physmem.readRowHits 659544 # Number of row buffer hits during reads
+system.physmem.writeRowHits 429323 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 74.73 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 37.46 # Row buffer hit rate for writes
+system.physmem.avgGap 23365998.85 # Average gap between requests
+system.physmem.pageHitRate 53.68 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 3575759040 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 1951059000 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 3364272600 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 3726194400 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 3099896966400 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 1199863250505 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 27423860344500 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 31736237846445 # Total energy per rank (pJ)
+system.physmem_0.averagePower 668.685699 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 45621402632571 # Time in different power states
+system.physmem_0.memoryStateTime::REF 1584814400000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 288003145282 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 254405603429 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 4078249560 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 2225235375 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 4226055600 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 4202118000 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 3107688614160 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 1219254807825 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 27478426088250 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 31820101168770 # Total energy per rank (pJ)
-system.physmem_1.averagePower 668.771738 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 45712034121275 # Time in different power states
-system.physmem_1.memoryStateTime::REF 1588797860000 # Time in different power states
+system.physmem_1.actEnergy 3528047880 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 1925026125 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 3519999600 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 3699373680 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 3099896966400 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 1198418138910 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 27425127986250 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 31736115538845 # Total energy per rank (pJ)
+system.physmem_1.averagePower 668.683122 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 45623502554973 # Time in different power states
+system.physmem_1.memoryStateTime::REF 1584814400000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 279086495725 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 252305273527 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.walks 116306 # Table walker walks requested
-system.cpu0.dtb.walker.walksLong 116306 # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10885 # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 88573 # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore 22 # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples 116284 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean 0.223591 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev 76.245351 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-2047 116283 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walks 102194 # Table walker walks requested
+system.cpu0.dtb.walker.walksLong 102194 # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9208 # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 76624 # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples 102185 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean 0.254440 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev 81.335431 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-2047 102184 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 116284 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples 99480 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 22519.581825 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 21136.105654 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 15840.339731 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535 98726 99.24% 99.24% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071 154 0.15% 99.40% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607 495 0.50% 99.89% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143 15 0.02% 99.91% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-327679 37 0.04% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-393215 19 0.02% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::393216-458751 26 0.03% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkWaitTime::total 102185 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples 85841 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 22586.042800 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 20965.618936 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 16893.735669 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-65535 85046 99.07% 99.07% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071 170 0.20% 99.27% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-196607 522 0.61% 99.88% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-262143 25 0.03% 99.91% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-327679 28 0.03% 99.94% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-393215 14 0.02% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-458751 28 0.03% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total 99480 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples 8374009004 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean 0.680543 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::stdev 0.466266 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0 2675132860 31.95% 31.95% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::1 5698876144 68.05% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 8374009004 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 88573 89.06% 89.06% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M 10885 10.94% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 99458 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 116306 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkCompletionTime::total 85841 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples 4536625496 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean 0.282786 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev 0.450353 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0 3253731032 71.72% 71.72% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::1 1282894464 28.28% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 4536625496 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K 76625 89.27% 89.27% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M 9208 10.73% 100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total 85833 # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 102194 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 116306 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 99458 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 102194 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 85833 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 99458 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 215764 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 85833 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total 188027 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 86290817 # DTB read hits
-system.cpu0.dtb.read_misses 86990 # DTB read misses
-system.cpu0.dtb.write_hits 77965379 # DTB write hits
-system.cpu0.dtb.write_misses 29316 # DTB write misses
+system.cpu0.dtb.read_hits 85563003 # DTB read hits
+system.cpu0.dtb.read_misses 75756 # DTB read misses
+system.cpu0.dtb.write_hits 77475573 # DTB write hits
+system.cpu0.dtb.write_misses 26438 # DTB write misses
system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 43834 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 1062 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 36691 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_tlb_mva_asid 40703 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 1030 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 34001 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 4448 # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults 4044 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 9789 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 86377807 # DTB read accesses
-system.cpu0.dtb.write_accesses 77994695 # DTB write accesses
+system.cpu0.dtb.perms_faults 8915 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 85638759 # DTB read accesses
+system.cpu0.dtb.write_accesses 77502011 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 164256196 # DTB hits
-system.cpu0.dtb.misses 116306 # DTB misses
-system.cpu0.dtb.accesses 164372502 # DTB accesses
+system.cpu0.dtb.hits 163038576 # DTB hits
+system.cpu0.dtb.misses 102194 # DTB misses
+system.cpu0.dtb.accesses 163140770 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.walker.walks 53337 # Table walker walks requested
-system.cpu0.itb.walker.walksLong 53337 # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2 559 # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3 47077 # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples 53337 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0 53337 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total 53337 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples 47636 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 25421.330506 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 23137.989766 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 22597.528238 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-65535 46963 98.59% 98.59% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-131071 37 0.08% 98.66% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-196607 536 1.13% 99.79% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-262143 19 0.04% 99.83% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-327679 27 0.06% 99.89% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-393215 15 0.03% 99.92% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-458751 23 0.05% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::458752-524287 11 0.02% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::524288-589823 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total 47636 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walks 56381 # Table walker walks requested
+system.cpu0.itb.walker.walksLong 56381 # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2 642 # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3 50009 # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples 56381 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0 56381 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total 56381 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples 50651 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 25304.495469 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 23033.115990 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 21560.503846 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-65535 49913 98.54% 98.54% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-131071 55 0.11% 98.65% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-196607 593 1.17% 99.82% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-262143 11 0.02% 99.84% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-327679 28 0.06% 99.90% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-393215 13 0.03% 99.92% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-458751 34 0.07% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::458752-524287 3 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total 50651 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 1979242204 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 1979242204 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 1979242204 # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K 47077 98.83% 98.83% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M 559 1.17% 100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total 47636 # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::4K 50009 98.73% 98.73% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M 642 1.27% 100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total 50651 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 53337 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total 53337 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 56381 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total 56381 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 47636 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total 47636 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total 100973 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 461259285 # ITB inst hits
-system.cpu0.itb.inst_misses 53337 # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 50651 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total 50651 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total 107032 # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits 455204971 # ITB inst hits
+system.cpu0.itb.inst_misses 56381 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 43834 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 1062 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 25459 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid 40703 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 1030 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 24108 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 461312622 # ITB inst accesses
-system.cpu0.itb.hits 461259285 # DTB hits
-system.cpu0.itb.misses 53337 # DTB misses
-system.cpu0.itb.accesses 461312622 # DTB accesses
-system.cpu0.numCycles 95159838338 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 455261352 # ITB inst accesses
+system.cpu0.itb.hits 455204971 # DTB hits
+system.cpu0.itb.misses 56381 # DTB misses
+system.cpu0.itb.accesses 455261352 # DTB accesses
+system.cpu0.numCycles 94921246031 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 13594 # number of quiesce instructions executed
-system.cpu0.committedInsts 460977499 # Number of instructions committed
-system.cpu0.committedOps 540688150 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 495872658 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 377758 # Number of float alu accesses
-system.cpu0.num_func_calls 27096084 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 70442961 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 495872658 # number of integer instructions
-system.cpu0.num_fp_insts 377758 # number of float instructions
-system.cpu0.num_int_register_reads 724744849 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 393986605 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 623895 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 289632 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 122670714 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 122315787 # number of times the CC registers were written
-system.cpu0.num_mem_refs 164249297 # number of memory refs
-system.cpu0.num_load_insts 86287437 # Number of load instructions
-system.cpu0.num_store_insts 77961860 # Number of store instructions
-system.cpu0.num_idle_cycles 93938070746.252213 # Number of idle cycles
-system.cpu0.num_busy_cycles 1221767591.747779 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.012839 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.987161 # Percentage of idle cycles
-system.cpu0.Branches 102925889 # Number of branches fetched
-system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu 375485543 69.40% 69.40% # Class of executed instruction
-system.cpu0.op_class::IntMult 1178634 0.22% 69.62% # Class of executed instruction
-system.cpu0.op_class::IntDiv 59866 0.01% 69.63% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 0 0.00% 69.63% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 0 0.00% 69.63% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 0 0.00% 69.63% # Class of executed instruction
-system.cpu0.op_class::FloatMult 0 0.00% 69.63% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 0 0.00% 69.63% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 69.63% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 69.63% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc 0 0.00% 69.63% # Class of executed instruction
-system.cpu0.op_class::SimdAlu 0 0.00% 69.63% # Class of executed instruction
-system.cpu0.op_class::SimdCmp 0 0.00% 69.63% # Class of executed instruction
-system.cpu0.op_class::SimdCvt 0 0.00% 69.63% # Class of executed instruction
-system.cpu0.op_class::SimdMisc 0 0.00% 69.63% # Class of executed instruction
-system.cpu0.op_class::SimdMult 0 0.00% 69.63% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc 0 0.00% 69.63% # Class of executed instruction
-system.cpu0.op_class::SimdShift 0 0.00% 69.63% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.63% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt 0 0.00% 69.63% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.63% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.63% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.63% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.63% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.63% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 39720 0.01% 69.64% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult 0 0.00% 69.64% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.64% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.64% # Class of executed instruction
-system.cpu0.op_class::MemRead 86287437 15.95% 85.59% # Class of executed instruction
-system.cpu0.op_class::MemWrite 77961860 14.41% 100.00% # Class of executed instruction
+system.cpu0.kern.inst.quiesce 13214 # number of quiesce instructions executed
+system.cpu0.committedInsts 454926589 # Number of instructions committed
+system.cpu0.committedOps 534313943 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 491049300 # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses 395385 # Number of float alu accesses
+system.cpu0.num_func_calls 27308099 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 68959046 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 491049300 # number of integer instructions
+system.cpu0.num_fp_insts 395385 # number of float instructions
+system.cpu0.num_int_register_reads 709557386 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 389375063 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 654866 # number of times the floating registers were read
+system.cpu0.num_fp_register_writes 293356 # number of times the floating registers were written
+system.cpu0.num_cc_register_reads 117980325 # number of times the CC registers were read
+system.cpu0.num_cc_register_writes 117652107 # number of times the CC registers were written
+system.cpu0.num_mem_refs 163029477 # number of memory refs
+system.cpu0.num_load_insts 85557806 # Number of load instructions
+system.cpu0.num_store_insts 77471671 # Number of store instructions
+system.cpu0.num_idle_cycles 93727706914.782028 # Number of idle cycles
+system.cpu0.num_busy_cycles 1193539116.217975 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.012574 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.987426 # Percentage of idle cycles
+system.cpu0.Branches 101606994 # Number of branches fetched
+system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu 370328410 69.27% 69.27% # Class of executed instruction
+system.cpu0.op_class::IntMult 1177627 0.22% 69.49% # Class of executed instruction
+system.cpu0.op_class::IntDiv 60510 0.01% 69.50% # Class of executed instruction
+system.cpu0.op_class::FloatAdd 0 0.00% 69.50% # Class of executed instruction
+system.cpu0.op_class::FloatCmp 0 0.00% 69.50% # Class of executed instruction
+system.cpu0.op_class::FloatCvt 0 0.00% 69.50% # Class of executed instruction
+system.cpu0.op_class::FloatMult 0 0.00% 69.50% # Class of executed instruction
+system.cpu0.op_class::FloatDiv 0 0.00% 69.50% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt 0 0.00% 69.50% # Class of executed instruction
+system.cpu0.op_class::SimdAdd 0 0.00% 69.50% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc 0 0.00% 69.50% # Class of executed instruction
+system.cpu0.op_class::SimdAlu 0 0.00% 69.50% # Class of executed instruction
+system.cpu0.op_class::SimdCmp 0 0.00% 69.50% # Class of executed instruction
+system.cpu0.op_class::SimdCvt 0 0.00% 69.50% # Class of executed instruction
+system.cpu0.op_class::SimdMisc 0 0.00% 69.50% # Class of executed instruction
+system.cpu0.op_class::SimdMult 0 0.00% 69.50% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc 0 0.00% 69.50% # Class of executed instruction
+system.cpu0.op_class::SimdShift 0 0.00% 69.50% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.50% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt 0 0.00% 69.50% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.50% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.50% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.50% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.50% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.50% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc 39424 0.01% 69.51% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult 0 0.00% 69.51% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.51% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.51% # Class of executed instruction
+system.cpu0.op_class::MemRead 85557806 16.00% 85.51% # Class of executed instruction
+system.cpu0.op_class::MemWrite 77471671 14.49% 100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 541013060 # Class of executed instruction
-system.cpu0.dcache.tags.replacements 5729731 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 475.426094 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 158277130 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 5730241 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 27.621374 # Average number of references to valid blocks.
+system.cpu0.op_class::total 534635449 # Class of executed instruction
+system.cpu0.dcache.tags.replacements 5459134 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 479.881862 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 157334556 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 5459646 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 28.817721 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 6293818000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 475.426094 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.928567 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.928567 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 56 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 399 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 334208607 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 334208607 # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data 80244173 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 80244173 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 73488227 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 73488227 # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data 200421 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total 200421 # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data 184838 # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total 184838 # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1883304 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 1883304 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1842196 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 1842196 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 153732400 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 153732400 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 153932821 # number of overall hits
-system.cpu0.dcache.overall_hits::total 153932821 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 3080001 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 3080001 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 1447988 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 1447988 # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data 695954 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total 695954 # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data 768699 # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total 768699 # number of WriteLineReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 158470 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 158470 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data 198134 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 198134 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 4527989 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 4527989 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 5223943 # number of overall misses
-system.cpu0.dcache.overall_misses::total 5223943 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 52478340000 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 52478340000 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 38322628500 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 38322628500 # number of WriteReq miss cycles
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system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
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system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu0.dcache.writebacks::total 5729731 # number of writebacks
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-system.cpu0.dcache.overall_mshr_misses::total 5173487 # number of overall MSHR misses
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-system.cpu0.dcache.ReadReq_mshr_uncacheable::total 28514 # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 27871 # number of WriteReq MSHR uncacheable
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-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1643233500 # number of LoadLockedReq MSHR miss cycles
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-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5280351500 # number of ReadReq MSHR uncacheable cycles
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-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5086850000 # number of WriteReq MSHR uncacheable cycles
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-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10367201500 # number of overall MSHR uncacheable cycles
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-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.775133 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.775133 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.806155 # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.806155 # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.057505 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.057505 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.097109 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.097109 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028299 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.028299 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032506 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.032506 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15503.456995 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15503.456995 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25502.030140 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25502.030140 # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24471.479973 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24471.479973 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 63471.947407 # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 63471.947407 # average WriteLineReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13995.447654 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13995.447654 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27209.845357 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27209.845357 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 5459134 # number of writebacks
+system.cpu0.dcache.writebacks::total 5459134 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 24235 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 24235 # number of ReadReq MSHR hits
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+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 43300 # number of LoadLockedReq MSHR hits
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+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.805275 # mshr miss rate for WriteLineReq accesses
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system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18688.650800 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18688.650800 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19465.296714 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19465.296714 # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185184.523392 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185184.523392 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182514.082738 # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 182514.082738 # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 183864.529573 # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 183864.529573 # average overall mshr uncacheable latency
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+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184110.640011 # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements 4741257 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.854043 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 456517510 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 4741769 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 96.275780 # Average number of references to valid blocks.
+system.cpu0.icache.tags.replacements 5000286 # number of replacements
+system.cpu0.icache.tags.tagsinuse 511.853700 # Cycle average of tags in use
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system.cpu0.icache.tags.warmup_cycle 46470060000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.854043 # Average occupied blocks per requestor
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-system.cpu0.icache.tags.occ_percent::total 0.999715 # Average percentage of cache occupancy
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system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
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-system.cpu0.icache.tags.age_task_id_blocks_1024::1 110 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 276 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
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+system.cpu0.icache.tags.age_task_id_blocks_1024::1 336 # Occupied blocks per task id
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system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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-system.cpu0.icache.ReadReq_avg_miss_latency::total 11365.051800 # average ReadReq miss latency
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-system.cpu0.icache.demand_avg_miss_latency::total 11365.051800 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11365.051800 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 11365.051800 # average overall miss latency
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+system.cpu0.icache.ReadReq_hits::total 450204172 # number of ReadReq hits
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system.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable
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-system.cpu0.icache.ReadReq_mshr_miss_latency::total 51519631500 # number of ReadReq MSHR miss cycles
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system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138068.614493 # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
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system.cpu0.l2cache.tags.warmup_cycle 8106870500 # Cycle when the warmup percentage was hit.
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+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.998394 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.212204 # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.212204 # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.098594 # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.098594 # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.254110 # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.254110 # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.778461 # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.778461 # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.034964 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.052143 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.098594 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.244226 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total 0.168169 # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.034964 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.052143 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.098594 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.244226 # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.221718 # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.221718 # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.091775 # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.091775 # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.245719 # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.245719 # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.755778 # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.755778 # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.039628 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.050848 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.091775 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.240188 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total 0.159779 # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.039628 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.050848 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.091775 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.240188 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total 0.246709 # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 36703.309338 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 38935.907750 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 37656.958763 # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 69416.351262 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 69416.351262 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 30104.940787 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 30104.940787 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19703.980740 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19703.980740 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 482899.600000 # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 482899.600000 # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 62918.364243 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 62918.364243 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 34098.951036 # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34098.951036 # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 36088.202106 # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 36088.202106 # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 71877.062952 # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 71877.062952 # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 36703.309338 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 38935.907750 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 34098.951036 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 41586.766119 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 39511.624446 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 36703.309338 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 38935.907750 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 34098.951036 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 41586.766119 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 69416.351262 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 49031.784454 # average overall mshr miss latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total 0.226157 # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 34090.241397 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 36649.993487 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 35218.843326 # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55618.555748 # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 55618.555748 # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 30327.980817 # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 30327.980817 # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19401.010006 # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19401.010006 # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 308176.294118 # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 308176.294118 # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57887.022480 # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57887.022480 # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33672.786836 # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33672.786836 # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 33686.225156 # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33686.225156 # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 70074.831676 # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 70074.831676 # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 34090.241397 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 36649.993487 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33672.786836 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 38834.979997 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 37342.411589 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 34090.241397 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 36649.993487 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33672.786836 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 38834.979997 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55618.555748 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 42706.485834 # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177171.722663 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149117.743129 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 175001.040508 # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 175001.040508 # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 176686.417657 # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149282.624871 # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 175993.534781 # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 175993.534781 # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493 # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 176098.758535 # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 156367.199276 # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 176343.097955 # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 156894.388122 # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.toL2Bus.snoop_filter.tot_requests 21737448 # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11172038 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1012 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops 1879362 # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1879064 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.tot_requests 21678176 # Total number of requests made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11128402 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 962 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.snoop_filter.tot_snoops 1759585 # Total number of snoops made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1759287 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 298 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.trans_dist::ReadReq 568365 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp 9266330 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq 27872 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp 27871 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackDirty 5482404 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackClean 6640558 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict 2386717 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq 980471 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq 448075 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 360841 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp 517122 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 53 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 86 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq 1223880 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp 1201425 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq 4741775 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4748017 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq 819035 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateResp 766846 # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 14311056 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18559366 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 302345 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 623475 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total 33796242 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 607086484 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 696970881 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1144232 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2288536 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total 1307490133 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops 6577979 # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples 17957076 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean 0.118626 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev 0.323399 # Request fanout histogram
+system.cpu0.toL2Bus.trans_dist::ReadReq 537700 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp 9321471 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq 28925 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp 28924 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackDirty 5081322 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackClean 6856856 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict 2248329 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq 834929 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq 427184 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 348871 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp 496915 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 88 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 134 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq 1135852 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp 1114697 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5000799 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4556956 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq 799366 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateResp 748142 # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 15088134 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17701155 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 319339 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 542421 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total 33651049 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 640241940 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 663021135 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1207824 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1965272 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total 1306436171 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops 6076867 # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples 17397758 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean 0.114750 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev 0.318774 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0 15827205 88.14% 88.14% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1 2129573 11.86% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0 15401663 88.53% 88.53% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1 1995797 11.47% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 298 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total 17957076 # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy 21527019496 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total 17397758 # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy 21478508994 # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy 184192978 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy 177190009 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy 7155786000 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy 7544323500 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy 8237151691 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy 7836374127 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy 159316000 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy 168361000 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy 337408998 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy 296762000 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.dtb.walker.walks 108188 # Table walker walks requested
-system.cpu1.dtb.walker.walksLong 108188 # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9416 # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 83328 # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore 4 # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples 108184 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean 0.073948 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev 24.322514 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-511 108183 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walks 108457 # Table walker walks requested
+system.cpu1.dtb.walker.walksLong 108457 # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9827 # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 84631 # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore 22 # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples 108435 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean 0.073777 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev 24.294348 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-511 108434 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::7680-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total 108184 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples 92748 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 25260.781904 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 21819.891311 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 28424.827210 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535 90515 97.59% 97.59% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-131071 165 0.18% 97.77% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-196607 1735 1.87% 99.64% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-262143 64 0.07% 99.71% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-327679 109 0.12% 99.83% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-393215 46 0.05% 99.88% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-458751 73 0.08% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::458752-524287 21 0.02% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::524288-589823 8 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::589824-655359 8 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total 92748 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples -800290088 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean -1.452962 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0 -1963081332 245.30% 245.30% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::1 1162791244 -145.30% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total -800290088 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K 83329 89.85% 89.85% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M 9416 10.15% 100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total 92745 # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 108188 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkWaitTime::total 108435 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples 94480 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 23264.092930 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 21359.678554 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 19330.218287 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535 93351 98.81% 98.81% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071 176 0.19% 98.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607 798 0.84% 99.84% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143 40 0.04% 99.88% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679 45 0.05% 99.93% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215 27 0.03% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-458751 24 0.03% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::458752-524287 10 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::524288-589823 6 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total 94480 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples 3353012192 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean 1.550742 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0 -1846644332 -55.07% -55.07% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::1 5199656524 155.07% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total 3353012192 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K 84631 89.60% 89.60% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M 9827 10.40% 100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total 94458 # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 108457 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 108188 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 92745 # Table walker requests started/completed, data/inst
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+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 94458 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 92745 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total 200933 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 94458 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total 202915 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 84911532 # DTB read hits
-system.cpu1.dtb.read_misses 79075 # DTB read misses
-system.cpu1.dtb.write_hits 77663318 # DTB write hits
-system.cpu1.dtb.write_misses 29113 # DTB write misses
+system.cpu1.dtb.read_hits 79507348 # DTB read hits
+system.cpu1.dtb.read_misses 80723 # DTB read misses
+system.cpu1.dtb.write_hits 72319570 # DTB write hits
+system.cpu1.dtb.write_misses 27734 # DTB write misses
system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 43834 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 1062 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 39584 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_tlb_mva_asid 40703 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 1030 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 39844 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 5277 # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults 4607 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 10813 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 84990607 # DTB read accesses
-system.cpu1.dtb.write_accesses 77692431 # DTB write accesses
+system.cpu1.dtb.perms_faults 10580 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 79588071 # DTB read accesses
+system.cpu1.dtb.write_accesses 72347304 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 162574850 # DTB hits
-system.cpu1.dtb.misses 108188 # DTB misses
-system.cpu1.dtb.accesses 162683038 # DTB accesses
+system.cpu1.dtb.hits 151826918 # DTB hits
+system.cpu1.dtb.misses 108457 # DTB misses
+system.cpu1.dtb.accesses 151935375 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.walker.walks 63937 # Table walker walks requested
-system.cpu1.itb.walker.walksLong 63937 # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2 631 # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3 57861 # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples 63937 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0 63937 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total 63937 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples 58492 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 30403.747521 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 24852.510144 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 37514.660324 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-65535 55985 95.71% 95.71% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-131071 47 0.08% 95.79% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-196607 2099 3.59% 99.38% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-262143 87 0.15% 99.53% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-327679 102 0.17% 99.71% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-393215 51 0.09% 99.79% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-458751 79 0.14% 99.93% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::458752-524287 15 0.03% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::524288-589823 17 0.03% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::589824-655359 4 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::655360-720895 4 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::917504-983039 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total 58492 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walks 59789 # Table walker walks requested
+system.cpu1.itb.walker.walksLong 59789 # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2 555 # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3 54230 # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples 59789 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0 59789 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total 59789 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples 54785 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 26806.178699 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 23797.611376 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 25937.791406 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-65535 53612 97.86% 97.86% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-131071 36 0.07% 97.92% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-196607 992 1.81% 99.74% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-262143 28 0.05% 99.79% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-327679 57 0.10% 99.89% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-393215 10 0.02% 99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-458751 37 0.07% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::458752-524287 4 0.01% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::524288-589823 4 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::589824-655359 3 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total 54785 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples -1988115332 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 -1988115332 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total -1988115332 # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K 57861 98.92% 98.92% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M 631 1.08% 100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total 58492 # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::4K 54230 98.99% 98.99% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M 555 1.01% 100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total 54785 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 63937 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total 63937 # Table walker requests started/completed, data/inst
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system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 58492 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total 58492 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total 122429 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 448499634 # ITB inst hits
-system.cpu1.itb.inst_misses 63937 # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 54785 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total 54785 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total 114574 # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits 420546617 # ITB inst hits
+system.cpu1.itb.inst_misses 59789 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 43834 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 1062 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 27923 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid 40703 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 1030 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 27682 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 448563571 # ITB inst accesses
-system.cpu1.itb.hits 448499634 # DTB hits
-system.cpu1.itb.misses 63937 # DTB misses
-system.cpu1.itb.accesses 448563571 # DTB accesses
-system.cpu1.numCycles 95159838343 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 420606406 # ITB inst accesses
+system.cpu1.itb.hits 420546617 # DTB hits
+system.cpu1.itb.misses 59789 # DTB misses
+system.cpu1.itb.accesses 420606406 # DTB accesses
+system.cpu1.numCycles 94920662633 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 5923 # number of quiesce instructions executed
-system.cpu1.committedInsts 448210596 # Number of instructions committed
-system.cpu1.committedOps 528777754 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 486415785 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 519922 # Number of float alu accesses
-system.cpu1.num_func_calls 27136019 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 67942031 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 486415785 # number of integer instructions
-system.cpu1.num_fp_insts 519922 # number of float instructions
-system.cpu1.num_int_register_reads 706615491 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 385601488 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 832776 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 452540 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 115428294 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 115157338 # number of times the CC registers were written
-system.cpu1.num_mem_refs 162566757 # number of memory refs
-system.cpu1.num_load_insts 84909557 # Number of load instructions
-system.cpu1.num_store_insts 77657200 # Number of store instructions
-system.cpu1.num_idle_cycles 94045434394.442017 # Number of idle cycles
-system.cpu1.num_busy_cycles 1114403948.557976 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.011711 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.988289 # Percentage of idle cycles
-system.cpu1.Branches 99989008 # Number of branches fetched
-system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu 365279701 69.04% 69.04% # Class of executed instruction
-system.cpu1.op_class::IntMult 1087060 0.21% 69.25% # Class of executed instruction
-system.cpu1.op_class::IntDiv 61840 0.01% 69.26% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 0 0.00% 69.26% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 0 0.00% 69.26% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 0 0.00% 69.26% # Class of executed instruction
-system.cpu1.op_class::FloatMult 0 0.00% 69.26% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 0 0.00% 69.26% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 69.26% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 69.26% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 69.26% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 69.26% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 69.26% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 69.26% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 69.26% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 69.26% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 69.26% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 69.26% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.26% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 69.26% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.26% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.26% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.26% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.26% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.26% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 71500 0.01% 69.27% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 69.27% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.27% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.27% # Class of executed instruction
-system.cpu1.op_class::MemRead 84909557 16.05% 85.32% # Class of executed instruction
-system.cpu1.op_class::MemWrite 77657200 14.68% 100.00% # Class of executed instruction
+system.cpu1.kern.inst.quiesce 5531 # number of quiesce instructions executed
+system.cpu1.committedInsts 420277684 # Number of instructions committed
+system.cpu1.committedOps 495146949 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 454880180 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 506575 # Number of float alu accesses
+system.cpu1.num_func_calls 25039229 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 63957319 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 454880180 # number of integer instructions
+system.cpu1.num_fp_insts 506575 # number of float instructions
+system.cpu1.num_int_register_reads 664278142 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 361063382 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 809640 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 450820 # number of times the floating registers were written
+system.cpu1.num_cc_register_reads 110083158 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 109779727 # number of times the CC registers were written
+system.cpu1.num_mem_refs 151817768 # number of memory refs
+system.cpu1.num_load_insts 79504880 # Number of load instructions
+system.cpu1.num_store_insts 72312888 # Number of store instructions
+system.cpu1.num_idle_cycles 93883487625.302155 # Number of idle cycles
+system.cpu1.num_busy_cycles 1037175007.697842 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.010927 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.989073 # Percentage of idle cycles
+system.cpu1.Branches 93646526 # Number of branches fetched
+system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu 342430715 69.12% 69.12% # Class of executed instruction
+system.cpu1.op_class::IntMult 1035788 0.21% 69.33% # Class of executed instruction
+system.cpu1.op_class::IntDiv 58966 0.01% 69.34% # Class of executed instruction
+system.cpu1.op_class::FloatAdd 0 0.00% 69.34% # Class of executed instruction
+system.cpu1.op_class::FloatCmp 0 0.00% 69.34% # Class of executed instruction
+system.cpu1.op_class::FloatCvt 0 0.00% 69.34% # Class of executed instruction
+system.cpu1.op_class::FloatMult 0 0.00% 69.34% # Class of executed instruction
+system.cpu1.op_class::FloatDiv 0 0.00% 69.34% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt 0 0.00% 69.34% # Class of executed instruction
+system.cpu1.op_class::SimdAdd 0 0.00% 69.34% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc 0 0.00% 69.34% # Class of executed instruction
+system.cpu1.op_class::SimdAlu 0 0.00% 69.34% # Class of executed instruction
+system.cpu1.op_class::SimdCmp 0 0.00% 69.34% # Class of executed instruction
+system.cpu1.op_class::SimdCvt 0 0.00% 69.34% # Class of executed instruction
+system.cpu1.op_class::SimdMisc 0 0.00% 69.34% # Class of executed instruction
+system.cpu1.op_class::SimdMult 0 0.00% 69.34% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc 0 0.00% 69.34% # Class of executed instruction
+system.cpu1.op_class::SimdShift 0 0.00% 69.34% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.34% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt 0 0.00% 69.34% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.34% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.34% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.34% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.34% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.34% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 72713 0.01% 69.36% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult 0 0.00% 69.36% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.36% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.36% # Class of executed instruction
+system.cpu1.op_class::MemRead 79504880 16.05% 85.40% # Class of executed instruction
+system.cpu1.op_class::MemWrite 72312888 14.60% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 529066901 # Class of executed instruction
-system.cpu1.dcache.tags.replacements 5332630 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 455.913081 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 157043226 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 5333142 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 29.446661 # Average number of references to valid blocks.
+system.cpu1.op_class::total 495415992 # Class of executed instruction
+system.cpu1.dcache.tags.replacements 5111729 # number of replacements
+system.cpu1.dcache.tags.tagsinuse 453.815972 # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs 146515734 # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs 5112105 # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs 28.660549 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 8395596843000 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 455.913081 # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data 0.890455 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total 0.890455 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1 413 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2 40 # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses 330516943 # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses 330516943 # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data 79081838 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 79081838 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 73714078 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 73714078 # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data 184325 # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total 184325 # number of SoftPFReq hits
-system.cpu1.dcache.WriteLineReq_hits::cpu1.data 141992 # number of WriteLineReq hits
-system.cpu1.dcache.WriteLineReq_hits::total 141992 # number of WriteLineReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1768915 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 1768915 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1742986 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 1742986 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 152795916 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 152795916 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 152980241 # number of overall hits
-system.cpu1.dcache.overall_hits::total 152980241 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data 3051137 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 3051137 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 1365469 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 1365469 # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data 638330 # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total 638330 # number of SoftPFReq misses
-system.cpu1.dcache.WriteLineReq_misses::cpu1.data 475836 # number of WriteLineReq misses
-system.cpu1.dcache.WriteLineReq_misses::total 475836 # number of WriteLineReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 176856 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 176856 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data 201345 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 201345 # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data 4416606 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 4416606 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data 5054936 # number of overall misses
-system.cpu1.dcache.overall_misses::total 5054936 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 51930161500 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 51930161500 # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 32223402000 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 32223402000 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 17094390000 # number of WriteLineReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::total 17094390000 # number of WriteLineReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3024227500 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total 3024227500 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5760420500 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total 5760420500 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 4429500 # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total 4429500 # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 84153563500 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 84153563500 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 84153563500 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 84153563500 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 82132975 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 82132975 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data 75079547 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 75079547 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 822655 # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total 822655 # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 617828 # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::total 617828 # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1945771 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total 1945771 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1944331 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total 1944331 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data 157212522 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 157212522 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data 158035177 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 158035177 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037149 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total 0.037149 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018187 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total 0.018187 # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.775939 # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total 0.775939 # miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.770176 # miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::total 0.770176 # miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.090893 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.090893 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103555 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103555 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data 0.028093 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total 0.028093 # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data 0.031986 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total 0.031986 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 17019.937649 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 17019.937649 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 23598.779613 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 23598.779613 # average WriteReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 35924.961541 # average WriteLineReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 35924.961541 # average WriteLineReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 17099.942891 # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 17099.942891 # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 28609.702252 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 28609.702252 # average StoreCondReq miss latency
+system.cpu1.dcache.tags.occ_blocks::cpu1.data 453.815972 # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data 0.886359 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total 0.886359 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024 376 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2 373 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024 0.734375 # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses 308802786 # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses 308802786 # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data 74029008 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total 74029008 # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data 68561672 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total 68561672 # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data 171099 # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total 171099 # number of SoftPFReq hits
+system.cpu1.dcache.WriteLineReq_hits::cpu1.data 145458 # number of WriteLineReq hits
+system.cpu1.dcache.WriteLineReq_hits::total 145458 # number of WriteLineReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1631683 # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total 1631683 # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1602426 # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total 1602426 # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data 142590680 # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total 142590680 # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data 142761779 # number of overall hits
+system.cpu1.dcache.overall_hits::total 142761779 # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data 2875045 # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total 2875045 # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data 1313230 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total 1313230 # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data 626301 # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total 626301 # number of SoftPFReq misses
+system.cpu1.dcache.WriteLineReq_misses::cpu1.data 483495 # number of WriteLineReq misses
+system.cpu1.dcache.WriteLineReq_misses::total 483495 # number of WriteLineReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 165519 # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total 165519 # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data 193387 # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total 193387 # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data 4188275 # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total 4188275 # number of demand (read+write) misses
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+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15749.154709 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 15749.154709 # average ReadReq miss latency
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system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
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-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16647.799992 # average overall miss latency
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system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 5332630 # number of writebacks
-system.cpu1.dcache.writebacks::total 5332630 # number of writebacks
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-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036878 # mshr miss rate for ReadReq accesses
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-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22587.538598 # average WriteReq mshr miss latency
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-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 34924.961541 # average WriteLineReq mshr miss latency
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-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14710.581247 # average LoadLockedReq mshr miss latency
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-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 27609.940649 # average StoreCondReq mshr miss latency
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system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
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system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 134213.636364 # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
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+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32316.734905 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20196.741531 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20196.741531 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 409178.428571 # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 409178.428571 # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 47670.371889 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 47670.371889 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31865.767877 # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31865.767877 # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 33190.039911 # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33190.039911 # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 52151.457317 # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 52151.457317 # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 41747.456923 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 46104.569859 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31865.767877 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 36331.942504 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 35129.272040 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 41747.456923 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 46104.569859 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31865.767877 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 36331.942504 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 58844.826929 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 42382.031452 # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 126713.636364 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 154769.189083 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 154468.369237 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 163932.755698 # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 163932.755698 # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 159620.192860 # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 159209.840154 # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 165281.205323 # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 165281.205323 # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 126713.636364 # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 159454.446959 # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 159281.937060 # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 162511.430016 # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 162291.615496 # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.toL2Bus.snoop_filter.tot_requests 22159802 # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11360195 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 912 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops 1833001 # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1832814 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 187 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.trans_dist::ReadReq 515851 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp 9779420 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq 10618 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp 10618 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackDirty 4509550 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackClean 7338954 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict 2389159 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq 893791 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq 389403 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 363316 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp 479303 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 86 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq 1190307 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp 1167875 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5369048 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4688099 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateReq 521676 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateResp 473618 # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 16106851 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17229570 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 365629 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 576836 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total 34278886 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 687205752 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 665341501 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1396720 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 2098264 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total 1356042237 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops 5987251 # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples 17478652 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean 0.119213 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev 0.324072 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_filter.tot_requests 20782124 # Total number of requests made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10655468 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 892 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.snoop_filter.tot_snoops 1707466 # Total number of snoops made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1707307 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 159 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.trans_dist::ReadReq 502417 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp 9121363 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq 9093 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp 9093 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackDirty 4367100 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackClean 6772532 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict 2206652 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq 838220 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq 373270 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 349428 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 455882 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 77 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 134 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq 1149239 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp 1127446 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4920793 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4454860 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateReq 528061 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateResp 481641 # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14762082 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16505656 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 342155 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 581136 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total 32191029 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 629828856 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 636046096 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1307840 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 2129720 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total 1269312512 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops 5644464 # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples 16439738 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean 0.118176 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.322847 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0 15395152 88.08% 88.08% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1 2083313 11.92% 100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2 187 0.00% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0 14497112 88.18% 88.18% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1 1942467 11.82% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2 159 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total 17478652 # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy 21924818496 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total 16439738 # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy 20566237996 # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy 193282156 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy 185505924 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy 8053682000 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy 7381299500 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy 7892863413 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy 7535601373 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy 191039000 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy 178675000 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy 314553499 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy 314921000 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 40370 # Transaction distribution
-system.iobus.trans_dist::ReadResp 40370 # Transaction distribution
-system.iobus.trans_dist::WriteReq 136628 # Transaction distribution
-system.iobus.trans_dist::WriteResp 136628 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47782 # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::ReadReq 40334 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40334 # Transaction distribution
+system.iobus.trans_dist::WriteReq 136621 # Transaction distribution
+system.iobus.trans_dist::WriteResp 136621 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47682 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 122664 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231252 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 231252 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 122616 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231214 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 231214 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 353996 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47802 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total 353910 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47702 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 155794 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339024 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 7339024 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 155723 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338872 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 7338872 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 7496904 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 37005501 # Layer occupancy (ticks)
+system.iobus.pkt_size::total 7496681 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 36912500 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 12000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 324001 # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy 323000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 8500 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 26468500 # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy 26561500 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer24.occupancy 37415000 # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy 37416000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 567277400 # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy 567387857 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 92767000 # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy 92726000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer3.occupancy 147948000 # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy 147910000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.replacements 115622 # number of replacements
-system.iocache.tags.tagsinuse 11.298154 # Cycle average of tags in use
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-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69320.540881 # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::total 69003.914396 # average InvalidateReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 132190.734135 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 131878.695349 # average overall mshr miss latency
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+system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.520791 # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::total 0.698024 # mshr miss rate for InvalidateReq accesses
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+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69165.770374 # average InvalidateReq mshr miss latency
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system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112568.602899 # average ReadReq mshr uncacheable latency
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system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 108700 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 136788.857298 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131789.337281 # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 157986.725916 # average WriteReq mshr uncacheable latency
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-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 154929.620177 # average WriteReq mshr uncacheable latency
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system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112568.602899 # average overall mshr uncacheable latency
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system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 108700 # average overall mshr uncacheable latency
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system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 81896 # Transaction distribution
-system.membus.trans_dist::ReadResp 974121 # Transaction distribution
-system.membus.trans_dist::WriteReq 38489 # Transaction distribution
-system.membus.trans_dist::WriteResp 38489 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 1317239 # Transaction distribution
-system.membus.trans_dist::CleanEvict 246913 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 405326 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 320030 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 23 # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution
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-system.membus.trans_dist::ReadExResp 141190 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 892225 # Transaction distribution
-system.membus.trans_dist::InvalidateReq 691970 # Transaction distribution
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system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26416 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4917130 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 5066302 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237968 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 237968 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 5304270 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155794 # Cumulative packet size per connected master and slave (bytes)
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+system.membus.pkt_count_system.iocache.mem_side::total 238367 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 4648208 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155723 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52832 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 143189356 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 143398186 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7255936 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 7255936 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 150654122 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 585601 # Total snoops (count)
-system.membus.snoop_fanout::samples 4153558 # Request fanout histogram
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+system.membus.pkt_size::total 127463179 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 565217 # Total snoops (count)
+system.membus.snoop_fanout::samples 3689099 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 4153558 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 3689099 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 4153558 # Request fanout histogram
-system.membus.reqLayer0.occupancy 101297998 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 3689099 # Request fanout histogram
+system.membus.reqLayer0.occupancy 101296000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 21722999 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 20132498 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 9168141817 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 7983633356 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 5620018463 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 4606610325 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 45534588 # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy 45425919 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
-system.realview.ethernet.totBandwidth 162 # Total Bandwidth (bits/s)
+system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
-system.realview.ethernet.txBandwidth 162 # Transmit Bandwidth (bits/s)
+system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests 11339751 # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests 6165572 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests 1768705 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops 157796 # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops 143620 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops 14176 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq 81898 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 4275837 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 38489 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 38489 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty 4106250 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 2453030 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 692369 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 399393 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 1091762 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq 86 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp 86 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 305771 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 305771 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 4201160 # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq 934668 # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateResp 827940 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9127029 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7489964 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 16616993 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 227401989 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 187094309 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 414496298 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 3137723 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 8291271 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 0.336829 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.476230 # Request fanout histogram
+system.toL2Bus.snoop_filter.tot_requests 10607741 # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests 5778542 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests 1706398 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops 126357 # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops 115095 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops 11262 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.trans_dist::ReadReq 81396 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 3972795 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 38017 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 38017 # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty 3722299 # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict 2264546 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 665609 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 384259 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 1049868 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq 134 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp 134 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 281631 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 281631 # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq 3898638 # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq 910400 # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateResp 803672 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8440853 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7105433 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 15546286 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 205041299 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 177324920 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 382366219 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 2848440 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 7664337 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 0.347835 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.479358 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 5512705 66.49% 66.49% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 2764390 33.34% 99.83% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 14176 0.17% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 5009678 65.36% 65.36% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 2643397 34.49% 99.85% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 11262 0.15% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 8291271 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 8991327701 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 7664337 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 8363064932 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 2644911 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy 2585436 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 4134292430 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 3816515270 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 3690529810 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 3482933794 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
[ 0.000000] NR_IRQS:64 nr_irqs:64 0\r
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).\r
[ 0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns\r
-[ 0.000033] Console: colour dummy device 80x25\r
-[ 0.000037] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
-[ 0.000038] pid_max: default: 32768 minimum: 301\r
-[ 0.000055] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000056] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000279] hw perfevents: no hardware support available\r
-[ 0.060074] CPU1: Booted secondary processor\r
+[ 0.000032] Console: colour dummy device 80x25\r
+[ 0.000036] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
+[ 0.000037] pid_max: default: 32768 minimum: 301\r
+[ 0.000053] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
+[ 0.000054] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
+[ 0.000245] hw perfevents: no hardware support available\r
+[ 0.060065] CPU1: Booted secondary processor\r
[ 1.080104] CPU2: failed to come online\r
-[ 2.100200] CPU3: failed to come online\r
+[ 2.100199] CPU3: failed to come online\r
[ 2.100203] Brought up 2 CPUs\r
-[ 2.100205] SMP: Total of 2 processors activated.\r
-[ 2.100290] devtmpfs: initialized\r
-[ 2.100968] atomic64_test: passed\r
-[ 2.101035] regulator-dummy: no parameters\r
-[ 2.101514] NET: Registered protocol family 16\r
-[ 2.101707] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
-[ 2.101716] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
-[ 2.104213] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
-[ 2.104217] Serial: AMBA PL011 UART driver\r
-[ 2.104479] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
-[ 2.104533] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
-[ 2.105109] console [ttyAMA0] enabled\r
-[ 2.105283] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
-[ 2.105354] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
-[ 2.105426] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
-[ 2.105498] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
-[ 2.130608] 3V3: 3300 mV \r
-[ 2.130675] vgaarb: loaded\r
-[ 2.130748] SCSI subsystem initialized\r
-[ 2.130791] libata version 3.00 loaded.\r
-[ 2.130865] usbcore: registered new interface driver usbfs\r
-[ 2.130887] usbcore: registered new interface driver hub\r
-[ 2.130914] usbcore: registered new device driver usb\r
-[ 2.130950] pps_core: LinuxPPS API ver. 1 registered\r
-[ 2.130959] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
-[ 2.130980] PTP clock support registered\r
-[ 2.131163] Switched to clocksource arch_sys_counter\r
-[ 2.132599] NET: Registered protocol family 2\r
-[ 2.132709] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
-[ 2.132728] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
-[ 2.132749] TCP: Hash tables configured (established 2048 bind 2048)\r
-[ 2.132800] TCP: reno registered\r
-[ 2.132807] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 2.132821] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 2.132868] NET: Registered protocol family 1\r
-[ 2.132938] RPC: Registered named UNIX socket transport module.\r
-[ 2.132948] RPC: Registered udp transport module.\r
-[ 2.132956] RPC: Registered tcp transport module.\r
-[ 2.132965] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
-[ 2.132978] PCI: CLS 0 bytes, default 64\r
-[ 2.133199] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
-[ 2.133318] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
-[ 2.135569] fuse init (API version 7.23)\r
-[ 2.135681] msgmni has been set to 469\r
-[ 2.138493] io scheduler noop registered\r
-[ 2.138564] io scheduler cfq registered (default)\r
-[ 2.139464] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
-[ 2.139478] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
-[ 2.139490] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
-[ 2.139502] pci_bus 0000:00: root bus resource [bus 00-ff]\r
-[ 2.139513] pci_bus 0000:00: scanning bus\r
-[ 2.139526] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
-[ 2.139540] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
-[ 2.139555] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 2.139598] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
-[ 2.139610] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
-[ 2.139622] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
-[ 2.139633] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
-[ 2.139644] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
-[ 2.139655] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
-[ 2.139667] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 2.139709] pci_bus 0000:00: fixups for bus\r
-[ 2.139717] pci_bus 0000:00: bus scan returning with max=00\r
-[ 2.139730] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
-[ 2.139752] pci 0000:00:00.0: fixup irq: got 33\r
-[ 2.139761] pci 0000:00:00.0: assigning IRQ 33\r
-[ 2.139773] pci 0000:00:01.0: fixup irq: got 34\r
-[ 2.139782] pci 0000:00:01.0: assigning IRQ 34\r
-[ 2.139794] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
-[ 2.139808] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
-[ 2.139821] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
-[ 2.139835] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
-[ 2.139847] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
-[ 2.139859] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
-[ 2.139870] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
-[ 2.139882] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
-[ 2.140477] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
-[ 2.140812] ata_piix 0000:00:01.0: version 2.13\r
-[ 2.140823] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
-[ 2.140866] ata_piix 0000:00:01.0: enabling bus mastering\r
-[ 2.141222] scsi0 : ata_piix\r
-[ 2.141325] scsi1 : ata_piix\r
-[ 2.141364] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
-[ 2.141376] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
-[ 2.141528] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
-[ 2.141540] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
-[ 2.141556] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
-[ 2.141568] e1000 0000:00:00.0: enabling bus mastering\r
-[ 2.301209] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
-[ 2.301220] ata1.00: 2096640 sectors, multi 0: LBA \r
-[ 2.301250] ata1.00: configured for UDMA/33\r
-[ 2.301329] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
-[ 2.301473] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
-[ 2.301486] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
-[ 2.301562] sd 0:0:0:0: [sda] Write Protect is off\r
-[ 2.301571] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
-[ 2.301592] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
-[ 2.301766] sda: sda1\r
-[ 2.301900] sd 0:0:0:0: [sda] Attached SCSI disk\r
-[ 2.421494] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
-[ 2.421508] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
-[ 2.421533] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
-[ 2.421543] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
-[ 2.421567] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
-[ 2.421579] igb: Copyright (c) 2007-2014 Intel Corporation.\r
-[ 2.421669] usbcore: registered new interface driver usb-storage\r
-[ 2.421738] mousedev: PS/2 mouse device common for all mice\r
-[ 2.421934] usbcore: registered new interface driver usbhid\r
-[ 2.421944] usbhid: USB HID core driver\r
-[ 2.421984] TCP: cubic registered\r
-[ 2.421992] NET: Registered protocol family 17\r
-\0[ 2.422478] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
-[ 2.422519] devtmpfs: mounted\r
-[ 2.422652] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
+[ 2.100204] SMP: Total of 2 processors activated.\r
+[ 2.100286] devtmpfs: initialized\r
+[ 2.100949] atomic64_test: passed\r
+[ 2.101011] regulator-dummy: no parameters\r
+[ 2.101476] NET: Registered protocol family 16\r
+[ 2.101658] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
+[ 2.101666] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
+[ 2.103275] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
+[ 2.103279] Serial: AMBA PL011 UART driver\r
+[ 2.103525] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
+[ 2.103576] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
+[ 2.104152] console [ttyAMA0] enabled\r
+[ 2.104323] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
+[ 2.104394] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
+[ 2.104465] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
+[ 2.104535] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
+[ 2.150406] 3V3: 3300 mV \r
+[ 2.150465] vgaarb: loaded\r
+[ 2.150535] SCSI subsystem initialized\r
+[ 2.150576] libata version 3.00 loaded.\r
+[ 2.150646] usbcore: registered new interface driver usbfs\r
+[ 2.150667] usbcore: registered new interface driver hub\r
+[ 2.150693] usbcore: registered new device driver usb\r
+[ 2.150726] pps_core: LinuxPPS API ver. 1 registered\r
+[ 2.150736] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
+[ 2.150757] PTP clock support registered\r
+[ 2.150931] Switched to clocksource arch_sys_counter\r
+[ 2.152285] NET: Registered protocol family 2\r
+[ 2.152391] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
+[ 2.152411] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
+[ 2.152431] TCP: Hash tables configured (established 2048 bind 2048)\r
+[ 2.152471] TCP: reno registered\r
+[ 2.152479] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
+[ 2.152493] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
+[ 2.152538] NET: Registered protocol family 1\r
+[ 2.152603] RPC: Registered named UNIX socket transport module.\r
+[ 2.152613] RPC: Registered udp transport module.\r
+[ 2.152622] RPC: Registered tcp transport module.\r
+[ 2.152630] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
+[ 2.152643] PCI: CLS 0 bytes, default 64\r
+[ 2.152855] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
+[ 2.152973] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
+[ 2.155121] fuse init (API version 7.23)\r
+[ 2.155231] msgmni has been set to 469\r
+[ 2.157249] io scheduler noop registered\r
+[ 2.157315] io scheduler cfq registered (default)\r
+[ 2.158049] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
+[ 2.158063] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
+[ 2.158075] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
+[ 2.158088] pci_bus 0000:00: root bus resource [bus 00-ff]\r
+[ 2.158099] pci_bus 0000:00: scanning bus\r
+[ 2.158111] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
+[ 2.158125] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
+[ 2.158141] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[ 2.158181] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
+[ 2.158194] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
+[ 2.158205] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
+[ 2.158216] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
+[ 2.158227] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
+[ 2.158239] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
+[ 2.158251] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[ 2.158291] pci_bus 0000:00: fixups for bus\r
+[ 2.158300] pci_bus 0000:00: bus scan returning with max=00\r
+[ 2.158312] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
+[ 2.158334] pci 0000:00:00.0: fixup irq: got 33\r
+[ 2.158343] pci 0000:00:00.0: assigning IRQ 33\r
+[ 2.158355] pci 0000:00:01.0: fixup irq: got 34\r
+[ 2.158364] pci 0000:00:01.0: assigning IRQ 34\r
+[ 2.158377] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
+[ 2.158390] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
+[ 2.158404] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
+[ 2.158417] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
+[ 2.158429] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
+[ 2.158441] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
+[ 2.158453] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
+[ 2.158465] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
+[ 2.159060] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
+[ 2.159386] ata_piix 0000:00:01.0: version 2.13\r
+[ 2.159397] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
+[ 2.159432] ata_piix 0000:00:01.0: enabling bus mastering\r
+[ 2.159775] scsi0 : ata_piix\r
+[ 2.159868] scsi1 : ata_piix\r
+[ 2.159904] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
+[ 2.159917] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
+[ 2.160058] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
+[ 2.160070] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
+[ 2.160086] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
+[ 2.160098] e1000 0000:00:00.0: enabling bus mastering\r
+[ 2.300957] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
+[ 2.300967] ata1.00: 2096640 sectors, multi 0: LBA \r
+[ 2.300998] ata1.00: configured for UDMA/33\r
+[ 2.301069] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
+[ 2.301206] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
+[ 2.301211] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
+[ 2.301241] sd 0:0:0:0: [sda] Write Protect is off\r
+[ 2.301251] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
+[ 2.301279] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
+[ 2.301443] sda: sda1\r
+[ 2.301585] sd 0:0:0:0: [sda] Attached SCSI disk\r
+[ 2.421256] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
+[ 2.421269] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
+[ 2.421295] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
+[ 2.421306] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
+[ 2.421330] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
+[ 2.421342] igb: Copyright (c) 2007-2014 Intel Corporation.\r
+[ 2.421439] usbcore: registered new interface driver usb-storage\r
+[ 2.421506] mousedev: PS/2 mouse device common for all mice\r
+[ 2.421699] usbcore: registered new interface driver usbhid\r
+[ 2.421709] usbhid: USB HID core driver\r
+[ 2.421746] TCP: cubic registered\r
+[ 2.421755] NET: Registered protocol family 17\r
+\0[ 2.422224] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
+[ 2.422264] devtmpfs: mounted\r
+[ 2.422355] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
\0\0\rINIT: \0version 2.88 booting\0\r\r
\0Starting udev\r
-[ 2.463118] udevd[609]: starting version 182\r
+[ 2.462786] udevd[609]: starting version 182\r
Starting Bootlog daemon: bootlogd.\r\r
-[ 2.544444] random: dd urandom read with 18 bits of entropy available\r
+[ 2.544201] random: dd urandom read with 18 bits of entropy available\r
Populating dev cache\r\r
net.ipv4.conf.default.rp_filter = 1\r\r
net.ipv4.conf.all.rp_filter = 1\r\r
hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
\rINIT: Entering runlevel: 5\r\r\r
Configuring network interfaces... udhcpc (v1.21.1) started\r\r
-[ 2.681396] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
+[ 2.681165] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
Sending discover...\r\r
Sending discover...\r\r
Sending discover...\r\r
init_param=0
intel_mp_pointer=system.intel_mp_pointer
intel_mp_table=system.intel_mp_table
-kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
+kernel=/home/stever/m5/m5_system_2.0b3/binaries/x86_64-vmlinux-2.6.22.9.smp
kernel_addr_check=true
load_addr_mask=18446744073709551615
load_offset=0
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
-readfile=/z/stever/hg/gem5/tests/halt.sh
+readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
smbios_table=system.smbios_table
symbolfile=
work_begin_ckpt_count=0
use_default_range=false
width=16
default=system.pc.pci_host.pio
-master=system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist1.pio system.pc.i_dont_exist2.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.ruby.l1_cntrl0.sequencer.pio_slave_port system.ruby.l1_cntrl1.sequencer.pio_slave_port system.ruby.io_controller.dma_sequencer.slave
+master=system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist1.pio system.pc.i_dont_exist2.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.ruby.l1_cntrl0.sequencer.pio_slave_port system.ruby.l1_cntrl1.sequencer.pio_slave_port system.ruby.io_controller.dma_sequencer.slave[0]
slave=system.pc.south_bridge.io_apic.int_master system.ruby.l1_cntrl0.sequencer.pio_master_port system.ruby.l1_cntrl0.sequencer.mem_master_port system.ruby.l1_cntrl1.sequencer.pio_master_port system.ruby.l1_cntrl1.sequencer.mem_master_port
[system.mem_ctrls]
pci_func=0
pio_latency=30000
system=system
-dma=system.ruby.dma_cntrl0.dma_sequencer.slave
+dma=system.ruby.dma_cntrl0.dma_sequencer.slave[0]
pio=system.iobus.master[2]
[system.pc.south_bridge.ide.disks0]
[system.pc.south_bridge.ide.disks0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/dist/m5/system/disks/linux-x86.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-x86.img
read_only=true
[system.pc.south_bridge.ide.disks1]
[system.pc.south_bridge.ide.disks1.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img
read_only=true
[system.pc.south_bridge.int_lines0]
type=DMASequencer
clk_domain=system.ruby.clk_domain
eventq_index=0
+is_cpu_sequencer=true
+no_retry_on_stall=false
ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
system=system
using_ruby_tester=false
version=0
type=DMASequencer
clk_domain=system.ruby.clk_domain
eventq_index=0
+is_cpu_sequencer=true
+no_retry_on_stall=false
ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
system=system
using_ruby_tester=false
version=1
type=RubyCache
children=replacement_policy
assoc=2
+block_size=0
dataAccessLatency=1
dataArrayBanks=1
eventq_index=0
type=RubyCache
children=replacement_policy
assoc=2
+block_size=0
dataAccessLatency=1
dataArrayBanks=1
eventq_index=0
[system.ruby.l1_cntrl0.sequencer]
type=RubySequencer
clk_domain=system.cpu_clk_domain
+coreid=99
dcache=system.ruby.l1_cntrl0.L1Dcache
dcache_hit_latency=1
deadlock_threshold=500000
eventq_index=0
icache=system.ruby.l1_cntrl0.L1Icache
icache_hit_latency=1
+is_cpu_sequencer=true
max_outstanding_requests=16
no_retry_on_stall=false
ruby_system=system.ruby
type=RubyCache
children=replacement_policy
assoc=2
+block_size=0
dataAccessLatency=1
dataArrayBanks=1
eventq_index=0
type=RubyCache
children=replacement_policy
assoc=2
+block_size=0
dataAccessLatency=1
dataArrayBanks=1
eventq_index=0
[system.ruby.l1_cntrl1.sequencer]
type=RubySequencer
clk_domain=system.cpu_clk_domain
+coreid=99
dcache=system.ruby.l1_cntrl1.L1Dcache
dcache_hit_latency=1
deadlock_threshold=500000
eventq_index=0
icache=system.ruby.l1_cntrl1.L1Icache
icache_hit_latency=1
+is_cpu_sequencer=true
max_outstanding_requests=16
no_retry_on_stall=false
ruby_system=system.ruby
type=RubyCache
children=replacement_policy
assoc=2
+block_size=0
dataAccessLatency=1
dataArrayBanks=1
eventq_index=0
type=RubyPortProxy
clk_domain=system.clk_domain
eventq_index=0
+is_cpu_sequencer=true
no_retry_on_stall=false
ruby_system=system.ruby
support_data_reqs=true
+Redirecting stdout to build/X86_MESI_Two_Level/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/simout
+Redirecting stderr to build/X86_MESI_Two_Level/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 30 2015 02:51:00
-gem5 started Dec 30 2015 02:51:16
-gem5 executing on zizzer, pid 30304
-command line: build/X86_MESI_Two_Level/gem5.opt -d build/X86_MESI_Two_Level/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_Two_Level -re /z/stever/hg/gem5/tests/run.py build/X86_MESI_Two_Level/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_Two_Level
+gem5 compiled Mar 15 2016 21:26:21
+gem5 started Mar 15 2016 21:35:42
+gem5 executing on phenom, pid 15979
+command line: build/X86_MESI_Two_Level/gem5.opt -d build/X86_MESI_Two_Level/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_Two_Level -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86_MESI_Two_Level/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_Two_Level
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
+info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/x86_64-vmlinux-2.6.22.9.smp
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 5221333868500 because m5_exit instruction encountered
+Exiting @ tick 5220166723500 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 5.221334 # Number of seconds simulated
-sim_ticks 5221333868500 # Number of ticks simulated
-final_tick 5221333868500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 5.220167 # Number of seconds simulated
+sim_ticks 5220166723500 # Number of ticks simulated
+final_tick 5220166723500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 231127 # Simulator instruction rate (inst/s)
-host_op_rate 448792 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 7989012150 # Simulator tick rate (ticks/s)
-host_mem_usage 840496 # Number of bytes of host memory used
-host_seconds 653.56 # Real time elapsed on the host
-sim_insts 151056351 # Number of instructions simulated
-sim_ops 293314763 # Number of ops (including micro ops) simulated
+host_inst_rate 149296 # Simulator instruction rate (inst/s)
+host_op_rate 289896 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 5158950187 # Simulator tick rate (ticks/s)
+host_mem_usage 785372 # Number of bytes of host memory used
+host_seconds 1011.87 # Real time elapsed on the host
+sim_insts 151067812 # Number of instructions simulated
+sim_ops 293336428 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0 11629312 # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total 11629312 # Number of bytes read from this memory
-system.mem_ctrls.bytes_written::ruby.dir_cntrl0 9426176 # Number of bytes written to this memory
-system.mem_ctrls.bytes_written::total 9426176 # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0 181708 # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total 181708 # Number of read requests responded to by this memory
-system.mem_ctrls.num_writes::ruby.dir_cntrl0 147284 # Number of write requests responded to by this memory
-system.mem_ctrls.num_writes::total 147284 # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 2227268 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 2227268 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0 1805320 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total 1805320 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0 4032588 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 4032588 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs 181708 # Number of read requests accepted
-system.mem_ctrls.writeReqs 147284 # Number of write requests accepted
-system.mem_ctrls.readBursts 181708 # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts 147284 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM 11602432 # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ 26880 # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten 9421952 # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys 11629312 # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys 9426176 # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ 420 # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts 38 # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.bytes_read::ruby.dir_cntrl0 11621312 # Number of bytes read from this memory
+system.mem_ctrls.bytes_read::total 11621312 # Number of bytes read from this memory
+system.mem_ctrls.bytes_written::ruby.dir_cntrl0 9422976 # Number of bytes written to this memory
+system.mem_ctrls.bytes_written::total 9422976 # Number of bytes written to this memory
+system.mem_ctrls.num_reads::ruby.dir_cntrl0 181583 # Number of read requests responded to by this memory
+system.mem_ctrls.num_reads::total 181583 # Number of read requests responded to by this memory
+system.mem_ctrls.num_writes::ruby.dir_cntrl0 147234 # Number of write requests responded to by this memory
+system.mem_ctrls.num_writes::total 147234 # Number of write requests responded to by this memory
+system.mem_ctrls.bw_read::ruby.dir_cntrl0 2226234 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total 2226234 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0 1805110 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total 1805110 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0 4031344 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total 4031344 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.readReqs 181583 # Number of read requests accepted
+system.mem_ctrls.writeReqs 147234 # Number of write requests accepted
+system.mem_ctrls.readBursts 181583 # Number of DRAM read bursts, including those serviced by the write queue
+system.mem_ctrls.writeBursts 147234 # Number of DRAM write bursts, including those merged in the write queue
+system.mem_ctrls.bytesReadDRAM 11591808 # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ 29504 # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten 9419008 # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadSys 11621312 # Total read bytes from the system interface side
+system.mem_ctrls.bytesWrittenSys 9422976 # Total written bytes from the system interface side
+system.mem_ctrls.servicedByWrQ 461 # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts 33 # Number of DRAM write bursts merged with an existing one
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0 11314 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1 10807 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2 10914 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3 11597 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4 11232 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::5 10764 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::6 11927 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::7 10886 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::8 12498 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::9 12229 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::10 11811 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::11 12012 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::12 11054 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::13 10768 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::14 10808 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::15 10667 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0 10064 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1 9271 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2 8835 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3 9280 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4 9017 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::5 9023 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::6 9283 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::0 11329 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::1 10774 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::2 10935 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::3 11505 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::4 11170 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::5 10899 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::6 11836 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::7 10884 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::8 12484 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::9 12159 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::10 11756 # Per bank write bursts
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system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 5221333759000 # Total gap between requests
+system.mem_ctrls.totGap 5220166614000 # Total gap between requests
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
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-system.mem_ctrls.bytesPerActivate::samples 59929 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 350.820471 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 206.478602 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 350.358122 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127 19905 33.21% 33.21% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255 13767 22.97% 56.19% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383 6125 10.22% 66.41% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511 3674 6.13% 72.54% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639 2562 4.28% 76.81% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767 2015 3.36% 80.17% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895 1654 2.76% 82.93% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 1396 2.33% 85.26% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151 8831 14.74% 100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total 59929 # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples 8213 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean 22.069159 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev 311.468449 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::0-1023 8207 99.93% 99.93% # Reads before turning the bus around for writes
+system.mem_ctrls.bytesPerActivate::samples 59923 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean 350.629174 # Bytes accessed per row activation
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+system.mem_ctrls.bytesPerActivate::stdev 350.561474 # Bytes accessed per row activation
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+system.mem_ctrls.bytesPerActivate::384-511 3634 6.06% 72.55% # Bytes accessed per row activation
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+system.mem_ctrls.bytesPerActivate::1024-1151 8841 14.75% 100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total 59923 # Bytes accessed per row activation
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+system.mem_ctrls.rdPerTurnAround::mean 22.065919 # Reads before turning the bus around for writes
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system.mem_ctrls.rdPerTurnAround::1024-2047 3 0.04% 99.96% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::10240-11263 1 0.01% 99.99% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::25600-26623 1 0.01% 100.00% # Reads before turning the bus around for writes
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-system.mem_ctrls.wrPerTurnAround::16 6150 74.88% 74.88% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::17 17 0.21% 75.09% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18 147 1.79% 76.88% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::19 19 0.23% 77.11% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::20 39 0.47% 77.58% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::21 480 5.84% 83.43% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::22 195 2.37% 85.80% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::23 58 0.71% 86.51% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::24 616 7.50% 94.01% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::25 111 1.35% 95.36% # Writes before turning the bus around for reads
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-system.mem_ctrls.wrPerTurnAround::27 13 0.16% 95.59% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::28 281 3.42% 99.01% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::29 5 0.06% 99.07% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::30 6 0.07% 99.15% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::31 4 0.05% 99.20% # Writes before turning the bus around for reads
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-system.mem_ctrls.wrPerTurnAround::34 1 0.01% 99.34% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::35 1 0.01% 99.35% # Writes before turning the bus around for reads
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system.mem_ctrls.wrPerTurnAround::50 1 0.01% 99.95% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::51 4 0.05% 100.00% # Writes before turning the bus around for reads
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-system.mem_ctrls.totQLat 1928702995 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 5327852995 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat 906440000 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 10638.89 # Average queueing delay per DRAM burst
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+system.mem_ctrls.totQLat 1926054246 # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat 5322091746 # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat 905610000 # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat 10634.02 # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 29388.89 # Average memory access latency per DRAM burst
+system.mem_ctrls.avgMemAccLat 29384.02 # Average memory access latency per DRAM burst
system.mem_ctrls.avgRdBW 2.22 # Average DRAM read bandwidth in MiByte/s
system.mem_ctrls.avgWrBW 1.80 # Average achieved write bandwidth in MiByte/s
system.mem_ctrls.avgRdBWSys 2.23 # Average system read bandwidth in MiByte/s
system.mem_ctrls.busUtilWrite 0.01 # Data bus utilization in percentage for writes
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
system.mem_ctrls.avgWrQLen 25.93 # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits 146985 # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits 121591 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 81.08 # Row buffer hit rate for reads
+system.mem_ctrls.readRowHits 146815 # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits 121555 # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate 81.06 # Row buffer hit rate for reads
system.mem_ctrls.writeRowHitRate 82.58 # Row buffer hit rate for writes
-system.mem_ctrls.avgGap 15870701.29 # Average gap between requests
-system.mem_ctrls.pageHitRate 81.75 # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy 222112800 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy 121192500 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy 697632000 # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy 474063840 # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy 341031690480 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy 139634929485 # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy 3010309497750 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy 3492491118855 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 668.889543 # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE 5007813786500 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::REF 174351580000 # Time in different power states
+system.mem_ctrls.avgGap 15875598.32 # Average gap between requests
+system.mem_ctrls.pageHitRate 81.74 # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy 222014520 # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy 121138875 # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy 696781800 # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy 474647040 # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.refreshEnergy 340955406480 # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy 139500530325 # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy 3009726629250 # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.totalEnergy 3491697148290 # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower 668.887101 # Core power per rank (mW)
+system.mem_ctrls_0.memoryStateTime::IDLE 5006844557250 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::REF 174312580000 # Time in different power states
system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT 39168401500 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT 39009485750 # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.mem_ctrls_1.actEnergy 230950440 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy 126014625 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy 716406600 # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy 479908800 # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy 341031690480 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy 139433194800 # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy 3010486458000 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy 3492504623745 # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower 668.892130 # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE 5008096006750 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::REF 174351580000 # Time in different power states
+system.mem_ctrls_1.actEnergy 231003360 # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy 126043500 # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy 715962000 # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy 479027520 # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.refreshEnergy 340955406480 # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy 139411599210 # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy 3009804639000 # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.totalEnergy 3491723681070 # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower 668.892184 # Core power per rank (mW)
+system.mem_ctrls_1.memoryStateTime::IDLE 5006961679500 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::REF 174312580000 # Time in different power states
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT 38879557000 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT 38884946750 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks
-system.cpu0.numCycles 10442667737 # number of cpu cycles simulated
+system.cpu0.numCycles 10440333447 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu0.committedInsts 100536787 # Number of instructions committed
-system.cpu0.committedOps 194797820 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 182088728 # Number of integer alu accesses
+system.cpu0.committedInsts 100619599 # Number of instructions committed
+system.cpu0.committedOps 194912227 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 182208047 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 48 # Number of float alu accesses
-system.cpu0.num_func_calls 1786032 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 17861747 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 182088728 # number of integer instructions
+system.cpu0.num_func_calls 1789060 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 17876463 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 182208047 # number of integer instructions
system.cpu0.num_fp_insts 48 # number of float instructions
-system.cpu0.num_int_register_reads 340615084 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 155370018 # number of times the integer registers were written
+system.cpu0.num_int_register_reads 340866599 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 155423898 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 48 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 104545129 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 75102334 # number of times the CC registers were written
-system.cpu0.num_mem_refs 18441276 # number of memory refs
-system.cpu0.num_load_insts 11598405 # Number of load instructions
-system.cpu0.num_store_insts 6842871 # Number of store instructions
-system.cpu0.num_idle_cycles 9945199528.030096 # Number of idle cycles
-system.cpu0.num_busy_cycles 497468208.969905 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.047638 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.952362 # Percentage of idle cycles
-system.cpu0.Branches 20259444 # Number of branches fetched
-system.cpu0.op_class::No_OpClass 186601 0.10% 0.10% # Class of executed instruction
-system.cpu0.op_class::IntAlu 175972167 90.34% 90.43% # Class of executed instruction
-system.cpu0.op_class::IntMult 117562 0.06% 90.49% # Class of executed instruction
-system.cpu0.op_class::IntDiv 85295 0.04% 90.54% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 0 0.00% 90.54% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 0 0.00% 90.54% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 16 0.00% 90.54% # Class of executed instruction
-system.cpu0.op_class::FloatMult 0 0.00% 90.54% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 0 0.00% 90.54% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 90.54% # Class of executed instruction
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-system.cpu0.op_class::SimdAddAcc 0 0.00% 90.54% # Class of executed instruction
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-system.cpu0.op_class::SimdMisc 0 0.00% 90.54% # Class of executed instruction
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-system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.54% # Class of executed instruction
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-system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.54% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.54% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult 0 0.00% 90.54% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.54% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.54% # Class of executed instruction
-system.cpu0.op_class::MemRead 11594261 5.95% 96.49% # Class of executed instruction
-system.cpu0.op_class::MemWrite 6842871 3.51% 100.00% # Class of executed instruction
+system.cpu0.num_cc_register_reads 104641558 # number of times the CC registers were read
+system.cpu0.num_cc_register_writes 75150612 # number of times the CC registers were written
+system.cpu0.num_mem_refs 18466644 # number of memory refs
+system.cpu0.num_load_insts 11577076 # Number of load instructions
+system.cpu0.num_store_insts 6889568 # Number of store instructions
+system.cpu0.num_idle_cycles 9942379374.520096 # Number of idle cycles
+system.cpu0.num_busy_cycles 497954072.479905 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.047695 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.952305 # Percentage of idle cycles
+system.cpu0.Branches 20277624 # Number of branches fetched
+system.cpu0.op_class::No_OpClass 187137 0.10% 0.10% # Class of executed instruction
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+system.cpu0.op_class::FloatAdd 0 0.00% 90.53% # Class of executed instruction
+system.cpu0.op_class::FloatCmp 0 0.00% 90.53% # Class of executed instruction
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+system.cpu0.op_class::FloatMult 0 0.00% 90.53% # Class of executed instruction
+system.cpu0.op_class::FloatDiv 0 0.00% 90.53% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt 0 0.00% 90.53% # Class of executed instruction
+system.cpu0.op_class::SimdAdd 0 0.00% 90.53% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc 0 0.00% 90.53% # Class of executed instruction
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+system.cpu0.op_class::SimdMisc 0 0.00% 90.53% # Class of executed instruction
+system.cpu0.op_class::SimdMult 0 0.00% 90.53% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc 0 0.00% 90.53% # Class of executed instruction
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+system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.53% # Class of executed instruction
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+system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.53% # Class of executed instruction
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+system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.53% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.53% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.53% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult 0 0.00% 90.53% # Class of executed instruction
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+system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.53% # Class of executed instruction
+system.cpu0.op_class::MemRead 11572910 5.94% 96.47% # Class of executed instruction
+system.cpu0.op_class::MemWrite 6889568 3.53% 100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 194798773 # Class of executed instruction
+system.cpu0.op_class::total 194913158 # Class of executed instruction
system.cpu1.apic_clk_domain.clock 8000 # Clock period in ticks
-system.cpu1.numCycles 10442335269 # number of cpu cycles simulated
+system.cpu1.numCycles 10439192066 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu1.committedInsts 50519564 # Number of instructions committed
-system.cpu1.committedOps 98516943 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 91922966 # Number of integer alu accesses
+system.cpu1.committedInsts 50448213 # Number of instructions committed
+system.cpu1.committedOps 98424201 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 91824874 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 48 # Number of float alu accesses
-system.cpu1.num_func_calls 994306 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 9151218 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 91922966 # number of integer instructions
+system.cpu1.num_func_calls 991908 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 9137643 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 91824874 # number of integer instructions
system.cpu1.num_fp_insts 48 # number of float instructions
-system.cpu1.num_int_register_reads 171998815 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 78483807 # number of times the integer registers were written
+system.cpu1.num_int_register_reads 171791517 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 78447804 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 48 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 52229792 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 37031955 # number of times the CC registers were written
-system.cpu1.num_mem_refs 8648347 # number of memory refs
-system.cpu1.num_load_insts 5505950 # Number of load instructions
-system.cpu1.num_store_insts 3142397 # Number of store instructions
-system.cpu1.num_idle_cycles 10281378678.091957 # Number of idle cycles
-system.cpu1.num_busy_cycles 160956590.908042 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.015414 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.984586 # Percentage of idle cycles
-system.cpu1.Branches 10509145 # Number of branches fetched
-system.cpu1.op_class::No_OpClass 118838 0.12% 0.12% # Class of executed instruction
-system.cpu1.op_class::IntAlu 89646727 91.00% 91.12% # Class of executed instruction
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-system.cpu1.op_class::IntDiv 39449 0.04% 91.23% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 0 0.00% 91.23% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 0 0.00% 91.23% # Class of executed instruction
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-system.cpu1.op_class::FloatMult 0 0.00% 91.23% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 0 0.00% 91.23% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 91.23% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 91.23% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 91.23% # Class of executed instruction
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-system.cpu1.op_class::SimdMisc 0 0.00% 91.23% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 91.23% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 91.23% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 91.23% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 91.23% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 91.23% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 0 0.00% 91.23% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 91.23% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 0 0.00% 91.23% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 0 0.00% 91.23% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 91.23% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 0 0.00% 91.23% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 91.23% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 91.23% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 91.23% # Class of executed instruction
-system.cpu1.op_class::MemRead 5501755 5.58% 96.81% # Class of executed instruction
-system.cpu1.op_class::MemWrite 3142397 3.19% 100.00% # Class of executed instruction
+system.cpu1.num_cc_register_reads 52143431 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 36991088 # number of times the CC registers were written
+system.cpu1.num_mem_refs 8627580 # number of memory refs
+system.cpu1.num_load_insts 5530314 # Number of load instructions
+system.cpu1.num_store_insts 3097266 # Number of store instructions
+system.cpu1.num_idle_cycles 10278680276.738028 # Number of idle cycles
+system.cpu1.num_busy_cycles 160511789.261972 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.015376 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.984624 # Percentage of idle cycles
+system.cpu1.Branches 10492962 # Number of branches fetched
+system.cpu1.op_class::No_OpClass 118368 0.12% 0.12% # Class of executed instruction
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+system.cpu1.op_class::FloatMult 0 0.00% 91.24% # Class of executed instruction
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+system.cpu1.op_class::SimdAdd 0 0.00% 91.24% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc 0 0.00% 91.24% # Class of executed instruction
+system.cpu1.op_class::SimdAlu 0 0.00% 91.24% # Class of executed instruction
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+system.cpu1.op_class::SimdMisc 0 0.00% 91.24% # Class of executed instruction
+system.cpu1.op_class::SimdMult 0 0.00% 91.24% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc 0 0.00% 91.24% # Class of executed instruction
+system.cpu1.op_class::SimdShift 0 0.00% 91.24% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc 0 0.00% 91.24% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt 0 0.00% 91.24% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd 0 0.00% 91.24% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu 0 0.00% 91.24% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp 0 0.00% 91.24% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt 0 0.00% 91.24% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv 0 0.00% 91.24% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 0 0.00% 91.24% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult 0 0.00% 91.24% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 91.24% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt 0 0.00% 91.24% # Class of executed instruction
+system.cpu1.op_class::MemRead 5526131 5.61% 96.85% # Class of executed instruction
+system.cpu1.op_class::MemWrite 3097266 3.15% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 98517583 # Class of executed instruction
-system.iobus.trans_dist::ReadReq 883857 # Transaction distribution
-system.iobus.trans_dist::ReadResp 883857 # Transaction distribution
-system.iobus.trans_dist::WriteReq 36766 # Transaction distribution
-system.iobus.trans_dist::WriteResp 36766 # Transaction distribution
-system.iobus.trans_dist::MessageReq 1833 # Transaction distribution
-system.iobus.trans_dist::MessageResp 1833 # Transaction distribution
+system.cpu1.op_class::total 98424862 # Class of executed instruction
+system.iobus.trans_dist::ReadReq 883871 # Transaction distribution
+system.iobus.trans_dist::ReadResp 883871 # Transaction distribution
+system.iobus.trans_dist::WriteReq 36792 # Transaction distribution
+system.iobus.trans_dist::WriteResp 36792 # Transaction distribution
+system.iobus.trans_dist::MessageReq 1835 # Transaction distribution
+system.iobus.trans_dist::MessageResp 1835 # Transaction distribution
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1736 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 1682 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3418 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 6154 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 6166 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 712 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 74 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 38 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 917434 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 1422 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 1234 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 90 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 14468 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 811270 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 178 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 14088 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 811278 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pci_host.pio 2214 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1754122 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1753576 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 4888 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 4922 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 652 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 31650 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 676 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 876 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 31738 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 12896 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 13284 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 70 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 4614 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 72 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 4620 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.pci_host.pio 92 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 87372 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 1844912 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 88002 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 1844996 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 3472 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 3364 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6836 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3500 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3506 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 356 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 37 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 19 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 458717 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 2844 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 2468 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 45 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 7234 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1622534 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 356 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 7044 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1622550 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 360 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pci_host.pio 4401 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 2100077 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 2099537 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3160 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3180 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 326 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 15825 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 1352 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 1752 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 15869 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 6448 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 6642 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 140 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 9225 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 144 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 9237 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.pci_host.pio 72 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 52465 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 2159378 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 53095 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 2159468 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 43000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 7500 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 9037000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy 9083500 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 944500 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 458718000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer8.occupancy 1770984 # Layer occupancy (ticks)
+system.iobus.reqLayer8.occupancy 1783484 # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer9.occupancy 31828500 # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 11500 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer17.occupancy 410369779 # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy 410414499 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer18.occupancy 7666639 # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy 7700146 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 1751500 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 2482464 # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy 2638190 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer2.occupancy 1948163500 # Layer occupancy (ticks)
+system.iobus.respLayer2.occupancy 1947717500 # Layer occupancy (ticks)
system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer4.occupancy 60411500 # Layer occupancy (ticks)
+system.iobus.respLayer4.occupancy 60917000 # Layer occupancy (ticks)
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_txs 30 # Number of DMA read transactions (not PRD).
+system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes 2987008 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
system.ruby.clk_domain.clock 500 # Clock period in ticks
system.ruby.delayHist::bucket_size 4 # delay histogram for all message
system.ruby.delayHist::max_bucket 39 # delay histogram for all message
-system.ruby.delayHist::samples 11180898 # delay histogram for all message
-system.ruby.delayHist::mean 0.431734 # delay histogram for all message
-system.ruby.delayHist::stdev 1.809496 # delay histogram for all message
-system.ruby.delayHist | 10578004 94.61% 94.61% | 2065 0.02% 94.63% | 600258 5.37% 99.99% | 191 0.00% 100.00% | 301 0.00% 100.00% | 12 0.00% 100.00% | 64 0.00% 100.00% | 2 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
-system.ruby.delayHist::total 11180898 # delay histogram for all message
+system.ruby.delayHist::samples 11184165 # delay histogram for all message
+system.ruby.delayHist::mean 0.431974 # delay histogram for all message
+system.ruby.delayHist::stdev 1.810021 # delay histogram for all message
+system.ruby.delayHist | 10580766 94.60% 94.60% | 2101 0.02% 94.62% | 600708 5.37% 99.99% | 188 0.00% 100.00% | 323 0.00% 100.00% | 9 0.00% 100.00% | 67 0.00% 100.00% | 2 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
+system.ruby.delayHist::total 11184165 # delay histogram for all message
system.ruby.outstanding_req_hist_seqr::bucket_size 1
system.ruby.outstanding_req_hist_seqr::max_bucket 9
-system.ruby.outstanding_req_hist_seqr::samples 197955008
+system.ruby.outstanding_req_hist_seqr::samples 197976054
system.ruby.outstanding_req_hist_seqr::mean 1.000129
system.ruby.outstanding_req_hist_seqr::gmean 1.000089
-system.ruby.outstanding_req_hist_seqr::stdev 0.011356
-system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 197929478 99.99% 99.99% | 25530 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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system.ruby.latency_hist_seqr::max_bucket 1279
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system.ruby.hit_latency_hist_seqr::max_bucket 9
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system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made
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system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages
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system.ruby.l1_cntrl1.prefetcher.miss_observed 0 # number of misses observed
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system.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
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system.ruby.network.routers4.throttle0.link_utilization 0.000259
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system.ruby.network.routers4.throttle1.link_utilization 0.000228
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system.ruby.network.routers5.throttle0.link_utilization 0
system.ruby.network.routers5.throttle1.link_utilization 0
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system.ruby.network.routers6.throttle4.link_utilization 0.000259
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system.ruby.network.routers6.throttle4.msg_count.Writeback_Control::1 46736
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system.ruby.network.routers6.throttle4.msg_bytes.Writeback_Control::1 373888
system.ruby.network.routers6.throttle5.link_utilization 0
system.ruby.delayVCHist.vnet_0::bucket_size 4 # delay histogram for vnet_0
system.ruby.delayVCHist.vnet_0::max_bucket 39 # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::samples 6276167 # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::mean 0.731662 # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::stdev 2.309437 # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0 | 5702991 90.87% 90.87% | 569 0.01% 90.88% | 572047 9.11% 99.99% | 186 0.00% 99.99% | 295 0.00% 100.00% | 12 0.00% 100.00% | 64 0.00% 100.00% | 2 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::total 6276167 # delay histogram for vnet_0
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+system.ruby.delayVCHist.vnet_0::mean 0.731657 # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::stdev 2.309527 # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0 | 5704590 90.87% 90.87% | 579 0.01% 90.88% | 572160 9.11% 99.99% | 182 0.00% 99.99% | 317 0.01% 100.00% | 9 0.00% 100.00% | 67 0.00% 100.00% | 2 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::total 6277907 # delay histogram for vnet_0
system.ruby.delayVCHist.vnet_1::bucket_size 2 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::max_bucket 19 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::samples 4817745 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::mean 0.048807 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::stdev 0.619369 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1 | 4787452 99.37% 99.37% | 575 0.01% 99.38% | 658 0.01% 99.40% | 838 0.02% 99.41% | 27971 0.58% 99.99% | 240 0.00% 100.00% | 4 0.00% 100.00% | 1 0.00% 100.00% | 3 0.00% 100.00% | 3 0.00% 100.00% # delay histogram for vnet_1
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+system.ruby.delayVCHist.vnet_1::mean 0.049390 # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::stdev 0.622960 # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1 | 4787836 99.36% 99.36% | 592 0.01% 99.38% | 677 0.01% 99.39% | 845 0.02% 99.41% | 28317 0.59% 99.99% | 231 0.00% 100.00% | 4 0.00% 100.00% | 2 0.00% 100.00% | 3 0.00% 100.00% | 3 0.00% 100.00% # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::total 4818510 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2
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-system.ruby.delayVCHist.vnet_2::mean 0.000069 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::stdev 0.011745 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2 | 86983 100.00% 100.00% | 0 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
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system.ruby.LD.latency_hist_seqr::bucket_size 128
system.ruby.LD.latency_hist_seqr::max_bucket 1279
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system.ruby.LD.hit_latency_hist_seqr::bucket_size 1
system.ruby.LD.hit_latency_hist_seqr::max_bucket 9
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system.ruby.LD.hit_latency_hist_seqr::mean 1
system.ruby.LD.hit_latency_hist_seqr::gmean 1
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system.ruby.LD.miss_latency_hist_seqr::bucket_size 128
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system.ruby.ST.latency_hist_seqr::bucket_size 128
system.ruby.ST.latency_hist_seqr::max_bucket 1279
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system.ruby.ST.hit_latency_hist_seqr::bucket_size 1
system.ruby.ST.hit_latency_hist_seqr::max_bucket 9
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system.ruby.ST.hit_latency_hist_seqr::mean 1
system.ruby.ST.hit_latency_hist_seqr::gmean 1
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system.ruby.IFETCH.latency_hist_seqr::bucket_size 128
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system.ruby.IFETCH.hit_latency_hist_seqr::mean 1
system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1
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system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 128
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system.ruby.Locked_RMW_Read.hit_latency_hist_seqr::bucket_size 1
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system.ruby.Locked_RMW_Read.hit_latency_hist_seqr::gmean 1
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system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::bucket_size 64
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system.ruby.Locked_RMW_Write.latency_hist_seqr::bucket_size 1
system.ruby.Locked_RMW_Write.latency_hist_seqr::max_bucket 9
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system.ruby.Locked_RMW_Write.latency_hist_seqr::mean 1
system.ruby.Locked_RMW_Write.latency_hist_seqr::gmean 1
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system.ruby.Locked_RMW_Write.hit_latency_hist_seqr::bucket_size 1
system.ruby.Locked_RMW_Write.hit_latency_hist_seqr::max_bucket 9
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system.ruby.Locked_RMW_Write.hit_latency_hist_seqr::mean 1
system.ruby.Locked_RMW_Write.hit_latency_hist_seqr::gmean 1
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-system.ruby.Directory_Controller.Data 103288 0.00% 0.00%
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system.ruby.Directory_Controller.DMA_WRITE 46736 0.00% 0.00%
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system.ruby.DMA_Controller.WriteRequest | 46736 100.00% 100.00% | 0 0.00% 100.00%
system.ruby.DMA_Controller.WriteRequest::total 46736
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system.ruby.DMA_Controller.Ack | 46736 100.00% 100.00% | 0 0.00% 100.00%
system.ruby.DMA_Controller.Ack::total 46736
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system.ruby.DMA_Controller.READY.WriteRequest | 46736 100.00% 100.00% | 0 0.00% 100.00%
system.ruby.DMA_Controller.READY.WriteRequest::total 46736
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system.ruby.DMA_Controller.BUSY_WR.Ack | 46736 100.00% 100.00% | 0 0.00% 100.00%
system.ruby.DMA_Controller.BUSY_WR.Ack::total 46736
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system.ruby.L1Cache_Controller.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00%
system.ruby.L1Cache_Controller.Fwd_GET_INSTR::total 4
-system.ruby.L1Cache_Controller.Data | 528 32.39% 32.39% | 1102 67.61% 100.00%
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-system.ruby.L1Cache_Controller.Ack | 12680 52.16% 52.16% | 11631 47.84% 100.00%
-system.ruby.L1Cache_Controller.Ack::total 24311
-system.ruby.L1Cache_Controller.Ack_all | 13208 50.92% 50.92% | 12733 49.08% 100.00%
-system.ruby.L1Cache_Controller.Ack_all::total 25941
-system.ruby.L1Cache_Controller.WB_Ack | 1129939 64.87% 64.87% | 611895 35.13% 100.00%
-system.ruby.L1Cache_Controller.WB_Ack::total 1741834
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-system.ruby.L1Cache_Controller.NP.Load::total 1412614
-system.ruby.L1Cache_Controller.NP.Ifetch | 550890 67.18% 67.18% | 269077 32.82% 100.00%
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-system.ruby.L1Cache_Controller.NP.Store | 298763 70.81% 70.81% | 123170 29.19% 100.00%
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-system.ruby.L1Cache_Controller.S.Store | 12680 52.16% 52.16% | 11632 47.84% 100.00%
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-system.ruby.L1Cache_Controller.M.Load | 6055780 67.95% 67.95% | 2855682 32.05% 100.00%
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-system.ruby.L1Cache_Controller.M.Fwd_GETS | 13658 53.96% 53.96% | 11652 46.04% 100.00%
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+system.ruby.L1Cache_Controller.Data | 521 31.46% 31.46% | 1135 68.54% 100.00%
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system.ruby.L1Cache_Controller.M.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00%
system.ruby.L1Cache_Controller.M.Fwd_GET_INSTR::total 4
-system.ruby.L1Cache_Controller.IS.Data_Exclusive | 840528 62.87% 62.87% | 496439 37.13% 100.00%
-system.ruby.L1Cache_Controller.IS.Data_Exclusive::total 1336967
-system.ruby.L1Cache_Controller.IS.DataS_fromL1 | 12824 46.66% 46.66% | 14661 53.34% 100.00%
-system.ruby.L1Cache_Controller.IS.DataS_fromL1::total 27485
-system.ruby.L1Cache_Controller.IS.Data_all_Acks | 589280 66.24% 66.24% | 300325 33.76% 100.00%
-system.ruby.L1Cache_Controller.IS.Data_all_Acks::total 889605
-system.ruby.L1Cache_Controller.IM.Data | 528 32.39% 32.39% | 1102 67.61% 100.00%
-system.ruby.L1Cache_Controller.IM.Data::total 1630
-system.ruby.L1Cache_Controller.IM.Data_all_Acks | 303947 70.36% 70.36% | 128024 29.64% 100.00%
-system.ruby.L1Cache_Controller.IM.Data_all_Acks::total 431971
-system.ruby.L1Cache_Controller.SM.Inv | 0 0.00% 0.00% | 1 100.00% 100.00%
-system.ruby.L1Cache_Controller.SM.Inv::total 1
-system.ruby.L1Cache_Controller.SM.Ack | 12680 52.16% 52.16% | 11631 47.84% 100.00%
-system.ruby.L1Cache_Controller.SM.Ack::total 24311
-system.ruby.L1Cache_Controller.SM.Ack_all | 13208 50.92% 50.92% | 12733 49.08% 100.00%
-system.ruby.L1Cache_Controller.SM.Ack_all::total 25941
-system.ruby.L1Cache_Controller.M_I.Ifetch | 4 80.00% 80.00% | 1 20.00% 100.00%
-system.ruby.L1Cache_Controller.M_I.Ifetch::total 5
-system.ruby.L1Cache_Controller.M_I.WB_Ack | 1129939 64.87% 64.87% | 611895 35.13% 100.00%
-system.ruby.L1Cache_Controller.M_I.WB_Ack::total 1741834
-system.ruby.L2Cache_Controller.L1_GET_INSTR 820271 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_GETS 1434178 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_GETX 433604 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_UPGRADE 24312 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_PUTX 1741834 0.00% 0.00%
-system.ruby.L2Cache_Controller.L2_Replacement 100151 0.00% 0.00%
-system.ruby.L2Cache_Controller.L2_Replacement_clean 13512 0.00% 0.00%
-system.ruby.L2Cache_Controller.Mem_Data 181234 0.00% 0.00%
-system.ruby.L2Cache_Controller.Mem_Ack 116748 0.00% 0.00%
-system.ruby.L2Cache_Controller.WB_Data 25808 0.00% 0.00%
-system.ruby.L2Cache_Controller.WB_Data_clean 2171 0.00% 0.00%
-system.ruby.L2Cache_Controller.Ack 1865 0.00% 0.00%
-system.ruby.L2Cache_Controller.Ack_all 7090 0.00% 0.00%
-system.ruby.L2Cache_Controller.Unblock 27485 0.00% 0.00%
-system.ruby.L2Cache_Controller.Exclusive_Unblock 1794879 0.00% 0.00%
-system.ruby.L2Cache_Controller.MEM_Inv 6170 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 15428 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETS 32321 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETX 133485 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.L1_GET_INSTR 804813 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.L1_GETS 69338 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.L1_GETX 1923 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.L1_UPGRADE 24311 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.L2_Replacement 291 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 6674 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.Inv | 1 100.00% 100.00% | 0 0.00% 100.00%
+system.ruby.L1Cache_Controller.IS.Inv::total 1
+system.ruby.L1Cache_Controller.IS.Data_Exclusive | 836671 62.58% 62.58% | 500206 37.42% 100.00%
+system.ruby.L1Cache_Controller.IS.Data_Exclusive::total 1336877
+system.ruby.L1Cache_Controller.IS.DataS_fromL1 | 13038 46.86% 46.86% | 14784 53.14% 100.00%
+system.ruby.L1Cache_Controller.IS.DataS_fromL1::total 27822
+system.ruby.L1Cache_Controller.IS.Data_all_Acks | 587563 66.02% 66.02% | 302388 33.98% 100.00%
+system.ruby.L1Cache_Controller.IS.Data_all_Acks::total 889951
+system.ruby.L1Cache_Controller.IM.Data | 521 31.46% 31.46% | 1135 68.54% 100.00%
+system.ruby.L1Cache_Controller.IM.Data::total 1656
+system.ruby.L1Cache_Controller.IM.Data_all_Acks | 305196 70.62% 70.62% | 126971 29.38% 100.00%
+system.ruby.L1Cache_Controller.IM.Data_all_Acks::total 432167
+system.ruby.L1Cache_Controller.SM.Inv | 2 40.00% 40.00% | 3 60.00% 100.00%
+system.ruby.L1Cache_Controller.SM.Inv::total 5
+system.ruby.L1Cache_Controller.SM.Ack | 12812 52.14% 52.14% | 11761 47.86% 100.00%
+system.ruby.L1Cache_Controller.SM.Ack::total 24573
+system.ruby.L1Cache_Controller.SM.Ack_all | 13333 50.83% 50.83% | 12896 49.17% 100.00%
+system.ruby.L1Cache_Controller.SM.Ack_all::total 26229
+system.ruby.L1Cache_Controller.IS_I.DataS_fromL1 | 1 100.00% 100.00% | 0 0.00% 100.00%
+system.ruby.L1Cache_Controller.IS_I.DataS_fromL1::total 1
+system.ruby.L1Cache_Controller.M_I.Ifetch | 4 66.67% 66.67% | 2 33.33% 100.00%
+system.ruby.L1Cache_Controller.M_I.Ifetch::total 6
+system.ruby.L1Cache_Controller.M_I.Fwd_GETX | 0 0.00% 0.00% | 1 100.00% 100.00%
+system.ruby.L1Cache_Controller.M_I.Fwd_GETX::total 1
+system.ruby.L1Cache_Controller.M_I.WB_Ack | 1127309 64.72% 64.72% | 614454 35.28% 100.00%
+system.ruby.L1Cache_Controller.M_I.WB_Ack::total 1741763
+system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack | 0 0.00% 0.00% | 1 100.00% 100.00%
+system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack::total 1
+system.ruby.L2Cache_Controller.L1_GET_INSTR 820529 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_GETS 1434524 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_GETX 433826 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_UPGRADE 24578 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_PUTX 1741764 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_PUTX_old 1 0.00% 0.00%
+system.ruby.L2Cache_Controller.L2_Replacement 100099 0.00% 0.00%
+system.ruby.L2Cache_Controller.L2_Replacement_clean 13487 0.00% 0.00%
+system.ruby.L2Cache_Controller.Mem_Data 181113 0.00% 0.00%
+system.ruby.L2Cache_Controller.Mem_Ack 116345 0.00% 0.00%
+system.ruby.L2Cache_Controller.WB_Data 26110 0.00% 0.00%
+system.ruby.L2Cache_Controller.WB_Data_clean 2213 0.00% 0.00%
+system.ruby.L2Cache_Controller.Ack 1845 0.00% 0.00%
+system.ruby.L2Cache_Controller.Ack_all 7085 0.00% 0.00%
+system.ruby.L2Cache_Controller.Unblock 27823 0.00% 0.00%
+system.ruby.L2Cache_Controller.Exclusive_Unblock 1795273 0.00% 0.00%
+system.ruby.L2Cache_Controller.MEM_Inv 5518 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 15422 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETS 32337 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETX 133354 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS.L1_GET_INSTR 805077 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS.L1_GETS 69426 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS.L1_GETX 1949 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS.L1_UPGRADE 24573 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS.L2_Replacement 290 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 6672 0.00% 0.00%
system.ruby.L2Cache_Controller.SS.MEM_Inv 5 0.00% 0.00%
system.ruby.L2Cache_Controller.M.L1_GET_INSTR 26 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_GETS 1304646 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_GETX 274082 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement 99609 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement_clean 6704 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.MEM_Inv 2851 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L1_GETS 1304540 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L1_GETX 274254 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement 99553 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement_clean 6682 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.MEM_Inv 2525 0.00% 0.00%
system.ruby.L2Cache_Controller.MT.L1_GET_INSTR 4 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L1_GETS 27481 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L1_GETX 24111 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L1_PUTX 1741834 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L2_Replacement 251 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 134 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT.L1_GETS 27819 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT.L1_GETX 24266 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT.L1_PUTX 1741763 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT.L1_PUTX_old 1 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT.L2_Replacement 256 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 133 0.00% 0.00%
system.ruby.L2Cache_Controller.MT.MEM_Inv 229 0.00% 0.00%
-system.ruby.L2Cache_Controller.M_I.Mem_Ack 116748 0.00% 0.00%
-system.ruby.L2Cache_Controller.M_I.MEM_Inv 2851 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_I.WB_Data 442 0.00% 0.00%
+system.ruby.L2Cache_Controller.M_I.Mem_Ack 116345 0.00% 0.00%
+system.ruby.L2Cache_Controller.M_I.MEM_Inv 2525 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_I.WB_Data 447 0.00% 0.00%
system.ruby.L2Cache_Controller.MT_I.Ack_all 38 0.00% 0.00%
system.ruby.L2Cache_Controller.MT_I.MEM_Inv 229 0.00% 0.00%
-system.ruby.L2Cache_Controller.MCT_I.WB_Data 52 0.00% 0.00%
-system.ruby.L2Cache_Controller.MCT_I.Ack_all 82 0.00% 0.00%
-system.ruby.L2Cache_Controller.I_I.Ack 1570 0.00% 0.00%
-system.ruby.L2Cache_Controller.I_I.Ack_all 6674 0.00% 0.00%
-system.ruby.L2Cache_Controller.S_I.Ack 295 0.00% 0.00%
-system.ruby.L2Cache_Controller.S_I.Ack_all 296 0.00% 0.00%
+system.ruby.L2Cache_Controller.MCT_I.WB_Data 53 0.00% 0.00%
+system.ruby.L2Cache_Controller.MCT_I.Ack_all 80 0.00% 0.00%
+system.ruby.L2Cache_Controller.I_I.Ack 1551 0.00% 0.00%
+system.ruby.L2Cache_Controller.I_I.Ack_all 6672 0.00% 0.00%
+system.ruby.L2Cache_Controller.S_I.Ack 294 0.00% 0.00%
+system.ruby.L2Cache_Controller.S_I.Ack_all 295 0.00% 0.00%
system.ruby.L2Cache_Controller.S_I.MEM_Inv 5 0.00% 0.00%
-system.ruby.L2Cache_Controller.ISS.Mem_Data 32321 0.00% 0.00%
-system.ruby.L2Cache_Controller.IS.Mem_Data 15428 0.00% 0.00%
-system.ruby.L2Cache_Controller.IM.Mem_Data 133485 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS_MB.L1_GETS 233 0.00% 0.00%
+system.ruby.L2Cache_Controller.ISS.Mem_Data 32337 0.00% 0.00%
+system.ruby.L2Cache_Controller.IS.Mem_Data 15422 0.00% 0.00%
+system.ruby.L2Cache_Controller.IM.Mem_Data 133354 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS_MB.L1_GETS 237 0.00% 0.00%
system.ruby.L2Cache_Controller.SS_MB.L1_GETX 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS_MB.L1_UPGRADE 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 26234 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_MB.L1_GETS 159 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS_MB.L1_UPGRADE 5 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 26522 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_MB.L1_GETS 165 0.00% 0.00%
system.ruby.L2Cache_Controller.MT_MB.L1_GETX 2 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 1768645 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_IIB.WB_Data 25308 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean 2170 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_IIB.Unblock 7 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_IB.WB_Data 6 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_MB.L1_PUTX 1 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 1768751 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_IIB.WB_Data 25603 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean 2212 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_IIB.Unblock 8 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_IB.WB_Data 7 0.00% 0.00%
system.ruby.L2Cache_Controller.MT_IB.WB_Data_clean 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_SB.Unblock 27478 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_SB.Unblock 27815 0.00% 0.00%
---------- End Simulation Statistics ----------
cache_line_size=64
clk_domain=system.clk_domain
eventq_index=0
+exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
+multi_thread=false
num_work_ids=16
readfile=
symbolfile=
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
+writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
+writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
+writeback_clean=false
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
-snoop_filter=Null
+snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
+[system.cpu.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser
+executable=/home/stever/m5/dist/cpu2000/binaries/x86/linux/parser
gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/home/stever/m5/dist/cpu2000/data/parser/mdred/input/parser.in
kvmInSE=false
max_stack_size=67108864
output=cout
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 14 2015 22:13:36
-gem5 started Sep 14 2015 22:14:29
-gem5 executing on ribera.cs.wisc.edu
-command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
+gem5 compiled Mar 15 2016 21:27:50
+gem5 started Mar 15 2016 21:35:29
+gem5 executing on phenom, pid 15976
+command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Reading the dictionary files: **info: Increasing stack size by one page.
*******info: Increasing stack size by one page.
-******************************info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-**********
+****************************************
58924 words stored in 3784810 bytes
Echoing of input sentence turned on.
* as had expected the party to be a success , it was a success
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
* do you know where John 's
* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor
-* how fast the program is it
-* I am wondering whether to invite to the party
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+* how fast the program is it
+* I am wondering whether to invite to the party
* I gave him for his birthday it
* I thought terrible after our discussion
* I wonder how much money have you earned
about 2 million people attended
the five best costumes got prizes
No errors!
-Exiting @ tick 403706643500 because target called exit()
+Exiting @ tick 403557300500 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.403427 # Number of seconds simulated
-sim_ticks 403427114500 # Number of ticks simulated
-final_tick 403427114500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.403557 # Number of seconds simulated
+sim_ticks 403557300500 # Number of ticks simulated
+final_tick 403557300500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 97075 # Simulator instruction rate (inst/s)
-host_op_rate 179503 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 47362243 # Simulator tick rate (ticks/s)
-host_mem_usage 432836 # Number of bytes of host memory used
-host_seconds 8517.91 # Real time elapsed on the host
+host_inst_rate 114335 # Simulator instruction rate (inst/s)
+host_op_rate 211418 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 55801045 # Simulator tick rate (ticks/s)
+host_mem_usage 368712 # Number of bytes of host memory used
+host_seconds 7232.07 # Real time elapsed on the host
sim_insts 826877109 # Number of instructions simulated
sim_ops 1528988701 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 163328 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 24540032 # Number of bytes read from this memory
-system.physmem.bytes_read::total 24703360 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 163328 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 163328 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 18887104 # Number of bytes written to this memory
-system.physmem.bytes_written::total 18887104 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 2552 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 383438 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 385990 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 295111 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 295111 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 404851 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 60828911 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 61233762 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 404851 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 404851 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 46816645 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 46816645 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 46816645 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 404851 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 60828911 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 108050407 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 385990 # Number of read requests accepted
-system.physmem.writeReqs 295111 # Number of write requests accepted
-system.physmem.readBursts 385990 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 295111 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 24683712 # Total number of bytes read from DRAM
+system.physmem.bytes_read::cpu.inst 163584 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 24544448 # Number of bytes read from this memory
+system.physmem.bytes_read::total 24708032 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 163584 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 163584 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 18888768 # Number of bytes written to this memory
+system.physmem.bytes_written::total 18888768 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 2556 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 383507 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 386063 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 295137 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 295137 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 405355 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 60820230 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 61225585 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 405355 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 405355 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 46805665 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 46805665 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 46805665 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 405355 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 60820230 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 108031251 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 386063 # Number of read requests accepted
+system.physmem.writeReqs 295137 # Number of write requests accepted
+system.physmem.readBursts 386063 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 295137 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 24688384 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 19648 # Total number of bytes read from write queue
-system.physmem.bytesWritten 18885056 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 24703360 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 18887104 # Total written bytes from the system interface side
+system.physmem.bytesWritten 18886848 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 24708032 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 18888768 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 307 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 24081 # Per bank write bursts
-system.physmem.perBankRdBursts::1 26417 # Per bank write bursts
-system.physmem.perBankRdBursts::2 24826 # Per bank write bursts
-system.physmem.perBankRdBursts::3 24490 # Per bank write bursts
-system.physmem.perBankRdBursts::4 23233 # Per bank write bursts
-system.physmem.perBankRdBursts::5 23715 # Per bank write bursts
-system.physmem.perBankRdBursts::6 24493 # Per bank write bursts
-system.physmem.perBankRdBursts::7 24296 # Per bank write bursts
-system.physmem.perBankRdBursts::8 23625 # Per bank write bursts
-system.physmem.perBankRdBursts::9 23520 # Per bank write bursts
-system.physmem.perBankRdBursts::10 24786 # Per bank write bursts
-system.physmem.perBankRdBursts::11 23961 # Per bank write bursts
-system.physmem.perBankRdBursts::12 23329 # Per bank write bursts
-system.physmem.perBankRdBursts::13 22937 # Per bank write bursts
-system.physmem.perBankRdBursts::14 24074 # Per bank write bursts
-system.physmem.perBankRdBursts::15 23900 # Per bank write bursts
-system.physmem.perBankWrBursts::0 18616 # Per bank write bursts
-system.physmem.perBankWrBursts::1 19936 # Per bank write bursts
-system.physmem.perBankWrBursts::2 19195 # Per bank write bursts
+system.physmem.perBankRdBursts::0 24073 # Per bank write bursts
+system.physmem.perBankRdBursts::1 26429 # Per bank write bursts
+system.physmem.perBankRdBursts::2 24836 # Per bank write bursts
+system.physmem.perBankRdBursts::3 24494 # Per bank write bursts
+system.physmem.perBankRdBursts::4 23227 # Per bank write bursts
+system.physmem.perBankRdBursts::5 23706 # Per bank write bursts
+system.physmem.perBankRdBursts::6 24492 # Per bank write bursts
+system.physmem.perBankRdBursts::7 24304 # Per bank write bursts
+system.physmem.perBankRdBursts::8 23632 # Per bank write bursts
+system.physmem.perBankRdBursts::9 23534 # Per bank write bursts
+system.physmem.perBankRdBursts::10 24801 # Per bank write bursts
+system.physmem.perBankRdBursts::11 23978 # Per bank write bursts
+system.physmem.perBankRdBursts::12 23332 # Per bank write bursts
+system.physmem.perBankRdBursts::13 22938 # Per bank write bursts
+system.physmem.perBankRdBursts::14 24084 # Per bank write bursts
+system.physmem.perBankRdBursts::15 23896 # Per bank write bursts
+system.physmem.perBankWrBursts::0 18613 # Per bank write bursts
+system.physmem.perBankWrBursts::1 19937 # Per bank write bursts
+system.physmem.perBankWrBursts::2 19197 # Per bank write bursts
system.physmem.perBankWrBursts::3 19026 # Per bank write bursts
-system.physmem.perBankWrBursts::4 18116 # Per bank write bursts
-system.physmem.perBankWrBursts::5 18513 # Per bank write bursts
-system.physmem.perBankWrBursts::6 19137 # Per bank write bursts
-system.physmem.perBankWrBursts::7 19093 # Per bank write bursts
-system.physmem.perBankWrBursts::8 18645 # Per bank write bursts
-system.physmem.perBankWrBursts::9 17955 # Per bank write bursts
-system.physmem.perBankWrBursts::10 18907 # Per bank write bursts
-system.physmem.perBankWrBursts::11 17752 # Per bank write bursts
-system.physmem.perBankWrBursts::12 17408 # Per bank write bursts
-system.physmem.perBankWrBursts::13 17006 # Per bank write bursts
-system.physmem.perBankWrBursts::14 17895 # Per bank write bursts
-system.physmem.perBankWrBursts::15 17879 # Per bank write bursts
+system.physmem.perBankWrBursts::4 18109 # Per bank write bursts
+system.physmem.perBankWrBursts::5 18508 # Per bank write bursts
+system.physmem.perBankWrBursts::6 19135 # Per bank write bursts
+system.physmem.perBankWrBursts::7 19091 # Per bank write bursts
+system.physmem.perBankWrBursts::8 18652 # Per bank write bursts
+system.physmem.perBankWrBursts::9 17959 # Per bank write bursts
+system.physmem.perBankWrBursts::10 18920 # Per bank write bursts
+system.physmem.perBankWrBursts::11 17762 # Per bank write bursts
+system.physmem.perBankWrBursts::12 17406 # Per bank write bursts
+system.physmem.perBankWrBursts::13 17012 # Per bank write bursts
+system.physmem.perBankWrBursts::14 17899 # Per bank write bursts
+system.physmem.perBankWrBursts::15 17881 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 403427072500 # Total gap between requests
+system.physmem.totGap 403557258500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 385990 # Read request sizes (log2)
+system.physmem.readPktSize::6 386063 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 295111 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 380786 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 4546 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 308 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 33 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 295137 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 380830 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 4573 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 303 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 40 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 6166 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 6569 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 16986 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 6160 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 6563 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 17529 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 17639 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 17648 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 17662 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 17655 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 17706 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 17661 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 17722 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 17690 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 17764 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 17770 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 17759 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 17891 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 17597 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 17537 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 39 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 17644 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 17643 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 17669 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 17657 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::24 17665 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::26 17685 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 17778 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 17778 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 17761 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 17921 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 17612 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 17541 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 41 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 19 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 14 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 11 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 12 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 10 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 6 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 146923 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 296.528440 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 175.268112 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 322.869611 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 54238 36.92% 36.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 39906 27.16% 64.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 13861 9.43% 73.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 7527 5.12% 78.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 5392 3.67% 82.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 3977 2.71% 85.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 3022 2.06% 87.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 2802 1.91% 88.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 16198 11.02% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 146923 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 17507 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 22.029360 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 217.887118 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 17497 99.94% 99.94% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples 146836 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 296.749026 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 175.460690 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 322.805815 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 54147 36.88% 36.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 39842 27.13% 64.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 13777 9.38% 73.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 7669 5.22% 78.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 5515 3.76% 82.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 3906 2.66% 85.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 2997 2.04% 87.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 2808 1.91% 88.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 16175 11.02% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 146836 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 17510 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 22.029754 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 217.905540 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023 17500 99.94% 99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047 5 0.03% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3072-4095 3 0.02% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 17507 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 17507 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 16.854915 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 16.776896 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 2.816664 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 17316 98.91% 98.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 131 0.75% 99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 34 0.19% 99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 8 0.05% 99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 2 0.01% 99.91% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total 17510 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 17510 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 16.853626 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 16.775847 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 2.814458 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 17322 98.93% 98.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 130 0.74% 99.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 32 0.18% 99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 9 0.05% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 1 0.01% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 3 0.02% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 1 0.01% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 1 0.01% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127 2 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 1 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::216-219 1 0.01% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 17507 # Writes before turning the bus around for reads
-system.physmem.totQLat 4287997000 # Total ticks spent queuing
-system.physmem.totMemAccLat 11519553250 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 1928415000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 11117.93 # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total 17510 # Writes before turning the bus around for reads
+system.physmem.totQLat 4294664500 # Total ticks spent queuing
+system.physmem.totMemAccLat 11527589500 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 1928780000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 11133.11 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 29867.93 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 61.19 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 46.81 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 29883.11 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 61.18 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 46.80 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 61.23 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 46.82 # Average system write bandwidth in MiByte/s
+system.physmem.avgWrBWSys 46.81 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.84 # Data bus utilization in percentage
system.physmem.busUtilRead 0.48 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.37 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 21.97 # Average write queue length when enqueuing
-system.physmem.readRowHits 318108 # Number of row buffer hits during reads
-system.physmem.writeRowHits 215717 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 82.48 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 73.10 # Row buffer hit rate for writes
-system.physmem.avgGap 592316.08 # Average gap between requests
-system.physmem.pageHitRate 78.41 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 568655640 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 310278375 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 1525157400 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 982374480 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 26349510720 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 62248054410 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 187449302250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 279433333275 # Total energy per rank (pJ)
-system.physmem_0.averagePower 692.658624 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 311288113000 # Time in different power states
-system.physmem_0.memoryStateTime::REF 13471120000 # Time in different power states
+system.physmem.avgWrQLen 21.17 # Average write queue length when enqueuing
+system.physmem.readRowHits 318250 # Number of row buffer hits during reads
+system.physmem.writeRowHits 215762 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 82.50 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 73.11 # Row buffer hit rate for writes
+system.physmem.avgGap 592421.11 # Average gap between requests
+system.physmem.pageHitRate 78.43 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 567929880 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 309882375 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 1525258800 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 982361520 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 26358156240 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 62125312320 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 187636398750 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 279505299885 # Total energy per rank (pJ)
+system.physmem_0.averagePower 692.609739 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 311602147750 # Time in different power states
+system.physmem_0.memoryStateTime::REF 13475540000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 78663487000 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 78476140500 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 541689120 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 295564500 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 1482585000 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 929322720 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 26349510720 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 60147053505 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 189292285500 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 279038011065 # Total energy per rank (pJ)
-system.physmem_1.averagePower 691.678700 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 314369366250 # Time in different power states
-system.physmem_1.memoryStateTime::REF 13471120000 # Time in different power states
+system.physmem_1.actEnergy 541832760 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 295642875 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 1483138800 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 929594880 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 26358156240 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 60415771455 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 189135996000 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 279160133010 # Total energy per rank (pJ)
+system.physmem_1.averagePower 691.754421 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 314107658000 # Time in different power states
+system.physmem_1.memoryStateTime::REF 13475540000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 75582067750 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 75970627000 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 219277494 # Number of BP lookups
-system.cpu.branchPred.condPredicted 219277494 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 8530091 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 124020025 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 121811454 # Number of BTB hits
+system.cpu.branchPred.lookups 219252380 # Number of BP lookups
+system.cpu.branchPred.condPredicted 219252380 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 8528271 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 123973177 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 121800120 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 98.219182 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 27064699 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 1406143 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 98.247156 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 27061903 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 1407355 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.workload.num_syscalls 551 # Number of system calls
-system.cpu.numCycles 806854230 # number of cpu cycles simulated
+system.cpu.numCycles 807114602 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 175890438 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 1208681477 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 219277494 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 148876153 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 621110348 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 17764353 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 230 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles 91101 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 722324 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 1300 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 170768195 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 2322348 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.icacheStallCycles 175891157 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 1208567118 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 219252380 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 148862023 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 621375374 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 17762469 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 208 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles 90709 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 718160 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 1191 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 35 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 170755406 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 2320013 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes 3 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 806697934 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.787860 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.367990 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples 806958068 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.786744 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.368251 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 416692027 51.65% 51.65% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 32514924 4.03% 55.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 31852485 3.95% 59.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 32737208 4.06% 63.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 26535487 3.29% 66.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 26940530 3.34% 70.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 35175393 4.36% 74.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 31366288 3.89% 78.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 172883592 21.43% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 417094848 51.69% 51.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 32452037 4.02% 55.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 31902781 3.95% 59.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 32612026 4.04% 63.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 26524373 3.29% 66.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 26910367 3.33% 70.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 35157617 4.36% 74.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 31335613 3.88% 78.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 172968406 21.43% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 806697934 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.271768 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.498017 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 120436174 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 370050155 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 225346926 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 81982503 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 8882176 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 2132175908 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 8882176 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 152549485 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 150499256 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 41235 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 271495233 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 223230549 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 2088541699 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 133771 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 138231059 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 24777266 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 50120464 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 2190713921 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 5278163786 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 3357090809 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 59859 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 806958068 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.271650 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.497392 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 120421699 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 370368413 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 225215938 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 82070784 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 8881234 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 2132047991 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 8881234 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 152579592 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 150649676 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 43646 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 271398208 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 223405712 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 2088421237 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 135982 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 138413157 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 24833190 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 50057898 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 2190635347 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 5277929489 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 3356932236 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 59989 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 576673067 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 3285 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 3078 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 422612041 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 507148674 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 200824572 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 228968697 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 68242516 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 2023165492 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 27791 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 1789027795 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 414599 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 494204582 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 832990276 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 27239 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 806697934 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.217717 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.070743 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 576594493 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 3330 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 3150 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 422929221 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 507109788 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 200805340 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 229274294 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 68310404 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 2023046060 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 27646 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 1788955161 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 413315 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 494085005 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 832817551 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 27094 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 806958068 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.216912 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.070634 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 238149356 29.52% 29.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 123576451 15.32% 44.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 118711028 14.72% 59.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 107747587 13.36% 72.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 89829016 11.14% 84.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 60156883 7.46% 91.51% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 42289548 5.24% 96.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 18955760 2.35% 99.10% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 7282305 0.90% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 238363650 29.54% 29.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 123779759 15.34% 44.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 118420990 14.67% 59.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 107850309 13.37% 72.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 89928227 11.14% 84.06% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 60113985 7.45% 91.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 42280336 5.24% 96.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 18948850 2.35% 99.10% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 7271962 0.90% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 806697934 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 806958068 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 11505863 42.68% 42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 12343295 45.78% 88.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 3110421 11.54% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 11501801 42.82% 42.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 42.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 42.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 42.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 42.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 42.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 12260611 45.64% 88.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 3099977 11.54% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 2715990 0.15% 0.15% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1183116627 66.13% 66.28% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 369664 0.02% 66.30% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 3881147 0.22% 66.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 118 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 2718189 0.15% 0.15% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1183067002 66.13% 66.28% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 368893 0.02% 66.30% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 3881187 0.22% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 137 0.00% 66.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 58 0.00% 66.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 380 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 38 0.00% 66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 395 0.00% 66.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.52% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 428537576 23.95% 90.47% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 170406235 9.53% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 428511642 23.95% 90.47% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 170407678 9.53% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 1789027795 # Type of FU issued
-system.cpu.iq.rate 2.217287 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 26959579 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.015069 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 4412098039 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 2517646847 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1762392188 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 29663 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 69110 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 5652 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 1813258358 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 13026 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 185949248 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 1788955161 # Type of FU issued
+system.cpu.iq.rate 2.216482 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 26862389 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.015016 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 4412114486 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 2517408815 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 1762314892 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 29608 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 69342 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 5559 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 1813086388 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 12973 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 185891278 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 123048931 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 213773 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 371791 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 51664386 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 123009946 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 214354 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 373061 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 51645154 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 23126 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 1127 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 23005 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 1152 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 8882176 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 97661574 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 6126306 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 2023193283 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 371095 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 507151088 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 200824572 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 12039 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 1828108 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 3395741 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 371791 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 4845230 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 4136012 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 8981242 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 1770011750 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 423132476 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 19016045 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 8881234 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 97675937 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 6156450 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 2023073706 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 372553 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 507112103 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 200805340 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 12025 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 1859445 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 3396246 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 373061 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 4843605 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 4134020 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 8977625 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 1769939059 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 423109380 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 19016102 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 590347878 # number of memory reference insts executed
-system.cpu.iew.exec_branches 168976982 # Number of branches executed
-system.cpu.iew.exec_stores 167215402 # Number of stores executed
-system.cpu.iew.exec_rate 2.193719 # Inst execution rate
-system.cpu.iew.wb_sent 1766881473 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 1762397840 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1339889750 # num instructions producing a value
-system.cpu.iew.wb_consumers 2050179516 # num instructions consuming a value
-system.cpu.iew.wb_rate 2.184283 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.653548 # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts 494265381 # The number of squashed insts skipped by commit
+system.cpu.iew.exec_refs 590326143 # number of memory reference insts executed
+system.cpu.iew.exec_branches 168971977 # Number of branches executed
+system.cpu.iew.exec_stores 167216763 # Number of stores executed
+system.cpu.iew.exec_rate 2.192922 # Inst execution rate
+system.cpu.iew.wb_sent 1766810354 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 1762320451 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1339786199 # num instructions producing a value
+system.cpu.iew.wb_consumers 2050074397 # num instructions consuming a value
+system.cpu.iew.wb_rate 2.183482 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.653531 # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts 494145922 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 8610728 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 739482483 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 2.067647 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.576172 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 8608481 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 739768084 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 2.066849 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.575796 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 275479046 37.25% 37.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 172073402 23.27% 60.52% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 55823940 7.55% 68.07% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 86367064 11.68% 79.75% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 25894199 3.50% 83.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 26482728 3.58% 86.83% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 9848964 1.33% 88.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 9023113 1.22% 89.39% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 78490027 10.61% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 275719169 37.27% 37.27% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 172002982 23.25% 60.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 56035372 7.57% 68.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 86287676 11.66% 79.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 25889173 3.50% 83.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 26492883 3.58% 86.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 9844270 1.33% 88.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 9007252 1.22% 89.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 78489307 10.61% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 739482483 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 739768084 # Number of insts commited each cycle
system.cpu.commit.committedInsts 826877109 # Number of instructions committed
system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction
-system.cpu.commit.bw_lim_events 78490027 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 2684246538 # The number of ROB reads
-system.cpu.rob.rob_writes 4113897788 # The number of ROB writes
-system.cpu.timesIdled 1953 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 156296 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events 78489307 # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads 2684413400 # The number of ROB reads
+system.cpu.rob.rob_writes 4113633509 # The number of ROB writes
+system.cpu.timesIdled 1975 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 156534 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 826877109 # Number of Instructions Simulated
system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 0.975785 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.975785 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.024816 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.024816 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 2722631435 # number of integer regfile reads
-system.cpu.int_regfile_writes 1435841734 # number of integer regfile writes
-system.cpu.fp_regfile_reads 5845 # number of floating regfile reads
-system.cpu.fp_regfile_writes 533 # number of floating regfile writes
-system.cpu.cc_regfile_reads 596631944 # number of cc regfile reads
-system.cpu.cc_regfile_writes 405465564 # number of cc regfile writes
-system.cpu.misc_regfile_reads 971632310 # number of misc regfile reads
+system.cpu.cpi 0.976100 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.976100 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.024485 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.024485 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 2722552264 # number of integer regfile reads
+system.cpu.int_regfile_writes 1435774618 # number of integer regfile writes
+system.cpu.fp_regfile_reads 5765 # number of floating regfile reads
+system.cpu.fp_regfile_writes 491 # number of floating regfile writes
+system.cpu.cc_regfile_reads 596650045 # number of cc regfile reads
+system.cpu.cc_regfile_writes 405459285 # number of cc regfile writes
+system.cpu.misc_regfile_reads 971600702 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
-system.cpu.dcache.tags.replacements 2530979 # number of replacements
-system.cpu.dcache.tags.tagsinuse 4087.807694 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 381987598 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 2535075 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 150.680985 # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements 2530810 # number of replacements
+system.cpu.dcache.tags.tagsinuse 4087.810337 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 382026213 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 2534906 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 150.706264 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 1673396500 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 4087.807694 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.998000 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.998000 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data 4087.810337 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.998001 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.998001 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 866 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 3174 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 867 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3 3177 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 773071261 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 773071261 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 233342532 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 233342532 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 148176085 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 148176085 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 381518617 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 381518617 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 381518617 # number of overall hits
-system.cpu.dcache.overall_hits::total 381518617 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 2765359 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 2765359 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 984117 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 984117 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 3749476 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 3749476 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 3749476 # number of overall misses
-system.cpu.dcache.overall_misses::total 3749476 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 58561335000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 58561335000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 30709347495 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 30709347495 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 89270682495 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 89270682495 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 89270682495 # number of overall miss cycles
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-system.cpu.dcache.ReadReq_accesses::cpu.data 236107891 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses)
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-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21176.756797 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 21176.756797 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31204.976131 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 31204.976131 # average WriteReq miss latency
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-system.cpu.dcache.demand_avg_miss_latency::total 23808.842221 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 23808.842221 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 23808.842221 # average overall miss latency
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-system.cpu.dcache.ReadReq_mshr_hits::total 1000418 # number of ReadReq MSHR hits
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-system.cpu.dcache.ReadReq_mshr_misses::total 1764941 # number of ReadReq MSHR misses
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-system.cpu.dcache.demand_mshr_miss_latency::total 63053157997 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63053157997 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 63053157997 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007475 # mshr miss rate for ReadReq accesses
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-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19016.661463 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30568.417989 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30568.417989 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23099.288628 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 23099.288628 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23099.288628 # average overall mshr miss latency
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+system.cpu.dcache.writebacks::writebacks 2330455 # number of writebacks
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system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests 5470136 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 2729158 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 209637 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 3579 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3579 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
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system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
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-system.cpu.toL2Bus.trans_dist::WritebackDirty 2625725 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 6598 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 260490 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 194583 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 194583 # Transaction distribution
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-system.cpu.toL2Bus.trans_dist::ReadSharedReq 1764548 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217689 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7990295 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 8207984 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 946432 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311404096 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 312350528 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 549945 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 3287795 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.123088 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.328538 # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp 1969849 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty 2625592 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean 6689 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict 260538 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 197036 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 197036 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 770487 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 770487 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 205432 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 1764419 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 220390 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7994694 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 8215084 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 957312 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311383104 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 312340416 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 552481 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 3292694 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 0.124385 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.330020 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 2883107 87.69% 87.69% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 404688 12.31% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 2883132 87.56% 87.56% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 409562 12.44% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 3287795 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 5100517412 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 3292694 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 5103271503 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 304355486 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 308149990 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 3899906073 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 3900879073 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
-system.membus.trans_dist::ReadResp 179130 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 295111 # Transaction distribution
-system.membus.trans_dist::CleanEvict 56614 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 192805 # Transaction distribution
-system.membus.trans_dist::ReadExReq 206859 # Transaction distribution
-system.membus.trans_dist::ReadExResp 206859 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 179131 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1316509 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1316509 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1316509 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43590400 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43590400 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 43590400 # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp 179188 # Transaction distribution
+system.membus.trans_dist::WritebackDirty 295137 # Transaction distribution
+system.membus.trans_dist::CleanEvict 56656 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 195245 # Transaction distribution
+system.membus.trans_dist::ReadExReq 206874 # Transaction distribution
+system.membus.trans_dist::ReadExResp 206874 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 179189 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1319163 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1319163 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1319163 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43596736 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43596736 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 43596736 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 930520 # Request fanout histogram
+system.membus.snoop_fanout::samples 933101 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 930520 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 933101 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 930520 # Request fanout histogram
-system.membus.reqLayer0.occupancy 2239434504 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 933101 # Request fanout histogram
+system.membus.reqLayer0.occupancy 2242999911 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.6 # Layer utilization (%)
-system.membus.respLayer1.occupancy 2041939000 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 2042259250 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.5 # Layer utilization (%)
---------- End Simulation Statistics ----------
projects / gem5.git / commitdiff