Add $_FF_ and $_SR* courtesy of @mwkmwkmwk

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 627133314e47af23a7751ca7859dcf83d3cc6d33..e0ae118ad5fc752a352f2af0c9ae2035770ddc37 100644 (file)
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -605,15 +605,25 @@ struct XAigerWriter
                        RTLIL::Module *holes_module = module->design->addModule("$__holes__");
                        log_assert(holes_module);
 
+                       dict<IdString, Cell*> cell_cache;
+
                        int port_id = 1;
                        int box_count = 0;
                        for (auto cell : box_list) {
                                RTLIL::Module* box_module = module->design->module(cell->type);
+                               log_assert(box_module);
+                               IdString derived_name = box_module->derive(module->design, cell->parameters);
+                               box_module = module->design->module(derived_name);
+                               if (box_module->has_processes())
+                                       log_error("ABC9 box '%s' contains processes!\n", box_module->name.c_str());
+
                                int box_inputs = 0, box_outputs = 0;
-                               Cell *holes_cell = nullptr;
-                               if (box_module->get_bool_attribute("\\whitebox")) {
+                               auto r = cell_cache.insert(std::make_pair(derived_name, nullptr));
+                               Cell *holes_cell = r.first->second;
+                               if (r.second && !holes_cell && box_module->get_bool_attribute("\\whitebox")) {
                                        holes_cell = holes_module->addCell(cell->name, cell->type);
                                        holes_cell->parameters = cell->parameters;
+                                       r.first->second = holes_cell;
                                }
 
                                // NB: Assume box_module->ports are sorted alphabetically
@@ -622,8 +632,8 @@ struct XAigerWriter
                                        RTLIL::Wire *w = box_module->wire(port_name);
                                        log_assert(w);
                                        RTLIL::Wire *holes_wire;
-                                       RTLIL::SigSpec port_wire;
-                                       if (w->port_input) {
+                                       RTLIL::SigSpec port_sig;
+                                       if (w->port_input)
                                                for (int i = 0; i < GetSize(w); i++) {
                                                        box_inputs++;
                                                        holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
@@ -634,28 +644,29 @@ struct XAigerWriter
                                                                holes_module->ports.push_back(holes_wire->name);
                                                        }
                                                        if (holes_cell)
-                                                               port_wire.append(holes_wire);
+                                                               port_sig.append(holes_wire);
                                                }
-                                               if (!port_wire.empty())
-                                                       holes_cell->setPort(w->name, port_wire);
-                                       }
                                        if (w->port_output) {
                                                box_outputs += GetSize(w);
                                                for (int i = 0; i < GetSize(w); i++) {
                                                        if (GetSize(w) == 1)
-                                                               holes_wire = holes_module->addWire(stringf("%s.%s", cell->name.c_str(), w->name.c_str()));
+                                                               holes_wire = holes_module->addWire(stringf("%s.%s", cell->name.c_str(), log_id(w->name)));
                                                        else
-                                                               holes_wire = holes_module->addWire(stringf("%s.%s[%d]", cell->name.c_str(), w->name.c_str(), i));
+                                                               holes_wire = holes_module->addWire(stringf("%s.%s[%d]", cell->name.c_str(), log_id(w->name), i));
                                                        holes_wire->port_output = true;
                                                        holes_wire->port_id = port_id++;
                                                        holes_module->ports.push_back(holes_wire->name);
                                                        if (holes_cell)
-                                                               port_wire.append(holes_wire);
+                                                               port_sig.append(holes_wire);
                                                        else
                                                                holes_module->connect(holes_wire, State::S0);
                                                }
-                                               if (!port_wire.empty())
-                                                       holes_cell->setPort(w->name, port_wire);
+                                       }
+                                       if (!port_sig.empty()) {
+                                               if (r.second)
+                                                       holes_cell->setPort(w->name, port_sig);
+                                               else
+                                                       holes_module->connect(holes_cell->getPort(w->name), port_sig);
                                        }
                                }
 
@@ -685,14 +696,11 @@ struct XAigerWriter
                                RTLIL::Selection& sel = holes_module->design->selection_stack.back();
                                sel.select(holes_module);
 
-                               // TODO: Should not need to opt_merge if we only instantiate
-                               //       each box type once...
-                               Pass::call(holes_module->design, "opt_merge -share_all");
-
                                Pass::call(holes_module->design, "flatten -wb");
 
-                               // TODO: Should techmap/aigmap/check all lib_whitebox-es just once,
-                               //       instead of per write_xaiger call
+                               // Cannot techmap/aigmap all lib_whitebox-es just once per design
+                               // instead of per write_xaiger call, since boxes may be parameterised
+                               // and new $paramod-s may have been created...
                                Pass::call(holes_module->design, "techmap");
                                Pass::call(holes_module->design, "aigmap");
                                for (auto cell : holes_module->cells())

diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc
index 8dd238bc77b76f40fe09673335f3a255c7409546..8823a9061853b014892a211abdd60fb66e5bf535 100644 (file)
--- a/passes/opt/opt_merge.cc
+++ b/passes/opt/opt_merge.cc
@@ -222,8 +222,9 @@ struct OptMergeWorker
                        return true;
                }
 
-               if (conn1.count(ID(Q)) != 0 && (cell1->type.begins_with("$dff") || cell1->type.begins_with("$dlatch") || cell1->type.in("$adff", "$sr", "$ff") ||
-                                       cell1->type.begins_with("$_DFF") || cell1->type.begins_with("$_DLATCH"))) {
+               if (conn1.count(ID(Q)) != 0 && (cell1->type.begins_with("$dff") || cell1->type.begins_with("$dlatch") ||
+                                       cell1->type.begins_with("$_DFF") || cell1->type.begins_with("$_DLATCH") || cell1->type.begins_with("$_SR_") ||
+                                       cell1->type.in("$adff", "$sr", "$ff", "$_FF_"))) {
                        std::vector<RTLIL::SigBit> q1 = dff_init_map(cell1->getPort(ID(Q))).to_sigbit_vector();
                        std::vector<RTLIL::SigBit> q2 = dff_init_map(cell2->getPort(ID(Q))).to_sigbit_vector();
                        for (size_t i = 0; i < q1.size(); i++)
@@ -325,8 +326,9 @@ struct OptMergeWorker
                                                        module->connect(RTLIL::SigSig(it.second, other_sig));
                                                        assign_map.add(it.second, other_sig);
 
-                                                       if (it.first == ID(Q) && (cell->type.begins_with("$dff") || cell->type.begins_with("$dlatch") || cell->type.in("$adff", "$sr", "$ff") ||
-                                                                               cell->type.begins_with("$_DFF") || cell->type.begins_with("$_DLATCH"))) {
+                                                       if (it.first == ID(Q) && (cell->type.begins_with("$dff") || cell->type.begins_with("$dlatch") ||
+                                                                               cell->type.begins_with("$_DFF") || cell->type.begins_with("$_DLATCH") || cell->type.begins_with("$_SR_") ||
+                                                                               cell->type.in("$adff", "$sr", "$ff", "$_FF_"))) {
                                                                for (auto c : it.second.chunks()) {
                                                                        auto jt = c.wire->attributes.find(ID(init));
                                                                        if (jt == c.wire->attributes.end())