radeon/llvm: Lower VCREATE_v4f32 for R600 and SI

diff --git a/src/gallium/drivers/radeon/AMDGPU.h b/src/gallium/drivers/radeon/AMDGPU.h
index 5613dab4b3512931fbaa536e09322cb827a5d876..eff002a5eae58a8b7c2005b4c4118b7b5ac02ad1 100644 (file)
--- a/src/gallium/drivers/radeon/AMDGPU.h
+++ b/src/gallium/drivers/radeon/AMDGPU.h
@@ -27,7 +27,6 @@ namespace llvm {
     FunctionPass *createR600LowerInstructionsPass(TargetMachine &tm);
 
     FunctionPass *createSIAssignInterpRegsPass(TargetMachine &tm);
-    FunctionPass *createSIConvertToISAPass(TargetMachine &tm);
     FunctionPass *createSIInitMachineFunctionInfoPass(TargetMachine &tm);
     FunctionPass *createSILowerShaderInstructionsPass(TargetMachine &tm);
     FunctionPass *createSIPropagateImmReadsPass(TargetMachine &tm);
@@ -35,6 +34,7 @@ namespace llvm {
 
     FunctionPass *createAMDGPUReorderPreloadInstructionsPass(TargetMachine &tm);
 
+    FunctionPass *createAMDGPULowerInstructionsPass(TargetMachine &tm);
     FunctionPass *createAMDGPULowerShaderInstructionsPass(TargetMachine &tm);
 
     FunctionPass *createAMDGPUDelimitInstGroupsPass(TargetMachine &tm);

diff --git a/src/gallium/drivers/radeon/AMDGPULowerInstructions.cpp b/src/gallium/drivers/radeon/AMDGPULowerInstructions.cpp
new file mode 100644 (file)
index 0000000..b49d0dd
--- /dev/null
+++ b/src/gallium/drivers/radeon/AMDGPULowerInstructions.cpp
@@ -0,0 +1,82 @@
+//===-- AMDGPULowerInstructions.cpp - TODO: Add brief description -------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// TODO: Add full description
+//
+//===----------------------------------------------------------------------===//
+
+
+#include "AMDGPU.h"
+#include "AMDGPURegisterInfo.h"
+#include "AMDIL.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+
+using namespace llvm;
+
+namespace {
+  class AMDGPULowerInstructionsPass : public MachineFunctionPass {
+
+  private:
+    static char ID;
+    TargetMachine &TM;
+    void lowerVCREATE_v4f32(MachineInstr &MI, MachineBasicBlock::iterator I,
+                              MachineBasicBlock &MBB, MachineFunction &MF);
+
+  public:
+    AMDGPULowerInstructionsPass(TargetMachine &tm) :
+      MachineFunctionPass(ID), TM(tm) { }
+
+    virtual bool runOnMachineFunction(MachineFunction &MF);
+
+  };
+} /* End anonymous namespace */
+
+char AMDGPULowerInstructionsPass::ID = 0;
+
+FunctionPass *llvm::createAMDGPULowerInstructionsPass(TargetMachine &tm) {
+  return new AMDGPULowerInstructionsPass(tm);
+}
+
+bool AMDGPULowerInstructionsPass::runOnMachineFunction(MachineFunction &MF)
+{
+  for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
+                                                  BB != BB_E; ++BB) {
+    MachineBasicBlock &MBB = *BB;
+    for (MachineBasicBlock::iterator I = MBB.begin(), Next = llvm::next(I);
+         I != MBB.end(); I = Next, Next = llvm::next(I) ) {
+      MachineInstr &MI = *I;
+
+      switch (MI.getOpcode()) {
+      default: continue;
+      case AMDIL::VCREATE_v4f32: lowerVCREATE_v4f32(MI, I, MBB, MF); break;
+
+      }
+      MI.eraseFromParent();
+    }
+  }
+  return false;
+}
+
+void AMDGPULowerInstructionsPass::lowerVCREATE_v4f32(MachineInstr &MI,
+    MachineBasicBlock::iterator I, MachineBasicBlock &MBB, MachineFunction &MF)
+{
+  MachineRegisterInfo & MRI = MF.getRegInfo();
+  unsigned tmp = MRI.createVirtualRegister(
+                  MRI.getRegClass(MI.getOperand(0).getReg()));
+
+  BuildMI(MBB, I, DebugLoc(), TM.getInstrInfo()->get(AMDIL::IMPLICIT_DEF), tmp);
+
+  BuildMI(MBB, I, DebugLoc(), TM.getInstrInfo()->get(AMDIL::INSERT_SUBREG))
+          .addOperand(MI.getOperand(0))
+          .addReg(tmp)
+          .addOperand(MI.getOperand(1))
+          .addImm(AMDIL::sel_x);
+}

diff --git a/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp b/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp
index 4d6a1bd7e34d3c48b75f107e3171b8d4c2deb47e..328589cc1437e05a0e79b66efe72bae3229b059f 100644 (file)
--- a/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp
+++ b/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp
@@ -152,8 +152,8 @@ bool AMDGPUPassConfig::addPreRegAlloc() {
   } else {
     PM.add(createSILowerShaderInstructionsPass(*TM));
     PM.add(createSIAssignInterpRegsPass(*TM));
-    PM.add(createSIConvertToISAPass(*TM));
   }
+  PM.add(createAMDGPULowerInstructionsPass(*TM));
   PM.add(createAMDGPUConvertToISAPass(*TM));
   return false;
 }

diff --git a/src/gallium/drivers/radeon/Makefile.sources b/src/gallium/drivers/radeon/Makefile.sources
index 96189e75a1748b72d0b9239ac274b4985dfa545c..fad207a6d9fd47e3006b8f5d64a9cb2647f71115 100644 (file)
--- a/src/gallium/drivers/radeon/Makefile.sources
+++ b/src/gallium/drivers/radeon/Makefile.sources
@@ -56,6 +56,7 @@ CPP_SOURCES := \
        AMDGPUTargetMachine.cpp         \
        AMDGPUISelLowering.cpp          \
        AMDGPUConvertToISA.cpp          \
+       AMDGPULowerInstructions.cpp             \
        AMDGPULowerShaderInstructions.cpp       \
        AMDGPUReorderPreloadInstructions.cpp    \
        AMDGPUInstrInfo.cpp             \
@@ -70,7 +71,6 @@ CPP_SOURCES := \
        R600RegisterInfo.cpp            \
        SIAssignInterpRegs.cpp          \
        SICodeEmitter.cpp               \
-       SIConvertToISA.cpp              \
        SIInstrInfo.cpp                 \
        SIISelLowering.cpp              \
        SILowerShaderInstructions.cpp   \

diff --git a/src/gallium/drivers/radeon/R600CodeEmitter.cpp b/src/gallium/drivers/radeon/R600CodeEmitter.cpp
index c951d9f3bad5ade8ffdc54331bd36baa1e8d880f..698dfa7cfb5c79b51763804d1506d68fcbcf1f23 100644 (file)
--- a/src/gallium/drivers/radeon/R600CodeEmitter.cpp
+++ b/src/gallium/drivers/radeon/R600CodeEmitter.cpp
@@ -400,11 +400,8 @@ void R600CodeEmitter::emitDst(const MachineOperand & MO)
     emitByte(getHWReg(MO.getReg()));
 
     /* Emit the element of the destination register (1 byte)*/
-    const MachineInstr * parent = MO.getParent();
     if (isReduction) {
       emitByte(reductionElement);
-    } else if (parent->getOpcode() == AMDIL::VCREATE_v4f32) {
-      emitByte(ELEMENT_X);
     } else {
       emitByte(TRI->getHWRegChan(MO.getReg()));
     }
@@ -631,7 +628,6 @@ unsigned int R600CodeEmitter::getHWInst(const MachineInstr &MI)
   switch (MI.getOpcode()) {
     case AMDIL::STORE_OUTPUT:
     case AMDIL::VCREATE_v4i32:
-    case AMDIL::VCREATE_v4f32:
     case AMDIL::LOADCONST_i32:
     case AMDIL::LOADCONST_f32:
     case AMDIL::MOVE_v4i32:

diff --git a/src/gallium/drivers/radeon/SIConvertToISA.cpp b/src/gallium/drivers/radeon/SIConvertToISA.cpp
deleted file mode 100644 (file)
index 44e6539..0000000
--- a/src/gallium/drivers/radeon/SIConvertToISA.cpp
+++ /dev/null
@@ -1,89 +0,0 @@
-//===-- SIConvertToISA.cpp - TODO: Add brief description -------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// TODO: Add full description
-//
-//===----------------------------------------------------------------------===//
-
-
-#include "AMDGPU.h"
-#include "AMDGPURegisterInfo.h"
-#include "AMDIL.h"
-#include "llvm/CodeGen/MachineFunctionPass.h"
-#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/CodeGen/MachineRegisterInfo.h"
-
-using namespace llvm;
-
-namespace {
-  class SIConvertToISAPass : public MachineFunctionPass {
-
-  private:
-    static char ID;
-    TargetMachine &TM;
-    void convertVCREATE_v4f32(MachineInstr &MI, MachineBasicBlock::iterator I,
-                              MachineBasicBlock &MBB, MachineFunction &MF);
-
-  public:
-    SIConvertToISAPass(TargetMachine &tm) :
-      MachineFunctionPass(ID), TM(tm) { }
-
-    virtual bool runOnMachineFunction(MachineFunction &MF);
-
-  };
-} /* End anonymous namespace */
-
-char SIConvertToISAPass::ID = 0;
-
-FunctionPass *llvm::createSIConvertToISAPass(TargetMachine &tm) {
-  return new SIConvertToISAPass(tm);
-}
-
-bool SIConvertToISAPass::runOnMachineFunction(MachineFunction &MF)
-{
-  for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
-                                                  BB != BB_E; ++BB) {
-    MachineBasicBlock &MBB = *BB;
-    for (MachineBasicBlock::iterator I = MBB.begin(), Next = llvm::next(I);
-         I != MBB.end(); I = Next, Next = llvm::next(I) ) {
-      MachineInstr &MI = *I;
-
-      switch (MI.getOpcode()) {
-      default: continue;
-      case AMDIL::VCREATE_v4f32: convertVCREATE_v4f32(MI, I, MBB, MF);
-
-      }
-      MI.removeFromParent();
-    }
-  }
-  return false;
-}
-
-void SIConvertToISAPass::convertVCREATE_v4f32(MachineInstr &MI,
-    MachineBasicBlock::iterator I, MachineBasicBlock &MBB, MachineFunction &MF)
-{
-  MachineInstrBuilder implicitDef;
-  MachineInstrBuilder insertSubreg;
-  MachineRegisterInfo & MRI = MF.getRegInfo();
-  unsigned tmp = MRI.createVirtualRegister(&AMDIL::VReg_128RegClass);
-
-  implicitDef = BuildMI(MF, MBB.findDebugLoc(I),
-                        TM.getInstrInfo()->get(AMDIL::IMPLICIT_DEF), tmp);
-
-  MRI.setRegClass(MI.getOperand(1).getReg(), &AMDIL::VReg_32RegClass);
-  insertSubreg = BuildMI(MF, MBB.findDebugLoc(I),
-                        TM.getInstrInfo()->get(AMDIL::INSERT_SUBREG))
-                        .addOperand(MI.getOperand(0))
-                        .addReg(tmp)
-                        .addOperand(MI.getOperand(1))
-                        .addImm(AMDIL::sel_x);
-
-  MBB.insert(I, implicitDef);
-  MBB.insert(I, insertSubreg);
-}