r600g: add fetch shader capabilities

Use fetch shader instead of having fetch instruction in the vertex
shader. Allow to restrict shader update to a smaller part when
vertex buffer input layout changes.

Signed-off-by: Jerome Glisse <jglisse@redhat.com>

diff --git a/src/gallium/drivers/r600/eg_asm.c b/src/gallium/drivers/r600/eg_asm.c
index c30f09c394bae1911644e033e2fc57e6663e1ba7..21d66fa9564e79097c43b6f45f45a802ef35d700 100644 (file)
--- a/src/gallium/drivers/r600/eg_asm.c
+++ b/src/gallium/drivers/r600/eg_asm.c
@@ -74,6 +74,8 @@ int eg_bc_cf_build(struct r600_bc *bc, struct r600_bc_cf *cf)
        case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
        case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
        case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
+       case EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
+       case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
                bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1);
                bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(cf->inst) |
                                        S_SQ_CF_WORD1_BARRIER(1) |

diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index 7609025bf29eecb54f1e7d1ed631d2dda91e74c5..669eef4598d404bc283853e7e60cfef09f928255 100644 (file)
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1289,7 +1289,7 @@ void evergreen_draw(struct pipe_context *ctx, const struct pipe_draw_info *info)
                r600_pipe_state_add_reg(rstate, R_030014_RESOURCE0_WORD5, 0x00000000, 0xFFFFFFFF, NULL);
                r600_pipe_state_add_reg(rstate, R_030018_RESOURCE0_WORD6, 0x00000000, 0xFFFFFFFF, NULL);
                r600_pipe_state_add_reg(rstate, R_03001C_RESOURCE0_WORD7, 0xC0000000, 0xFFFFFFFF, NULL);
-               evergreen_vs_resource_set(&rctx->ctx, rstate, i);
+               evergreen_fs_resource_set(&rctx->ctx, rstate, i);
        }
 
        mask = 0;
@@ -1554,7 +1554,7 @@ void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader
                        (r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo);
        r600_pipe_state_add_reg(rstate,
                        R_0288A4_SQ_PGM_START_FS,
-                       (r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo);
+                       (r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo_fetch);
 
        r600_pipe_state_add_reg(rstate,
                                R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,

diff --git a/src/gallium/drivers/r600/r600.h b/src/gallium/drivers/r600/r600.h
index 17858b2d381d19495c5ddf4f00def2e49703a80c..a617a5b8631b5e6fbba449d0b5d3f1ce62a2da3d 100644 (file)
--- a/src/gallium/drivers/r600/r600.h
+++ b/src/gallium/drivers/r600/r600.h
@@ -264,6 +264,7 @@ void r600_context_fini(struct r600_context *ctx);
 void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state);
 void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
 void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
+void r600_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
 void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 void r600_context_flush(struct r600_context *ctx);
@@ -284,9 +285,11 @@ int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon);
 void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *draw);
 void evergreen_ps_resource_set(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
 void evergreen_vs_resource_set(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
+void evergreen_fs_resource_set(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
 
 void evergreen_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
 void evergreen_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
+void evergreen_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
 void evergreen_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 void evergreen_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 

diff --git a/src/gallium/drivers/r600/r600_asm.c b/src/gallium/drivers/r600/r600_asm.c
index eed40d220933ff74302763f1d7c792531b9ca8d4..56a078d7e81ab29f2f0b02154513d433df3b37ee 100644 (file)
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -23,6 +23,7 @@
 #include <stdio.h>
 #include <errno.h>
 #include "util/u_memory.h"
+#include "pipe/p_shader_tokens.h"
 #include "r600_pipe.h"
 #include "r600_sq.h"
 #include "r600_opcodes.h"
@@ -592,10 +593,34 @@ int r600_bc_add_cfinst(struct r600_bc *bc, int inst)
 /* common to all 3 families */
 static int r600_bc_vtx_build(struct r600_bc *bc, struct r600_bc_vtx *vtx, unsigned id)
 {
-       bc->bytecode[id++] = S_SQ_VTX_WORD0_BUFFER_ID(vtx->buffer_id) |
-                               S_SQ_VTX_WORD0_SRC_GPR(vtx->src_gpr) |
-                               S_SQ_VTX_WORD0_SRC_SEL_X(vtx->src_sel_x) |
-                               S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx->mega_fetch_count);
+       unsigned fetch_resource_start = 0;
+
+       /* check if we are fetch shader */
+                       /* fetch shader can also access vertex resource,
+                        * first fetch shader resource is at 160
+                        */
+       if (bc->type == -1) {
+               switch (bc->chiprev) {
+               /* r600 */
+               case 0:
+               /* r700 */
+               case 1:
+                       fetch_resource_start = 160;
+                       break;
+               /* evergreen */
+               case 2:
+                       fetch_resource_start = 0;
+                       break;
+               default:
+                       fprintf(stderr,  "%s:%s:%d unknown chiprev %d\n",
+                               __FILE__, __func__, __LINE__, bc->chiprev);
+                       break;
+               }
+       }
+       bc->bytecode[id++] = S_SQ_VTX_WORD0_BUFFER_ID(vtx->buffer_id + fetch_resource_start) |
+                       S_SQ_VTX_WORD0_SRC_GPR(vtx->src_gpr) |
+                       S_SQ_VTX_WORD0_SRC_SEL_X(vtx->src_sel_x) |
+                       S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx->mega_fetch_count);
        bc->bytecode[id++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx->dst_sel_x) |
                                S_SQ_VTX_WORD1_DST_SEL_Y(vtx->dst_sel_y) |
                                S_SQ_VTX_WORD1_DST_SEL_Z(vtx->dst_sel_z) |
@@ -742,6 +767,8 @@ static int r600_bc_cf_build(struct r600_bc *bc, struct r600_bc_cf *cf)
        case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
        case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
        case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
+       case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
+       case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
                bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1);
                bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(cf->inst) |
                                        S_SQ_CF_WORD1_BARRIER(1) |
@@ -767,6 +794,9 @@ int r600_bc_build(struct r600_bc *bc)
 
        if (bc->callstack[0].max > 0)
                bc->nstack = ((bc->callstack[0].max + 3) >> 2) + 2;
+       if (bc->type == TGSI_PROCESSOR_VERTEX && !bc->nstack) {
+               bc->nstack = 1;
+       }
 
        /* first path compute addr of each CF block */
        /* addr start after all the CF instructions */
@@ -795,6 +825,8 @@ int r600_bc_build(struct r600_bc *bc)
                case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
                case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
                case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
+               case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
+               case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
                        break;
                default:
                        R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
@@ -868,6 +900,8 @@ int r600_bc_build(struct r600_bc *bc)
                case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
                case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
                case V_SQ_CF_WORD1_SQ_CF_INST_POP:
+               case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
+               case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
                        break;
                default:
                        R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);

diff --git a/src/gallium/drivers/r600/r600_asm.h b/src/gallium/drivers/r600/r600_asm.h
index 3295bf60ea65cf91503453fca953eaba7f3874a0..f2016af3e7264efa1eeceb4d7caa3012cbe0357b 100644 (file)
--- a/src/gallium/drivers/r600/r600_asm.h
+++ b/src/gallium/drivers/r600/r600_asm.h
@@ -170,6 +170,7 @@ struct r600_cf_callstack {
 struct r600_bc {
        enum radeon_family              family;
        int                             chiprev; /* 0 - r600, 1 - r700, 2 - evergreen */
+       int                             type;
        struct list_head                cf;
        struct r600_bc_cf               *cf_last;
        unsigned                        ndw;

diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h
index 1c691f6b764e261085823f8843ada03441c3350e..ba9fedf0b6cf55fea3ce3f5d4d8c777b1203aa7b 100644 (file)
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -93,6 +93,7 @@ struct r600_pipe_shader {
        struct r600_shader              shader;
        struct r600_pipe_state          rstate;
        struct r600_bo                  *bo;
+       struct r600_bo                  *bo_fetch;
        struct r600_vertex_element      vertex_elements;
 };
 

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index a9cce452345fac0d078db29bb93fd58910cf7569..a6e8345c25be698d9bd1bf37db04cbc155352983 100644 (file)
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -80,7 +80,7 @@ static void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shade
                        r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
        r600_pipe_state_add_reg(rstate,
                        R_028894_SQ_PGM_START_FS,
-                       r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
+                       r600_bo_offset(shader->bo_fetch) >> 8, 0xFFFFFFFF, shader->bo_fetch);
 
        r600_pipe_state_add_reg(rstate,
                                R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
@@ -217,6 +217,15 @@ static int r600_pipe_shader(struct pipe_context *ctx, struct r600_pipe_shader *s
        void *ptr;
 
        /* copy new shader */
+       if (rshader->processor_type == TGSI_PROCESSOR_VERTEX && shader->bo_fetch == NULL) {
+               shader->bo_fetch = r600_bo(rctx->radeon, rshader->bc_fetch.ndw * 4, 4096, 0, 0);
+               if (shader->bo_fetch == NULL) {
+                       return -ENOMEM;
+               }
+               ptr = r600_bo_map(rctx->radeon, shader->bo_fetch, 0, NULL);
+               memcpy(ptr, rshader->bc_fetch.bytecode, rshader->bc_fetch.ndw * 4);
+               r600_bo_unmap(rctx->radeon, shader->bo_fetch);
+       }
        if (shader->bo == NULL) {
                shader->bo = r600_bo(rctx->radeon, rshader->bc.ndw * 4, 4096, 0, 0);
                if (shader->bo == NULL) {
@@ -257,7 +266,7 @@ static int r600_shader_update(struct pipe_context *ctx, struct r600_pipe_shader
        const struct util_format_description *desc;
        enum pipe_format resource_format[160];
        unsigned i, nresources = 0;
-       struct r600_bc *bc = &shader->bc;
+       struct r600_bc *bc = &shader->bc_fetch;
        struct r600_bc_cf *cf;
        struct r600_bc_vtx *vtx;
 
@@ -272,7 +281,7 @@ static int r600_shader_update(struct pipe_context *ctx, struct r600_pipe_shader
        for (i = 0; i < rctx->vertex_elements->count; i++) {
                resource_format[nresources++] = rctx->vertex_elements->hw_format[i];
        }
-       r600_bo_reference(rctx->radeon, &rshader->bo, NULL);
+       r600_bo_reference(rctx->radeon, &rshader->bo_fetch, NULL);
        LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
                switch (cf->inst) {
                case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
@@ -293,7 +302,7 @@ static int r600_shader_update(struct pipe_context *ctx, struct r600_pipe_shader
                        break;
                }
        }
-       return r600_bc_build(&shader->bc);
+       return r600_bc_build(&shader->bc_fetch);
 }
 
 int r600_pipe_shader_update(struct pipe_context *ctx, struct r600_pipe_shader *shader)
@@ -334,6 +343,13 @@ int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *s
                R600_ERR("building bytecode failed !\n");
                return r;
        }
+       if (shader->shader.processor_type == TGSI_PROCESSOR_VERTEX) {
+               r = r600_bc_build(&shader->shader.bc_fetch);
+               if (r) {
+                       R600_ERR("building bytecode failed !\n");
+                       return r;
+               }
+       }
 //fprintf(stderr, "______________________________________________________________\n");
        return 0;
 }
@@ -364,6 +380,7 @@ struct r600_shader_ctx {
        unsigned                                temp_reg;
        struct r600_shader_tgsi_instruction     *inst_info;
        struct r600_bc                          *bc;
+       struct r600_bc                          *bc_fetch;
        struct r600_shader                      *shader;
        u32                                     value[4];
        u32                                     *literals;
@@ -511,7 +528,7 @@ static int tgsi_declaration(struct r600_shader_ctx *ctx)
                        vtx.dst_sel_z = 2;
                        vtx.dst_sel_w = 3;
                        vtx.use_const_fields = 1;
-                       r = r600_bc_add_vtx(ctx->bc, &vtx);
+                       r = r600_bc_add_vtx(ctx->bc_fetch, &vtx);
                        if (r)
                                return r;
                }
@@ -606,6 +623,7 @@ int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *s
        int i, r = 0, pos0;
 
        ctx.bc = &shader->bc;
+       ctx.bc_fetch = &shader->bc_fetch;
        ctx.shader = shader;
        r = r600_bc_init(ctx.bc, shader->family);
        if (r)
@@ -615,6 +633,13 @@ int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *s
        tgsi_parse_init(&ctx.parse, tokens);
        ctx.type = ctx.parse.FullHeader.Processor.Processor;
        shader->processor_type = ctx.type;
+       if (shader->processor_type == TGSI_PROCESSOR_VERTEX) {
+               r = r600_bc_init(ctx.bc_fetch, shader->family);
+               if (r)
+                       return r;
+               ctx.bc_fetch->type = -1;
+       }
+       ctx.bc->type = shader->processor_type;
 
        /* register allocations */
        /* Values [0,127] correspond to GPR[0..127].
@@ -640,6 +665,11 @@ int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *s
        }
        if (ctx.type == TGSI_PROCESSOR_VERTEX) {
                ctx.file_offset[TGSI_FILE_INPUT] = 1;
+               if (ctx.bc->chiprev == 2) {
+                       r600_bc_add_cfinst(ctx.bc, EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS);
+               } else {
+                       r600_bc_add_cfinst(ctx.bc, V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS);
+               }
        }
        if (ctx.type == TGSI_PROCESSOR_FRAGMENT && ctx.bc->chiprev == 2) {
                ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
@@ -809,6 +839,14 @@ int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *s
                        output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE);
                }
        }
+       /* add return to fetch shader */
+       if (ctx.type == TGSI_PROCESSOR_VERTEX) {
+               if (ctx.bc->chiprev == 2) {
+                       r600_bc_add_cfinst(ctx.bc_fetch, EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN);
+               } else {
+                       r600_bc_add_cfinst(ctx.bc_fetch, V_SQ_CF_WORD1_SQ_CF_INST_RETURN);
+               }
+       }
        /* add output to bytecode */
        for (i = 0; i < noutput; i++) {
                r = r600_bc_add_output(ctx.bc, &output[i]);

diff --git a/src/gallium/drivers/r600/r600_shader.h b/src/gallium/drivers/r600/r600_shader.h
index f8bc59513954916819929d4002d0a63f56d3a212..cd108da49153171a564cbce0061c448acbabe9bb 100644 (file)
--- a/src/gallium/drivers/r600/r600_shader.h
+++ b/src/gallium/drivers/r600/r600_shader.h
@@ -46,6 +46,7 @@ struct r600_shader {
        struct r600_shader_io   output[32];
        enum radeon_family      family;
        boolean                 uses_kill;
+       struct r600_bc          bc_fetch;
 };
 
 int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader);

diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index f97f28795047f6c1bbd2c18770ae3dca82f9a0c1..3d876e775ea48cf9dd91325cc2d766e64fc9f8e1 100644 (file)
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -109,7 +109,7 @@ static void r600_draw_common(struct r600_drawl *draw)
                r600_pipe_state_add_reg(rstate, R_038010_RESOURCE0_WORD4, 0x00000000, 0xFFFFFFFF, NULL);
                r600_pipe_state_add_reg(rstate, R_038014_RESOURCE0_WORD5, 0x00000000, 0xFFFFFFFF, NULL);
                r600_pipe_state_add_reg(rstate, R_038018_RESOURCE0_WORD6, 0xC0000000, 0xFFFFFFFF, NULL);
-               r600_context_pipe_state_set_vs_resource(&rctx->ctx, rstate, i);
+               r600_context_pipe_state_set_fs_resource(&rctx->ctx, rstate, i);
        }
 
        mask = 0;

diff --git a/src/gallium/winsys/r600/drm/evergreen_hw_context.c b/src/gallium/winsys/r600/drm/evergreen_hw_context.c
index 7f21b53ace02ecfe807ffed08a61e2242206ed89..b93cc650272e67851245c6f60e2f9ea9c7a9aab1 100644 (file)
--- a/src/gallium/winsys/r600/drm/evergreen_hw_context.c
+++ b/src/gallium/winsys/r600/drm/evergreen_hw_context.c
@@ -577,6 +577,12 @@ int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon)
                if (r)
                        goto out_err;
        }
+       /* FS RESOURCE */
+       for (int j = 0, offset = 0x7C00; j < 16; j++, offset += 0x20) {
+               r = evergreen_state_resource_init(ctx, offset);
+               if (r)
+                       goto out_err;
+       }
 
        /* PS loop const */
        evergreen_loop_const_init(ctx, 0);
@@ -686,6 +692,13 @@ void evergreen_context_pipe_state_set_vs_resource(struct r600_context *ctx, stru
        evergreen_context_pipe_state_set_resource(ctx, state, offset);
 }
 
+void evergreen_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid)
+{
+       unsigned offset = R_030000_SQ_TEX_RESOURCE_WORD0_0 + 0x7C00 + 0x20 * rid;
+
+       evergreen_context_pipe_state_set_resource(ctx, state, offset);
+}
+
 static inline void evergreen_context_pipe_state_set_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
 {
        struct r600_range *range;
@@ -917,3 +930,10 @@ void evergreen_vs_resource_set(struct r600_context *ctx, struct r600_pipe_state
 
        evergreen_resource_set(ctx, state, offset);
 }
+
+void evergreen_fs_resource_set(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid)
+{
+       unsigned offset = R_030000_RESOURCE0_WORD0 + 0x7C00 + 0x20 * rid;
+
+       evergreen_resource_set(ctx, state, offset);
+}

diff --git a/src/gallium/winsys/r600/drm/r600_hw_context.c b/src/gallium/winsys/r600/drm/r600_hw_context.c
index 71a531f535f188a3879ae38bc27c8d479b6d606d..de228918953590f91722ee2358ee027252b0dc29 100644 (file)
--- a/src/gallium/winsys/r600/drm/r600_hw_context.c
+++ b/src/gallium/winsys/r600/drm/r600_hw_context.c
@@ -706,6 +706,12 @@ int r600_context_init(struct r600_context *ctx, struct radeon *radeon)
                if (r)
                        goto out_err;
        }
+       /* FS RESOURCE */
+       for (int j = 0, offset = 0x2300; j < 16; j++, offset += 0x1C) {
+               r = r600_state_resource_init(ctx, offset);
+               if (r)
+                       goto out_err;
+       }
 
        /* PS loop const */
        r600_loop_const_init(ctx, 0);
@@ -893,6 +899,13 @@ void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r6
        r600_context_pipe_state_set_resource(ctx, state, offset);
 }
 
+void r600_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid)
+{
+       unsigned offset = R_038000_SQ_TEX_RESOURCE_WORD0_0 + 0x2300 + 0x1C * rid;
+
+       r600_context_pipe_state_set_resource(ctx, state, offset);
+}
+
 static inline void r600_context_pipe_state_set_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
 {
        struct r600_range *range;