add VexRiscv submodule

diff --git a/.gitmodules b/.gitmodules
index 69988365be41d1345c7a1543c44eab3c4acaf17e..26af8537e81648def9d1cdbb5059ba3b7fc4f5cd 100644 (file)
--- a/.gitmodules
+++ b/.gitmodules
@@ -13,3 +13,6 @@
 [submodule "litex/build/sim/core/modules/ethernet/tapcfg"]
        path = litex/build/sim/core/modules/ethernet/tapcfg
        url = https://github.com/nizox/tapcfg
+[submodule "litex/soc/cores/cpu/vexriscv/verilog"]
+       path = litex/soc/cores/cpu/vexriscv/verilog
+       url = https://github.com/m-labs/VexRiscv-verilog.git

diff --git a/litex/soc/cores/cpu/vexriscv/verilog b/litex/soc/cores/cpu/vexriscv/verilog
new file mode 160000 (submodule)
index 0000000..4811a12
--- /dev/null
+++ b/litex/soc/cores/cpu/vexriscv/verilog
@@ -0,0 +1 @@
+Subproject commit 4811a12127eef5dfaaa8df47a59e58a1e561b0eb