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diff --git a/meetings/dmitry_2023-11-24.mdwn b/meetings/dmitry_2023-11-24.mdwn
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@@ -1,7 +1,8 @@
 # Friday 24th November 17:00 UTC
 
 - A meeting with Dmitry, David, James, Luke, and Andrey to explain the
-new grants for extending SV for RISC-V.
+new grants for updating Simple-V for RISC-V (first implemented 4 years
+ago, now in need of an update)
 
 Main points to take away:
 
@@ -28,6 +29,7 @@ full feature set of SimpleV. Link to LibreSOC'
 - [[nlnet_2023_simplev_riscv_binutils]]
 
 - Primarily Dmitry doing most of the work.
+- Communication on Simple-V formats to be defined by luke and jacob
 
 ## Primary Tasks
 
@@ -43,15 +45,15 @@ full feature set of SimpleV. Link to LibreSOC'
      - SVP48 (16+32) - 16-bit prefix for 32-bit instructions.
      - SVP64 (32+32) - 32-bit prefix for 64-bit instructions.
 
-The 16-bit prefix saves instruction space in memory
-(but with limited feature set).
-
-The 32-bit prefix gives full access to SimpleV feature set
-(128 reg's, all SV modes such as data dependent fail-first, etc.)
+* The 16-bit prefix saves instruction space in memory
+ (but with limited feature set: 128 regs span but cruder spacing).
+* The 32-bit prefix gives full access to SimpleV feature set
+ (128 regs, all SV modes such as data dependent fail-first, etc.)
 
 # Defining SVPxxSingle
 
 Another point mentioned after Dmitry left is the need to define SVPxxSingle.
+[[sv/svp64-single]]
 
 For both RISC-V and PowerISA need to define: