Missing endmodule

diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v
index b302e46f61fb195f80200da542ab7c2004918579..8255804c2813b3bfdbbe06e220b2fa1af4a02214 100644 (file)
--- a/techlibs/xilinx/abc_model.v
+++ b/techlibs/xilinx/abc_model.v
@@ -35,6 +35,7 @@ endmodule
 
 (* abc_box_id = 1000 *)
 module \$__ABC_ASYNC (input A, S, output Y);
+endmodule
 
 // Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32}
 //   Necessary since RAMD* and SRL* have both combinatorial (i.e.