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diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index 7e86257e40b922596abf41a5efcb46a1d47fa393..601a9bb28eb798cf39bea7b5d4c4ce078a3eccef 100644 (file)
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -9,7 +9,8 @@ has no meaning. Consequently an alternative Mode Format is required.
 This alternative mapping **only** applies to instructions that **only**
 reference a CR Field or CR bit as the sole exclusive result. This section
 **does not** apply to instructions which primarily produce arithmetic
-results that also produce a CR Field (such as when Rc=1).
+results that also, as an aside, produce a corresponding
+CR Field (such as when Rc=1).
 Instructions that involve Rc=1 are definitively arithmetic in nature,
 where the corresponding Condition Register Field can be considered to
 be a "co-result". Thus, if the arithmetic result is Vectorised, so