+2019-09-17 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/arm/types.md (no_reservation): New reservation.
+ * config/aarch64/falkor.md (falkor_other_0_nothing): Don't handle
+ no_insn here.
+ * config/aarch64/saphira.md (saphira_other_0_nothing): Likewise.
+ * config/aarch64/thunderx2t99.md (thunderx2t99_nothing): Likewise.
+ * config/aarch64/tsv110.md (tsv110_alu): Likewise.
+ * config/arm/arm1020e.md (1020alu_op): Likewise.
+ * config/arm/arm1026ejs.md (alu_op): Likewise.
+ * config/arm/arm1136jfs.md (11_alu_op): Likewise.
+ * config/arm/arm926ejs.md (9_alu_op): Likewise.
+ * config/arm/cortex-a15.md (cortex_a15_alu): Likewise.
+ * config/arm/cortex-a17.md (cortex_a17_alu): Likewise.
+ * config/arm/cortex-a5.md (cortex_a5_alu): Likewise.
+ * config/arm/cortex-a53.md (cortex_a53_alu): Likewise.
+ * config/arm/cortex-a57.md (cortex_a57_alu): Likewise.
+ * config/arm/cortex-a7.md (cortex_a7_alu_shift): Likewise.
+ * config/arm/cortex-a8.md (cortex_a8_alu): Likewise.
+ * config/arm/cortex-a9.md (cortex_a9_dp): Likewise.
+ * config/arm/cortex-m4.md (cortex_m4_alu): Likewise.
+ * config/arm/cortex-m7.md (cortex_m7_alu_simple): Likewise.
+ * config/arm/cortex-r4.md (cortex_r4_alu_shift_reg): Likewise.
+ * config/arm/fa526.md (526_alu_op): Likewise.
+ * config/arm/fa606te.md (606te_alu_op): Likewise.
+ * config/arm/fa626te.md (626te_alu_op): Likewise.
+ * config/arm/fa726te.md (726te_alu_op): Likewise.
+ * config/arm/xgene1.md (xgene1_nop): Likewise.
+
2019-09-17 Richard Sandiford <richard.sandiford@arm.com>
* config/arm/thumb1.md (*thumb1_tablejump): Change type from
(define_insn_reservation "falkor_other_0_nothing" 0
(and (eq_attr "tune" "falkor")
- (eq_attr "type" "no_insn,trap,block"))
+ (eq_attr "type" "trap,block"))
"nothing")
(define_insn_reservation "falkor_other_2_z" 2
(define_insn_reservation "saphira_other_0_nothing" 0
(and (eq_attr "tune" "saphira")
- (eq_attr "type" "no_insn,trap,block"))
+ (eq_attr "type" "trap,block"))
"nothing")
(define_insn_reservation "saphira_other_2_ld" 2
(define_insn_reservation "thunderx2t99_nothing" 0
(and (eq_attr "tune" "thunderx2t99")
- (eq_attr "type" "no_insn,block"))
+ (eq_attr "type" "block"))
"nothing")
(define_insn_reservation "thunderx2t99_mrs" 0
shift_imm,shift_reg,\
mov_imm,mov_reg,\
mvn_imm,mvn_reg,\
- mrs,multiple,no_insn"))
+ mrs,multiple"))
"tsv110_alu1|tsv110_alu2|tsv110_alu3")
(define_insn_reservation "tsv110_alus" 1
adr,bfm,rev,\
shift_imm,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg,\
- multiple,no_insn"))
+ multiple"))
"1020a_e,1020a_m,1020a_w")
;; ALU operations with a shift-by-constant operand
adr,bfm,rev,\
shift_imm,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg,\
- multiple,no_insn"))
+ multiple"))
"a_e,a_m,a_w")
;; ALU operations with a shift-by-constant operand
adr,bfm,rev,\
shift_imm,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg,\
- multiple,no_insn"))
+ multiple"))
"e_1,e_2,e_3,e_wb")
;; ALU operations with a shift-by-constant operand
shift_imm,shift_reg,extend,\
mov_imm,mov_reg,mov_shift,\
mvn_imm,mvn_reg,mvn_shift,\
- multiple,no_insn"))
+ multiple"))
"e,m,w")
;; ALU operations with a shift-by-register operand
shift_imm,shift_reg,\
mov_imm,mov_reg,\
mvn_imm,mvn_reg,\
- mrs,multiple,no_insn"))
+ mrs,multiple"))
"ca15_issue1,(ca15_sx1,ca15_sx1_alu)|(ca15_sx2,ca15_sx2_alu)")
;; ALU ops with immediate shift
adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr, mov_imm,mov_reg,\
mvn_imm,mvn_reg,extend,\
- mrs,multiple,no_insn"))
+ mrs,multiple"))
"ca17_alu")
(define_insn_reservation "cortex_a17_alu_shiftimm" 2
adr,bfm,clz,rbit,rev,alu_dsp_reg,\
shift_imm,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg,\
- mrs,multiple,no_insn"))
+ mrs,multiple"))
"cortex_a5_ex1")
(define_insn_reservation "cortex_a5_alu_shift" 2
alu_sreg,alus_sreg,logic_reg,logics_reg,
adc_imm,adcs_imm,adc_reg,adcs_reg,
csel,clz,rbit,rev,alu_dsp_reg,
- mov_reg,mvn_reg,mrs,multiple,no_insn"))
+ mov_reg,mvn_reg,mrs,multiple"))
"cortex_a53_slot_any")
(define_insn_reservation "cortex_a53_alu_shift" 3
rotate_imm,shift_imm,shift_reg,\
mov_imm,mov_reg,\
mvn_imm,mvn_reg,\
- mrs,multiple,no_insn"))
+ mrs,multiple"))
"ca57_sx1|ca57_sx2")
;; ALU ops with immediate shift
logic_shift_reg,logics_shift_reg,\
mov_shift,mov_shift_reg,\
mvn_shift,mvn_shift_reg,\
- mrs,multiple,no_insn"))
+ mrs,multiple"))
"cortex_a7_ex1")
;; Forwarding path for unshifted operands.
adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,clz,rbit,rev,alu_dsp_reg,\
shift_imm,shift_reg,\
- multiple,no_insn"))
+ multiple"))
"cortex_a8_default")
(define_insn_reservation "cortex_a8_alu_shift" 2
shift_imm,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg,\
mov_shift_reg,mov_shift,\
- mrs,multiple,no_insn"))
+ mrs,multiple"))
"cortex_a9_p0_default|cortex_a9_p1_default")
;; An instruction using the shifter will go down E1.
logic_shift_reg,logics_shift_reg,\
mov_imm,mov_reg,mov_shift,mov_shift_reg,\
mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg,\
- mrs,multiple,no_insn")
+ mrs,multiple")
(ior (eq_attr "mul32" "yes")
(eq_attr "widen_mul64" "yes"))))
"cortex_m4_ex")
logic_shift_imm,logics_shift_imm,\
alu_shift_reg,alus_shift_reg,\
logic_shift_reg,logics_shift_reg,\
- mrs,clz,f_mcr,f_mrc,multiple,no_insn"))
+ mrs,clz,f_mcr,f_mrc,multiple"))
"cm7_i0|cm7_i1,cm7_a0|cm7_a1")
;; Simple alu with inline shift operation.
(eq_attr "type" "alu_shift_reg,alus_shift_reg,\
logic_shift_reg,logics_shift_reg,\
mov_shift_reg,mvn_shift_reg,\
- mrs,multiple,no_insn"))
+ mrs,multiple"))
"cortex_r4_alu_shift_reg")
;; An ALU instruction followed by an ALU instruction with no early dep.
adr,bfm,rev,\
shift_imm,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg,\
- mrs,multiple,no_insn"))
+ mrs,multiple"))
"fa526_core")
(define_insn_reservation "526_alu_shift_op" 2
logic_shift_reg,logics_shift_reg,\
mov_imm,mov_reg,mov_shift,mov_shift_reg,\
mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg,\
- mrs,multiple,no_insn"))
+ mrs,multiple"))
"fa606te_core")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
adr,bfm,rev,\
shift_imm,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg,\
- mrs,multiple,no_insn"))
+ mrs,multiple"))
"fa626te_core")
(define_insn_reservation "626te_alu_shift_op" 2
adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,rev,\
shift_imm,shift_reg,\
- mrs,multiple,no_insn"))
+ mrs,multiple"))
"fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)")
;; ALU operations with a shift-by-register operand.
crypto_sha256_fast, crypto_sha256_slow")
(const_string "yes")
(const_string "no")))
+
+(define_insn_reservation "no_reservation" 0
+ (eq_attr "type" "no_insn")
+ "nothing")
(eq_attr "type" "branch"))
"xgene1_decode1op")
-(define_insn_reservation "xgene1_nop" 1
- (and (eq_attr "tune" "xgene1")
- (eq_attr "type" "no_insn"))
- "xgene1_decode1op")
-
(define_insn_reservation "xgene1_call" 1
(and (eq_attr "tune" "xgene1")
(eq_attr "type" "call"))
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