targets/sim: add rom-init

diff --git a/litex/boards/targets/sim.py b/litex/boards/targets/sim.py
index a11f9149ca72283212e3d4064b52bf5f66b9c3d9..447ee1c608aeebf6c74efeb37753c83434d2db17 100755 (executable)
--- a/litex/boards/targets/sim.py
+++ b/litex/boards/targets/sim.py
@@ -144,6 +144,8 @@ def main():
     parser = argparse.ArgumentParser(description="Generic LiteX SoC Simulation")
     builder_args(parser)
     soc_sdram_args(parser)
+    parser.add_argument("--rom-init", default=None,
+                        help="rom_init file")
     parser.add_argument("--ram-init", default=None,
                         help="ram_init file")
     parser.add_argument("--with-sdram", action="store_true",
@@ -156,15 +158,17 @@ def main():
                         help="enable Analyzer support")
     args = parser.parse_args()
 
+    kwargs = soc_sdram_argdict(args)
+
     sim_config = SimConfig(default_clk="sys_clk")
     sim_config.add_module("serial2console", "serial")
-    integrated_main_ram_init = []
+    if args.rom_init:
+        kwargs["integrated_rom_init"] = get_mem_data(args.rom_init)
+    kwargs["integrated_main_ram_size"] = 0x10000
     if not args.with_sdram:
         if args.ram_init is not None:
-            integrated_main_ram_init = get_mem_data(args.ram_init)
-            integrated_main_ram_size = max(len(integrated_main_ram_init), 0x10000)
-    else:
-        integrated_main_ram_size = 0
+            kwargs["integrated_main_ram_init"] = get_mem_data(args.ram_init)
+            kwargs["integrated_main_ram_size"] = max(len(kwargs["integrated_main_ram_init"]), 0x10000)
     if args.with_ethernet:
         sim_config.add_module("ethernet", "eth", args={"interface": "tap0", "ip": "192.168.1.100"})
     if args.with_etherbone:
@@ -174,9 +178,7 @@ def main():
         with_ethernet=args.with_ethernet,
         with_etherbone=args.with_etherbone,
         with_analyzer=args.with_analyzer,
-        integrated_main_ram_size=integrated_main_ram_size,
-        integrated_main_ram_init=integrated_main_ram_init,
-        **soc_sdram_argdict(args))
+        **kwargs)
     builder = Builder(soc, **builder_argdict(args))
     builder.build(sim_config=sim_config)