Replace them with std::array<>s.
Change-Id: I76624c87a1cd9b21c386a96147a18de92b8a8a34
Reviewed-on: https://gem5-review.googlesource.com/6602
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
'''
elif self.size == 16:
accCode = '''
- Twin64_t data = cSwap(Mem%s,
- isBigEndian64(xc->tcBase()));
-
-
- AA64FpDestP0_uw = (uint32_t)data.a;
- AA64FpDestP1_uw = (data.a >> 32);
- AA64FpDestP2_uw = (uint32_t)data.b;
- AA64FpDestP3_uw = (data.b >> 32);
+ auto data = cSwap(Mem%s, isBigEndian64(xc->tcBase()));
+ AA64FpDestP0_uw = (uint32_t)data[0];
+ AA64FpDestP1_uw = (data[0] >> 32);
+ AA64FpDestP2_uw = (uint32_t)data[1];
+ AA64FpDestP3_uw = (data[1] >> 32);
'''
elif self.flavor == "widen" or self.size == 8:
accCode = "XDest = cSwap(Mem%s, isBigEndian64(xc->tcBase()));"
'''
elif self.size == 8:
accCode = '''
- AA64FpDestP0_uw = (uint32_t)Mem_tud.a;
- AA64FpDestP1_uw = (uint32_t)(Mem_tud.a >> 32);
+ AA64FpDestP0_uw = (uint32_t)Mem_tud[0];
+ AA64FpDestP1_uw = (uint32_t)(Mem_tud[0] >> 32);
AA64FpDestP2_uw = 0;
AA64FpDestP3_uw = 0;
- AA64FpDest2P0_uw = (uint32_t)Mem_tud.b;
- AA64FpDest2P1_uw = (uint32_t)(Mem_tud.b >> 32);
+ AA64FpDest2P0_uw = (uint32_t)Mem_tud[1];
+ AA64FpDest2P1_uw = (uint32_t)(Mem_tud[1] >> 32);
AA64FpDest2P2_uw = 0;
AA64FpDest2P3_uw = 0;
'''
'''
elif self.size == 8:
accCode = '''
- XDest = Mem_tud.a;
- XDest2 = Mem_tud.b;
+ XDest = Mem_tud[0];
+ XDest2 = Mem_tud[1];
'''
else:
if self.size == 4:
'''
elif self.size == 8:
accCode = '''
- XDest = Mem_tud.a;
- XDest2 = Mem_tud.b;
+ XDest = Mem_tud[0];
+ XDest2 = Mem_tud[1];
'''
self.codeBlobs["memacc_code"] = accCode
accCode = '''
// This temporary needs to be here so that the parser
// will correctly identify this instruction as a store.
- Twin64_t temp;
- temp.a = XDest_ud;
- temp.b = XDest2_ud;
+ std::array<uint64_t, 2> temp;
+ temp[0] = XDest_ud;
+ temp[1] = XDest2_ud;
Mem_tud = temp;
'''
self.codeBlobs["memacc_code"] = accCode
'sw' : 'int32_t',
'uw' : 'uint32_t',
'ud' : 'uint64_t',
- 'tud' : 'Twin64_t',
+ 'tud' : 'std::array<uint64_t, 2>',
'sf' : 'float',
'df' : 'double',
'vc' : 'TheISA::VecRegContainer',
xc->writeMem((uint8_t *)&host_mem, sizeof(MemT), addr, flags, res);
if (fault == NoFault && res != NULL) {
if (flags & Request::MEM_SWAP || flags & Request::MEM_SWAP_COND)
- *res = TheISA::gtoh((MemT)*res);
+ *(MemT *)res = TheISA::gtoh(*(MemT *)res);
else
*res = TheISA::gtoh(*res);
}
0x01: ldub({{Rd = Mem_ub;}});
0x02: lduh({{Rd = Mem_uhw;}});
0x03: ldtw({{
- RdLow = (Mem_tuw).a;
- RdHigh = (Mem_tuw).b;
+ RdLow = Mem_tuw[0];
+ RdHigh = Mem_tuw[1];
}});
}
format Store {
// will correctly identify this instruction as a store.
// It's probably either the parenthesis or referencing
// the member variable that throws confuses it.
- Twin32_t temp;
- temp.a = RdLow<31:0>;
- temp.b = RdHigh<31:0>;
+ std::array<uint32_t, 2> temp;
+ temp[0] = RdLow<31:0>;
+ temp[1] = RdHigh<31:0>;
Mem_tuw = temp;
}});
}
0x13: decode EXT_ASI {
// ASI_LDTD_AIUP
0x22: TwinLoad::ldtx_aiup(
- {{RdLow_udw = (Mem_tudw).a;
- RdHigh_udw = (Mem_tudw).b;}});
+ {{RdLow_udw = Mem_tudw[0];
+ RdHigh_udw = Mem_tudw[1];}});
// ASI_LDTD_AIUS
0x23: TwinLoad::ldtx_aius(
- {{RdLow_udw = (Mem_tudw).a;
- RdHigh_udw = (Mem_tudw).b;}});
+ {{RdLow_udw = Mem_tudw[0];
+ RdHigh_udw = Mem_tudw[1];}});
// ASI_QUAD_LDD
0x24: TwinLoad::ldtx_quad_ldd(
- {{RdLow_udw = (Mem_tudw).a;
- RdHigh_udw = (Mem_tudw).b;}});
+ {{RdLow_udw = Mem_tudw[0];
+ RdHigh_udw = Mem_tudw[1];}});
// ASI_LDTX_REAL
0x26: TwinLoad::ldtx_real(
- {{RdLow_udw = (Mem_tudw).a;
- RdHigh_udw = (Mem_tudw).b;}});
+ {{RdLow_udw = Mem_tudw[0];
+ RdHigh_udw = Mem_tudw[1];}});
// ASI_LDTX_N
0x27: TwinLoad::ldtx_n(
- {{RdLow_udw = (Mem_tudw).a;
- RdHigh_udw = (Mem_tudw).b;}});
+ {{RdLow_udw = Mem_tudw[0];
+ RdHigh_udw = Mem_tudw[1];}});
// ASI_LDTX_AIUP_L
0x2A: TwinLoad::ldtx_aiup_l(
- {{RdLow_udw = (Mem_tudw).a;
- RdHigh_udw = (Mem_tudw).b;}});
+ {{RdLow_udw = Mem_tudw[0];
+ RdHigh_udw = Mem_tudw[1];}});
// ASI_LDTX_AIUS_L
0x2B: TwinLoad::ldtx_aius_l(
- {{RdLow_udw = (Mem_tudw).a;
- RdHigh_udw = (Mem_tudw).b;}});
+ {{RdLow_udw = Mem_tudw[0];
+ RdHigh_udw = Mem_tudw[1];}});
// ASI_LDTX_L
0x2C: TwinLoad::ldtx_l(
- {{RdLow_udw = (Mem_tudw).a;
- RdHigh_udw = (Mem_tudw).b;}});
+ {{RdLow_udw = Mem_tudw[0];
+ RdHigh_udw = Mem_tudw[1];}});
// ASI_LDTX_REAL_L
0x2E: TwinLoad::ldtx_real_l(
- {{RdLow_udw = (Mem_tudw).a;
- RdHigh_udw = (Mem_tudw).b;}});
+ {{RdLow_udw = Mem_tudw[0];
+ RdHigh_udw = Mem_tudw[1];}});
// ASI_LDTX_N_L
0x2F: TwinLoad::ldtx_n_l(
- {{RdLow_udw = (Mem_tudw).a;
- RdHigh_udw = (Mem_tudw).b;}});
+ {{RdLow_udw = Mem_tudw[0];
+ RdHigh_udw = Mem_tudw[1];}});
// ASI_LDTX_P
0xE2: TwinLoad::ldtx_p(
- {{RdLow_udw = (Mem_tudw).a;
- RdHigh_udw = (Mem_tudw).b;}});
+ {{RdLow_udw = Mem_tudw[0];
+ RdHigh_udw = Mem_tudw[1];}});
// ASI_LDTX_S
0xE3: TwinLoad::ldtx_s(
- {{RdLow_udw = (Mem_tudw).a;
- RdHigh_udw = (Mem_tudw).b;}});
+ {{RdLow_udw = Mem_tudw[0];
+ RdHigh_udw = Mem_tudw[1];}});
// ASI_LDTX_PL
0xEA: TwinLoad::ldtx_pl(
- {{RdLow_udw = (Mem_tudw).a;
- RdHigh_udw = (Mem_tudw).b;}});
+ {{RdLow_udw = Mem_tudw[0];
+ RdHigh_udw = Mem_tudw[1];}});
// ASI_LDTX_SL
0xEB: TwinLoad::ldtx_sl(
- {{RdLow_udw = (Mem_tudw).a;
- RdHigh_udw = (Mem_tudw).b;}});
+ {{RdLow_udw = Mem_tudw[0];
+ RdHigh_udw = Mem_tudw[1];}});
default: ldtwa({{
- RdLow = (Mem_tuw).a;
- RdHigh = (Mem_tuw).b;}});
+ RdLow = Mem_tuw[0];
+ RdHigh = Mem_tuw[1];}});
}
}
format StoreAlt {
// will correctly identify this instruction as a store.
// It's probably either the parenthesis or referencing
// the member variable that throws confuses it.
- Twin32_t temp;
- temp.a = RdLow<31:0>;
- temp.b = RdHigh<31:0>;
+ std::array<uint32_t, 2> temp;
+ temp[0] = RdLow<31:0>;
+ temp[1] = RdHigh<31:0>;
Mem_tuw = temp;
}});
}
#include "arch/generic/memhelpers.hh"
#include "arch/sparc/asi.hh"
-#include "base/bigint.hh"
#include "cpu/base.hh"
#include "cpu/exetrace.hh"
#include "debug/Sparc.hh"
'uw' : 'uint32_t',
'sdw' : 'int64_t',
'udw' : 'uint64_t',
- 'tudw' : 'Twin64_t',
- 'tuw' : 'Twin32_t',
+ 'tudw' : 'std::array<uint64_t, 2>',
+ 'tuw' : 'std::array<uint32_t, 2>',
'sf' : 'float',
'df' : 'double',
#define __ARCH_SPARC_TYPES_HH__
#include "arch/generic/types.hh"
-#include "base/bigint.hh"
#include "base/types.hh"
namespace SparcISA
#include "arch/x86/faults.hh"
#include "arch/x86/memhelpers.hh"
#include "arch/x86/tlb.hh"
-#include "base/bigint.hh"
#include "base/compiler.hh"
#include "base/condcodes.hh"
#include "cpu/base.hh"
SimObject('Graphics.py')
Source('atomicio.cc')
Source('bitfield.cc')
-Source('bigint.cc')
Source('imgwriter.cc')
Source('bmpwriter.cc')
Source('callback.cc')
+++ /dev/null
-/*
- * Copyright (c) 2006 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- */
-
-#include "base/bigint.hh"
-
-#include <iostream>
-
-using namespace std;
-
-ostream & operator << (ostream & os, const Twin64_t & t)
-{
- os << t.a << ", " << t.b;
- return os;
-}
-
-ostream & operator << (ostream & os, const Twin32_t & t)
-{
- os << t.a << ", " << t.b;
- return os;
-}
+++ /dev/null
-/*
- * Copyright (c) 2006 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Ali Saidi
- */
-
-#include <iostream>
-
-#include "base/logging.hh"
-#include "base/types.hh"
-
-#ifndef __BASE_BIGINT_HH__
-#define __BASE_BIGINT_HH__
-// Create a couple of large int types for atomic reads
-struct m5_twin64_t {
- uint64_t a;
- uint64_t b;
- m5_twin64_t() : a(0), b(0)
- {}
- m5_twin64_t(const uint64_t x) : a(x), b(x)
- {}
- inline m5_twin64_t& operator=(const uint64_t x)
- {
- a = x;
- b = x;
- return *this;
- }
-
- operator uint64_t()
- {
- panic("Tried to cram a twin64_t into an integer!\n");
- return a;
- }
-};
-
-struct m5_twin32_t {
- uint32_t a;
- uint32_t b;
- m5_twin32_t()
- {}
- m5_twin32_t(const uint32_t x)
- {
- a = x;
- b = x;
- }
- inline m5_twin32_t& operator=(const uint32_t x)
- {
- a = x;
- b = x;
- return *this;
- }
-
- operator uint32_t()
- {
- panic("Tried to cram a twin32_t into an integer!\n");
- return a;
- }
-};
-
-
-// This is for twin loads (two 64 bit values), not 1 128 bit value (as far as
-// endian conversion is concerned!
-typedef m5_twin64_t Twin64_t;
-typedef m5_twin32_t Twin32_t;
-
-// Output operator overloads
-std::ostream & operator << (std::ostream & os, const Twin64_t & t);
-std::ostream & operator << (std::ostream & os, const Twin32_t & t);
-
-#endif // __BASE_BIGINT_HH__
-
#include "arch/locked_mem.hh"
#include "arch/mmapped_ipr.hh"
#include "arch/utility.hh"
-#include "base/bigint.hh"
#include "base/output.hh"
#include "config/the_isa.hh"
#include "cpu/exetrace.hh"
#include "arch/locked_mem.hh"
#include "arch/mmapped_ipr.hh"
#include "arch/utility.hh"
-#include "base/bigint.hh"
#include "config/the_isa.hh"
#include "cpu/exetrace.hh"
#include "debug/Config.hh"
*/
#include "arch/isa_traits.hh"
-#include "base/bigint.hh"
#include "config/the_isa.hh"
#include "mem/packet.hh"
#include "sim/byteswap.hh"
#ifndef __SIM_BYTE_SWAP_HH__
#define __SIM_BYTE_SWAP_HH__
-#include "base/bigint.hh"
#include "base/types.hh"
// This lets us figure out what the byte order of the host system is
panic("Can't byte-swap values larger than 64 bits");
}
-template<>
-inline Twin64_t swap_byte<Twin64_t>(Twin64_t x)
-{
- x.a = swap_byte(x.a);
- x.b = swap_byte(x.b);
- return x;
-}
-
-template<>
-inline Twin32_t swap_byte<Twin32_t>(Twin32_t x)
-{
- x.a = swap_byte(x.a);
- x.b = swap_byte(x.b);
- return x;
-}
-
template <typename T, size_t N>
inline std::array<T, N>
swap_byte(std::array<T, N> a)
#ifndef __INSTRECORD_HH__
#define __INSTRECORD_HH__
-#include "base/bigint.hh"
#include "base/types.hh"
#include "cpu/inst_seq.hh"
#include "cpu/static_inst.hh"
/** @ingroup data
* What size of data was written?
*/
- enum {
+ enum DataStatus {
DataInvalid = 0,
DataInt8 = 1, // set to equal number of bytes
DataInt16 = 2,
addr = a; size = s; flags = f; mem_valid = true;
}
- void setData(Twin64_t d) { data.as_int = d.a; data_status = DataInt64; }
- void setData(Twin32_t d) { data.as_int = d.a; data_status = DataInt32; }
+ template <typename T, size_t N>
+ void
+ setData(std::array<T, N> d)
+ {
+ data.as_int = d[0];
+ data_status = (DataStatus)sizeof(T);
+ static_assert(sizeof(T) == DataInt8 || sizeof(T) == DataInt16 ||
+ sizeof(T) == DataInt32 || sizeof(T) == DataInt64,
+ "Type T has an unrecognized size.");
+ }
+
void setData(uint64_t d) { data.as_int = d; data_status = DataInt64; }
void setData(uint32_t d) { data.as_int = d; data_status = DataInt32; }
void setData(uint16_t d) { data.as_int = d; data_status = DataInt16; }
projects / gem5.git / commitdiff