Clean up pseudo-private member usage in `backends/verilog/verilog_backend.cc`.

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 19541f1c46e95cf696029799579d4d12b66d55e3..e0fd201e1abd9f7f5a1dee18a7305ee03c9827fb 100644 (file)
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -73,12 +73,12 @@ void reset_auto_counter(RTLIL::Module *module)
 
        reset_auto_counter_id(module->name, false);
 
-       for (auto it = module->wires_.begin(); it != module->wires_.end(); ++it)
-               reset_auto_counter_id(it->second->name, true);
+       for (auto w : module->wires())
+               reset_auto_counter_id(w->name, true);
 
-       for (auto it = module->cells_.begin(); it != module->cells_.end(); ++it) {
-               reset_auto_counter_id(it->second->name, true);
-               reset_auto_counter_id(it->second->type, false);
+       for (auto cell : module->cells()) {
+               reset_auto_counter_id(cell->name, true);
+               reset_auto_counter_id(cell->type, false);
        }
 
        for (auto it = module->processes.begin(); it != module->processes.end(); ++it)
@@ -1719,9 +1719,8 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
        if (!noexpr)
        {
                std::set<std::pair<RTLIL::Wire*,int>> reg_bits;
-               for (auto &it : module->cells_)
+               for (auto cell : module->cells())
                {
-                       RTLIL::Cell *cell = it.second;
                        if (!reg_ct.count(cell->type) || !cell->hasPort("\\Q"))
                                continue;
 
@@ -1734,9 +1733,8 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
                                                reg_bits.insert(std::pair<RTLIL::Wire*,int>(chunk.wire, chunk.offset+i));
                        }
                }
-               for (auto &it : module->wires_)
+               for (auto wire : module->wires())
                {
-                       RTLIL::Wire *wire = it.second;
                        for (int i = 0; i < wire->width; i++)
                                if (reg_bits.count(std::pair<RTLIL::Wire*,int>(wire, i)) == 0)
                                        goto this_wire_aint_reg;
@@ -1751,8 +1749,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
        bool keep_running = true;
        for (int port_id = 1; keep_running; port_id++) {
                keep_running = false;
-               for (auto it = module->wires_.begin(); it != module->wires_.end(); ++it) {
-                       RTLIL::Wire *wire = it->second;
+               for (auto wire : module->wires()) {
                        if (wire->port_id == port_id) {
                                if (port_id != 1)
                                        f << stringf(", ");
@@ -1764,14 +1761,14 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
        }
        f << stringf(");\n");
 
-       for (auto it = module->wires_.begin(); it != module->wires_.end(); ++it)
-               dump_wire(f, indent + "  ", it->second);
+       for (auto w : module->wires())
+               dump_wire(f, indent + "  ", w);
 
        for (auto it = module->memories.begin(); it != module->memories.end(); ++it)
                dump_memory(f, indent + "  ", it->second);
 
-       for (auto it = module->cells_.begin(); it != module->cells_.end(); ++it)
-               dump_cell(f, indent + "  ", it->second);
+       for (auto cell : module->cells())
+               dump_cell(f, indent + "  ", cell);
 
        for (auto it = module->processes.begin(); it != module->processes.end(); ++it)
                dump_process(f, indent + "  ", it->second);
@@ -1995,16 +1992,16 @@ struct VerilogBackend : public Backend {
                design->sort();
 
                *f << stringf("/* Generated by %s */\n", yosys_version_str);
-               for (auto it = design->modules_.begin(); it != design->modules_.end(); ++it) {
-                       if (it->second->get_blackbox_attribute() != blackboxes)
+               for (auto module : design->modules()) {
+                       if (module->get_blackbox_attribute() != blackboxes)
                                continue;
-                       if (selected && !design->selected_whole_module(it->first)) {
-                               if (design->selected_module(it->first))
-                                       log_cmd_error("Can't handle partially selected module %s!\n", RTLIL::id2cstr(it->first));
+                       if (selected && !design->selected_whole_module(module->name)) {
+                               if (design->selected_module(module->name))
+                                       log_cmd_error("Can't handle partially selected module %s!\n", log_id(module->name));
                                continue;
                        }
-                       log("Dumping module `%s'.\n", it->first.c_str());
-                       dump_module(*f, "", it->second);
+                       log("Dumping module `%s'.\n", module->name.c_str());
+                       dump_module(*f, "", module);
                }
 
                auto_name_map.clear();