adapt LiteScope to new SoC

diff --git a/misoclib/tools/litescope/example_designs/make.py b/misoclib/tools/litescope/example_designs/make.py
index 4cac064c4213ec71165210b3eb0f12fbba358c91..593ffd77efcbf36607d96cc04c29e00f1b95ba7e 100644 (file)
--- a/misoclib/tools/litescope/example_designs/make.py
+++ b/misoclib/tools/litescope/example_designs/make.py
@@ -72,6 +72,8 @@ if __name__ == "__main__":
        top_kwargs = dict((k, autotype(v)) for k, v in args.target_option)
        soc = top_class(platform, **top_kwargs)
        soc.finalize()
+       memory_regions = soc.get_memory_regions()
+       csr_regions = soc.get_csr_regions()
 
        # decode actions
        action_list = ["clean", "build-csr-csv", "build-bitstream", "load-bitstream", "all"]
@@ -130,7 +132,7 @@ RLE: {}
                subprocess.call(["rm", "-rf", "build/*"])
 
        if actions["build-csr-csv"]:
-               csr_csv = cpuif.get_csr_csv(soc.csr_regions)
+               csr_csv = cpuif.get_csr_csv(csr_regions)
                write_to_file(args.csr_csv, csr_csv)
 
        if actions["build-bitstream"]:

diff --git a/misoclib/tools/litescope/example_designs/targets/simple.py b/misoclib/tools/litescope/example_designs/targets/simple.py
index 224539017e476f0e4d208b80932cc5d912fd3511..fc1db076d368ba3b323239ce71e6a3152c3c3165 100644 (file)
--- a/misoclib/tools/litescope/example_designs/targets/simple.py
+++ b/misoclib/tools/litescope/example_designs/targets/simple.py
@@ -16,14 +16,15 @@ class LiteScopeSoC(SoC, AutoCSR):
        csr_map.update(SoC.csr_map)
        def __init__(self, platform):
                clk_freq = int((1/(platform.default_clk_period))*1000000000)
-               self.submodules.uart2wb = LiteScopeUART2WB(platform.request("serial"), clk_freq, baudrate=115200)
-               SoC.__init__(self, platform, clk_freq, self.uart2wb,
-                       with_cpu=False,
+               SoC.__init__(self, platform, clk_freq,
+                       cpu_type="none",
                        with_csr=True, csr_data_width=32,
                        with_uart=False,
                        with_identifier=True,
                        with_timer=False
                )
+               self.add_cpu_or_bridge(LiteScopeUART2WB(platform.request("serial"), clk_freq, baudrate=115200))
+               self.add_wb_master(self.cpu_or_bridge.wishbone)
                self.submodules.crg = CRG(platform.request(platform.default_clk_name))
 
                self.submodules.io = LiteScopeIO(8)