add fcpsgn parallel reduction test

https://bugs.libre-soc.org/show_bug.cgi?id=864

diff --git a/src/openpower/decoder/isa/test_caller_svp64_parallel_reduce.py b/src/openpower/decoder/isa/test_caller_svp64_parallel_reduce.py
index 7e5aab65ea39ab133f392a7437e53f3d529f2a83..14a6702666c25b40616b6f5fbf0fa24bade1d043 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_parallel_reduce.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_parallel_reduce.py
@@ -20,13 +20,20 @@ from functools import reduce
 import operator
 
 
+def signcopy(x, y):
+    y = abs(y)
+    if x < 0:
+        return -y
+    return y
+
+
 class DecoderTestCase(FHDLTestCase):
 
     def _check_regs(self, sim, expected):
         for i in range(32):
             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
 
-    def tst_sv_remap1(self):
+    def test_sv_remap1(self):
         """>>> lst = ["svshape 7, 0, 0, 7, 0",
                         "svremap 31, 0, 1, 0, 0, 0, 0",
                        "sv.add *0, *8, *16"
@@ -42,10 +49,6 @@ class DecoderTestCase(FHDLTestCase):
         gprs = [0] * 64
         vec = [1, 2, 3, 4, 9, 5, 6]
 
-        # and create a linear result2, same scheme
-        #result1 = [0] * (ydim1*xdim2)
-
-
         res = []
         # store GPRs
         for i, x in enumerate(vec):
@@ -69,7 +72,6 @@ class DecoderTestCase(FHDLTestCase):
             for i, v in enumerate(res):
                 self.assertEqual(v, expected[i])
 
-
     def test_sv_remap2(self):
         """>>> lst = ["svshape 7, 0, 0, 7, 0",
                         "svremap 31, 1, 0, 0, 0, 0, 0", # different order
@@ -87,10 +89,6 @@ class DecoderTestCase(FHDLTestCase):
         gprs = [0] * 64
         vec = [1, 2, 3, 4, 9, 5, 6]
 
-        # and create a linear result2, same scheme
-        #result1 = [0] * (ydim1*xdim2)
-
-
         res = []
         # store GPRs
         for i, x in enumerate(vec):
@@ -115,6 +113,47 @@ class DecoderTestCase(FHDLTestCase):
                 self.assertEqual(v&0xffffffffffffffff,
                                  expected[i]&0xffffffffffffffff)
 
+    def test_sv_remap3(self):
+        """>>> lst = ["svshape 7, 0, 0, 7, 0",
+                        "svremap 31, 0, 1, 0, 0, 0, 0",
+                       "sv.fcpsgn *0, *8, *16"
+                        ]
+                REMAP sv.subf RT,RA,RB - inverted application of RA/RB
+                                         left/right due to subf
+        """
+        lst = SVP64Asm(["svshape 7, 0, 0, 7, 0",
+                        "svremap 31, 0, 1, 0, 0, 0, 0",
+                       "sv.fcpsgn *0, *0, *0"
+                        ])
+        lst = list(lst)
+
+        fprs = [0] * 64
+        vec = [-1.0, 2.0, 3.0, -4.0, 9.0, -5.0, 6.0]
+
+        res = []
+        # store GPRs
+        for i, x in enumerate(vec):
+            fprs[i] = fp64toselectable(x)
+
+        with Program(lst, bigendian=False) as program:
+            sim = self.run_tst_program(program, initial_fprs=fprs)
+            print ("spr svshape0", sim.spr['SVSHAPE0'])
+            print ("    xdimsz", sim.spr['SVSHAPE0'].xdimsz)
+            print ("    ydimsz", sim.spr['SVSHAPE0'].ydimsz)
+            print ("    zdimsz", sim.spr['SVSHAPE0'].zdimsz)
+            print ("spr svshape1", sim.spr['SVSHAPE1'])
+            print ("spr svshape2", sim.spr['SVSHAPE2'])
+            print ("spr svshape3", sim.spr['SVSHAPE3'])
+            # confirm that the results are as expected
+            expected = preduce_y(vec, operation=signcopy)
+            for i in range(7):
+                val = sim.fpr(i).value
+                res.append(val)
+                print ("i", i, float(sim.fpr(i)), vec[i], expected[i])
+            for i, v in enumerate(res):
+                self.assertEqual(v&0xffffffffffffffff,
+                                 fp64toselectable(expected[i]).value)
+
     def run_tst_program(self, prog, initial_regs=None,
                               svstate=None,
                               initial_mem=None,