Fix spelling

diff --git a/README.md b/README.md
index 46bed42426d8f3def0ab4e5079e37aab1aec29cb..7b447705315fe8e6d7016d5d15d8270010481b35 100644 (file)
--- a/README.md
+++ b/README.md
@@ -370,7 +370,7 @@ Verilog Attributes and non-standard features
 
 - When defining a macro with `define, all text between triple double quotes
   is interpreted as macro body, even if it contains unescaped newlines. The
-  tipple double quotes are removed from the macro body. For example:
+  triple double quotes are removed from the macro body. For example:
 
       `define MY_MACRO(a, b) """
          assign a = 23;