* tree-ssa-loop-im.c (execute_sm): Do not force multi-threaded
model if the ref is always written to.
+2017-06-09 Tamar Christina <tamar.christina@arm.com>
+
+ * config/aarch64/aarch64.md (lrint<GPF:mode><GPI:mode>2): New.
+
2017-06-09 Tamar Christina <tamar.christina@arm.com>
* config/arm/arm.c (arm_rtx_costs_internal): Make sdiv more expensive
[(set_attr "type" "f_minmax<stype>")]
)
+(define_expand "lrint<GPF:mode><GPI:mode>2"
+ [(match_operand:GPI 0 "register_operand")
+ (match_operand:GPF 1 "register_operand")]
+ "TARGET_FLOAT"
+{
+ rtx cvt = gen_reg_rtx (<GPF:MODE>mode);
+ emit_insn (gen_rint<GPF:mode>2 (cvt, operands[1]));
+ emit_insn (gen_lbtrunc<GPF:mode><GPI:mode>2 (operands[0], cvt));
+ DONE;
+}
+)
+
;; For copysign (x, y), we want to generate:
;;
;; LDR d2, #(1 << 63)
+2017-06-09 Tamar Christina <tamar.christina@arm.com>
+
+ * gcc.target/aarch64/lrint-matherr.h: New.
+ * gcc.target/aarch64/inline-lrint_1.c: New.
+ * gcc.target/aarch64/inline-lrint_2.c: New.
+ * gcc.target/aarch64/no-inline-lrint_1.c: New.
+ * gcc.target/aarch64/no-inline-lrint_2.c: New.
+
2017-06-09 Tamar Christina <tamar.christina@arm.com>
* gcc.target/arm/sdiv_costs_1.c: New.
--- /dev/null
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O3 -fno-math-errno" } */
+
+#include "lrint-matherr.h"
+
+TEST (dld, double, long, )
+TEST (flf, float , long, )
+
+TEST (did, double, int, )
+TEST (fif, float , int, )
+
+TEST (dlld, double, long long, l)
+TEST (fllf, float , long long, l)
+
+/* { dg-final { scan-assembler-times "frintx\td\[0-9\]+, d\[0-9\]+" 3 } } */
+/* { dg-final { scan-assembler-times "frintx\ts\[0-9\]+, s\[0-9\]+" 3 } } */
+/* { dg-final { scan-assembler-times "fcvtzs\tx\[0-9\]+, d\[0-9\]+" 3 } } */
+/* { dg-final { scan-assembler-times "fcvtzs\tx\[0-9\]+, s\[0-9\]+" 3 } } */
+/* { dg-final { scan-assembler-not "bl" } } */
--- /dev/null
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O3 -fno-math-errno" } */
+
+#include "lrint-matherr.h"
+
+TEST (dld, double, long, )
+TEST (flf, float , long, )
+
+TEST (did, double, int, )
+TEST (fif, float , int, )
+
+TEST (dlld, double, long long, l)
+TEST (fllf, float , long long, l)
+
+/* { dg-final { scan-assembler-times "frintx\td\[0-9\]+, d\[0-9\]+" 3 } } */
+/* { dg-final { scan-assembler-times "frintx\ts\[0-9\]+, s\[0-9\]+" 3 } } */
+/* { dg-final { scan-assembler-times "fcvtzs\tx\[0-9\]+, d\[0-9\]+" 1 } } */
+/* { dg-final { scan-assembler-times "fcvtzs\tx\[0-9\]+, s\[0-9\]+" 1 } } */
+/* { dg-final { scan-assembler-times "fcvtzs\tw\[0-9\]+, d\[0-9\]+" 2 } } */
+/* { dg-final { scan-assembler-times "fcvtzs\tw\[0-9\]+, s\[0-9\]+" 2 } } */
+/* { dg-final { scan-assembler-not "bl" } } */
--- /dev/null
+#define TEST(name, float_type, int_type, pref) void f_##name (float_type x) \
+{ \
+ volatile float_type a = __builtin_rint (x); \
+ volatile int_type b = __builtin_l##pref##rint (x); \
+}
--- /dev/null
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O3" } */
+
+#include "lrint-matherr.h"
+
+TEST (dld, double, long, )
+TEST (flf, float , long, )
+
+TEST (did, double, int, )
+TEST (fif, float , int, )
+
+TEST (dlld, double, long long, l)
+TEST (fllf, float , long long, l)
+
+/* { dg-final { scan-assembler-times "frintx\td\[0-9\]+, d\[0-9\]+" 3 } } */
+/* { dg-final { scan-assembler-times "frintx\ts\[0-9\]+, s\[0-9\]+" 3 } } */
+/* { dg-final { scan-assembler-times "bl\tlrint" 4 } } */
+/* { dg-final { scan-assembler-times "bl\tllrint" 2 } } */
+/* { dg-final { scan-assembler-not "fcvtzs" } } */
--- /dev/null
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O3" } */
+
+#include "lrint-matherr.h"
+
+TEST (dld, double, long, )
+TEST (flf, float , long, )
+
+TEST (did, double, int, )
+TEST (fif, float , int, )
+
+TEST (dlld, double, long long, l)
+TEST (fllf, float , long long, l)
+
+/* { dg-final { scan-assembler-times "frintx\td\[0-9\]+, d\[0-9\]+" 3 } } */
+/* { dg-final { scan-assembler-times "frintx\ts\[0-9\]+, s\[0-9\]+" 3 } } */
+/* { dg-final { scan-assembler-times "bl\tlrint" 4 } } */
+/* { dg-final { scan-assembler-times "bl\tllrint" 2 } } */
+/* { dg-final { scan-assembler-not "fcvtzs" } } */