intel: Replace some gen3 IS_* checks with context structure usage.
authorEric Anholt <eric@anholt.net>
Wed, 16 Dec 2009 23:50:40 +0000 (15:50 -0800)
committerEric Anholt <eric@anholt.net>
Tue, 22 Dec 2009 22:20:27 +0000 (14:20 -0800)
Shaves 400 bytes or so from i915_dri.so.

src/mesa/drivers/dri/i915/i915_vtbl.c
src/mesa/drivers/dri/i915/intel_tris.c
src/mesa/drivers/dri/intel/intel_context.c
src/mesa/drivers/dri/intel/intel_context.h
src/mesa/drivers/dri/intel/intel_extensions.c
src/mesa/drivers/dri/intel/intel_mipmap_tree.c

index ba6be9796e185a65f1a4fe2d1b39abe5eb1c7586..9f7635a9538452f4222faa52e33e4639a1469ef8 100644 (file)
@@ -611,7 +611,7 @@ i915_state_draw_region(struct intel_context *intel,
     * the value of this bit, the pipeline needs to be MI_FLUSHed.  And it
     * can only be set when a depth buffer is already defined.
     */
-   if (IS_945(intel->intelScreen->deviceID) && intel->use_early_z &&
+   if (intel->is_945 && intel->use_early_z &&
        depth_region->tiling != I915_TILING_NONE)
       value |= CLASSIC_EARLY_DEPTH;
 
index 8a3ab39bc286e006875c4987e2221ff9bd24b8a7..63c5ae96dc7a62c7a087c17b62798d79a934ad08 100644 (file)
@@ -221,7 +221,7 @@ void intel_flush_prim(struct intel_context *intel)
    intel->prim.count = 0;
    offset = intel->prim.start_offset;
    intel->prim.start_offset = intel->prim.current_offset;
-   if (!IS_9XX(intel->intelScreen->deviceID))
+   if (!intel->gen >= 3)
       intel->prim.start_offset = ALIGN(intel->prim.start_offset, 128);
    intel->prim.flush = NULL;
 
@@ -251,7 +251,7 @@ void intel_flush_prim(struct intel_context *intel)
          intel->vertex_size * 4);
 #endif
 
-   if (IS_9XX(intel->intelScreen->deviceID)) {
+   if (intel->gen >= 3) {
       BEGIN_BATCH(5, LOOP_CLIPRECTS);
       OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 |
                I1_LOAD_S(0) | I1_LOAD_S(1) | 1);
index 6f567dc4d050b5ed5cf993b2846f19063eecd5ff..02e0cc7b332de1e38e3a2fa4863db308ff625762 100644 (file)
@@ -613,12 +613,16 @@ intelInitContext(struct intel_context *intel,
    intel->sarea = intelScreen->sarea;
    intel->driContext = driContextPriv;
 
-   if (IS_965(intel->intelScreen->deviceID))
+   if (IS_965(intel->intelScreen->deviceID)) {
       intel->gen = 4;
-   else if (IS_9XX(intel->intelScreen->deviceID))
+   } else if (IS_9XX(intel->intelScreen->deviceID)) {
       intel->gen = 3;
-   else
+      if (IS_945(intel->intelScreen->deviceID)) {
+        intel->is_945 = GL_TRUE;
+      }
+   } else {
       intel->gen = 2;
+   }
 
    if (IS_IGDNG(intel->intelScreen->deviceID)) {
       intel->is_ironlake = GL_TRUE;
index e46764e99cf7099d3cb360156d21c2ceb40175f9..e85886db82fb4de7ab92fa240d3f016a447d971e 100644 (file)
@@ -179,6 +179,7 @@ struct intel_context
    GLboolean needs_ff_sync;
    GLboolean is_ironlake;
    GLboolean is_g4x;
+   GLboolean is_945;
    GLboolean has_luminance_srgb;
 
    int urb_size;
index bb50531d98fb3b4b1d77db78ca76612fe1781c12..5ac5ce10afbfd2dfb8b1c90f1b55aa348e33f212 100644 (file)
@@ -199,8 +199,7 @@ intelInitExtensions(GLcontext *ctx)
    if (intel->gen >= 4)
       driInitExtensions(ctx, brw_extensions, GL_FALSE);
 
-   if (IS_915(intel->intelScreen->deviceID)
-       || IS_945(intel->intelScreen->deviceID)) {
+   if (intel->gen == 3) {
       driInitExtensions(ctx, i915_extensions, GL_FALSE);
 
       if (driQueryOptionb(&intel->optionCache, "fragment_shader"))
index 6a565f80cf4308301a1270f8a141a7ac003e94a6..82e4150c6a9dc016082985ee774edabf400fb86f 100644 (file)
@@ -87,7 +87,7 @@ intel_miptree_create_internal(struct intel_context *intel,
    mt->pitch = 0;
 
 #ifdef I915
-   if (IS_945(intel->intelScreen->deviceID))
+   if (intel->is_945)
       ok = i945_miptree_layout(intel, mt, tiling);
    else
       ok = i915_miptree_layout(intel, mt, tiling);