Minor cleanup: Use the blockAlign() method where it applies in the cache.

diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index 24f9933833d118b413762ff2543e00ef30787a14..c245fecd24e6235ab319069b2c106a55dd76c5d2 100644 (file)
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -379,7 +379,7 @@ class BaseCache : public MemObject
     }
 
 
-    Addr blockAlign(Addr addr) const { return (addr & ~(blkSize - 1)); }
+    Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); }
 
 
     const Range<Addr> &getAddrRange() const { return addrRange; }

diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index d8630c1f5d6f71cb82d82e5d45736408f98165e7..429928c7960493704fc48e298c3a458c4b856ad5 100644 (file)
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -449,7 +449,7 @@ Cache<TagStore>::timingAccess(PacketPtr pkt)
     } else {
         // miss
 
-        Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
+        Addr blk_addr = blockAlign(pkt->getAddr());
         MSHR *mshr = mshrQueue.findMatch(blk_addr);
 
         if (mshr) {
@@ -692,7 +692,7 @@ Cache<TagStore>::functionalAccess(PacketPtr pkt,
                                   CachePort *incomingPort,
                                   CachePort *otherSidePort)
 {
-    Addr blk_addr = pkt->getAddr() & ~(blkSize - 1);
+    Addr blk_addr = blockAlign(pkt->getAddr());
     BlkType *blk = tags->findBlock(pkt->getAddr());
 
     pkt->pushLabel(name());
@@ -1162,7 +1162,7 @@ Cache<TagStore>::snoopTiming(PacketPtr pkt)
 
     BlkType *blk = tags->findBlock(pkt->getAddr());
 
-    Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
+    Addr blk_addr = blockAlign(pkt->getAddr());
     MSHR *mshr = mshrQueue.findMatch(blk_addr);
 
     // Let the MSHR itself track the snoop and decide whether we want