* gas/mips/mips4-fp.s: ... to here.
* gas/mips/mips4.d: Update.
* gas/mips/mips4-fp.l: New file. Check error messages with
-msoft-float.
* gas/mips/mips4-fp.d: New file. Check disassembly with
hard-float.
* gas/mips/mips32r2.s: Split out fp instructions from here ...
* gas/mips/mips32r2-fp32.s: ... to here.
* gas/mips/mips32r2.d: Update.
* gas/mips/mips32r2-fp32.l: New file. Check error messages with
-msoft-float.
* gas/mips/mips32r2-fp32.d: New file. Check disassembly with
hard-float.
* gas/mips/mips32r2-ill-nofp.s, gas/mips/mips32r2-ill-nofp.l: New
test derived from mips32r2-ill.
* gas/mips/mips32-sf32.l: New list test for mips32-sf32.s to check
error messages for soft-float targets.
* gas/mips/mips-macro-ill-sfp.s, gas/mips/mips-macro-ill-sfp.l:
New test for -msingle-float.
* gas/mips/mips-macro-ill-nofp.s, gas/mips/mips-macro-ill-nofp.l:
New test for -msoft-float.
* gas/mips/mips-hard-float-flag.s,
gas/mips/mips-hard-float-flag.l: New test for -mhard-float.
* gas/mips/mips-double-float-flag.s,
gas/mips/mips-double-float-flag.l: New test for -mdouble-float.
* gas/mips/mips.exp: Run new mips4-fp and mips32r2-fp dump tests.
Run mips4-fp and mips32r2-fp list tests with -msoft-float. Run
new mips32r2-ill-nofp with -msoft-float. Run new mips32-sf32 list
test with -msoft-float. Run new mips-macro-ill-sfp test with
-msingle-float. Run new mips-macro-ill-nofp test with
-msoft-float. Run new mips-hard-float-flag and
mips-double-float-flag tests.
+2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
+
+ * gas/mips/mips4.s: Split out fp instruction from here ...
+ * gas/mips/mips4-fp.s: ... to here.
+ * gas/mips/mips4.d: Update.
+ * gas/mips/mips4-fp.l: New file. Check error messages with
+ -msoft-float.
+ * gas/mips/mips4-fp.d: New file. Check disassembly with
+ hard-float.
+
+ * gas/mips/mips32r2.s: Split out fp instructions from here ...
+ * gas/mips/mips32r2-fp32.s: ... to here.
+ * gas/mips/mips32r2.d: Update.
+ * gas/mips/mips32r2-fp32.l: New file. Check error messages with
+ -msoft-float.
+ * gas/mips/mips32r2-fp32.d: New file. Check disassembly with
+ hard-float.
+
+ * gas/mips/mips32r2-ill-nofp.s, gas/mips/mips32r2-ill-nofp.l: New
+ test derived from mips32r2-ill.
+
+ * gas/mips/mips32-sf32.l: New list test for mips32-sf32.s to check
+ error messages for soft-float targets.
+
+ * gas/mips/mips-macro-ill-sfp.s, gas/mips/mips-macro-ill-sfp.l:
+ New test for -msingle-float.
+ * gas/mips/mips-macro-ill-nofp.s, gas/mips/mips-macro-ill-nofp.l:
+ New test for -msoft-float.
+ * gas/mips/mips-hard-float-flag.s,
+ gas/mips/mips-hard-float-flag.l: New test for -mhard-float.
+ * gas/mips/mips-double-float-flag.s,
+ gas/mips/mips-double-float-flag.l: New test for -mdouble-float.
+
+ * gas/mips/mips.exp: Run new mips4-fp and mips32r2-fp dump tests.
+ Run mips4-fp and mips32r2-fp list tests with -msoft-float. Run
+ new mips32r2-ill-nofp with -msoft-float. Run new mips32-sf32 list
+ test with -msoft-float. Run new mips-macro-ill-sfp test with
+ -msingle-float. Run new mips-macro-ill-nofp test with
+ -msoft-float. Run new mips-hard-float-flag and
+ mips-double-float-flag tests.
+
2008-04-23 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run sse-noavx and x86-64-sse-noavx.
--- /dev/null
+.*: Assembler messages:
+.*:8: Error: opcode not supported on this processor: .* \(.*\) `add.d \$f2,\$f2,\$f2'
+.*:17: Error: opcode not supported on this processor: .* \(.*\) `add.d \$f2,\$f2,\$f2'
--- /dev/null
+ .text
+foo:
+ add.s $f2,$f2,$f2
+ add.d $f2,$f2,$f2
+
+ .set singlefloat
+ add.s $f2,$f2,$f2
+ add.d $f2,$f2,$f2
+ .set push
+
+ .set doublefloat
+ add.s $f2,$f2,$f2
+ add.d $f2,$f2,$f2
+
+ .set pop
+ add.s $f2,$f2,$f2
+ add.d $f2,$f2,$f2
--- /dev/null
+.*: Assembler messages:
+.*:7: Error: opcode not supported on this processor: .* \(.*\) `add.s \$f2,\$f2,\$f2'
+.*:8: Error: opcode not supported on this processor: .* \(.*\) `add.d \$f2,\$f2,\$f2'
+.*:16: Error: opcode not supported on this processor: .* \(.*\) `add.s \$f2,\$f2,\$f2'
+.*:17: Error: opcode not supported on this processor: .* \(.*\) `add.d \$f2,\$f2,\$f2'
--- /dev/null
+ .text
+foo:
+ add.s $f2,$f2,$f2
+ add.d $f2,$f2,$f2
+
+ .set softfloat
+ add.s $f2,$f2,$f2
+ add.d $f2,$f2,$f2
+ .set push
+
+ .set hardfloat
+ add.s $f2,$f2,$f2
+ add.d $f2,$f2,$f2
+
+ .set pop
+ add.s $f2,$f2,$f2
+ add.d $f2,$f2,$f2
--- /dev/null
+.*: Assembler messages:
+.*:5: Error: opcode not supported on this processor: .* \(.*\) `ldc1 \$f2,d'
+.*:6: Error: opcode not supported on this processor: .* \(.*\) `ldc1 \$22,d'
+.*:7: Error: opcode not supported on this processor: .* \(.*\) `l.d \$f2,d'
+.*:8: Error: opcode not supported on this processor: .* \(.*\) `li.d \$f2,1.2'
+.*:9: Error: opcode not supported on this processor: .* \(.*\) `li.d \$22,1.2'
+.*:11: Error: opcode not supported on this processor: .* \(.*\) `sdc1 \$f2,d'
+.*:12: Error: opcode not supported on this processor: .* \(.*\) `sdc1 \$22,d'
+.*:13: Error: opcode not supported on this processor: .* \(.*\) `s.d \$f2,d'
+.*:15: Error: opcode not supported on this processor: .* \(.*\) `trunc.w.d \$f4,\$f6,\$4'
+.*:18: Error: opcode not supported on this processor: .* \(.*\) `lwc1 \$f2,d'
+.*:19: Error: opcode not supported on this processor: .* \(.*\) `lwc1 \$22,d'
+.*:20: Error: opcode not supported on this processor: .* \(.*\) `l.s \$f2,d'
+.*:21: Error: opcode not supported on this processor: .* \(.*\) `li.s \$f2,1.2'
+.*:22: Error: opcode not supported on this processor: .* \(.*\) `li.s \$22,1.2'
+.*:24: Error: opcode not supported on this processor: .* \(.*\) `sdc1 \$f2,d'
+.*:25: Error: opcode not supported on this processor: .* \(.*\) `sdc1 \$22,d'
+.*:26: Error: opcode not supported on this processor: .* \(.*\) `s.d \$f2,d'
+.*:28: Error: opcode not supported on this processor: .* \(.*\) `trunc.w.s \$f4,\$f6,\$4'
--- /dev/null
+# Macros that are disabled without floating point.
+
+ .text
+double_float:
+ ldc1 $f2, d
+ ldc1 $22, d
+ l.d $f2, d
+ li.d $f2, 1.2
+ li.d $22, 1.2
+
+ sdc1 $f2, d
+ sdc1 $22, d
+ s.d $f2, d
+
+ trunc.w.d $f4,$f6,$4
+
+single_float:
+ lwc1 $f2, d
+ lwc1 $22, d
+ l.s $f2, d
+ li.s $f2, 1.2
+ li.s $22, 1.2
+
+ sdc1 $f2, d
+ sdc1 $22, d
+ s.d $f2, d
+
+ trunc.w.s $f4,$f6,$4
+
+d:
+ .word 0
+ .word 0
--- /dev/null
+.*: Assembler messages:
+.*:5: Error: opcode not supported on this processor: .* \(.*\) `ldc1 \$f2,d'
+.*:6: Error: opcode not supported on this processor: .* \(.*\) `ldc1 \$22,d'
+.*:7: Error: opcode not supported on this processor: .* \(.*\) `l.d \$f2,d'
+.*:8: Error: opcode not supported on this processor: .* \(.*\) `li.d \$f2,1.2'
+.*:9: Error: opcode not supported on this processor: .* \(.*\) `li.d \$22,1.2'
+.*:11: Error: opcode not supported on this processor: .* \(.*\) `sdc1 \$f2,d'
+.*:12: Error: opcode not supported on this processor: .* \(.*\) `sdc1 \$22,d'
+.*:13: Error: opcode not supported on this processor: .* \(.*\) `s.d \$f2,d'
+.*:15: Error: opcode not supported on this processor: .* \(.*\) `trunc.w.d \$f4,\$f6,\$4'
--- /dev/null
+# Macros that are disabled without double-precision fp insns.
+
+ .text
+double_float:
+ ldc1 $f2, d
+ ldc1 $22, d
+ l.d $f2, d
+ li.d $f2, 1.2
+ li.d $22, 1.2
+
+ sdc1 $f2, d
+ sdc1 $22, d
+ s.d $f2, d
+
+ trunc.w.d $f4,$f6,$4
+
+d:
+ .word 0
+ .word 0
if $elf { run_dump_test "lif-svr4pic" }
if $elf { run_dump_test "lif-xgot" }
run_dump_test_arches "mips4" [mips_arch_list_matching mips4]
+ run_dump_test_arches "mips4-fp" [mips_arch_list_matching mips4]
+ run_list_test_arches "mips4-fp" "-32 -msoft-float" \
+ [mips_arch_list_matching mips4]
run_dump_test_arches "mips5" [mips_arch_list_matching mips5]
if $ilocks {
run_dump_test "mul-ilocks"
run_dump_test_arches "mips32" [mips_arch_list_matching mips32]
run_dump_test_arches "mips32-sf32" [mips_arch_list_matching mips32]
+ run_list_test_arches "mips32-sf32" "-32 -msoft-float" \
+ [mips_arch_list_matching mips32]
run_dump_test_arches "mips32r2" [mips_arch_list_matching mips32r2]
+ run_dump_test_arches "mips32r2-fp32" \
+ [mips_arch_list_matching mips32r2]
+ run_list_test_arches "mips32r2-fp32" "-32 -msoft-float" \
+ [mips_arch_list_matching mips32r2]
run_list_test_arches "mips32r2-ill" "-32" \
- [mips_arch_list_matching mips32r2 gpr32]
+ [mips_arch_list_matching mips32r2 gpr32]
run_list_test_arches "mips32r2-ill-fp64" "-mabi=o64" \
- [mips_arch_list_matching mips32r2 gpr64]
+ [mips_arch_list_matching mips32r2 gpr64]
+ run_list_test_arches "mips32r2-ill-nofp" "-32 -msoft-float" \
+ [mips_arch_list_matching mips32r2]
run_dump_test_arches "mips64" [mips_arch_list_matching mips64]
run_dump_test "align2"
run_dump_test "align2-el"
run_dump_test "odd-float"
+
+ run_list_test_arches "mips-macro-ill-sfp" "-32 -msingle-float" \
+ [mips_arch_list_matching mips2]
+ run_list_test_arches "mips-macro-ill-nofp" "-32 -msoft-float" \
+ [mips_arch_list_matching mips2]
+
+ run_list_test_arches "mips-hard-float-flag" \
+ "-32 -msoft-float -mhard-float" \
+ [mips_arch_list_matching mips1]
+ run_list_test_arches "mips-double-float-flag" \
+ "-32 -msingle-float -mdouble-float" \
+ [mips_arch_list_matching mips1]
}
--- /dev/null
+.*: Assembler messages:
+.*:5: Error: opcode not supported on this processor: .* \(.*\) `li.s \$f1,1.0'
+.*:6: Error: opcode not supported on this processor: .* \(.*\) `li.s \$f3,1.9'
+.*:7: Error: opcode not supported on this processor: .* \(.*\) `add.s \$f5,\$f1,\$f3'
+.*:8: Error: opcode not supported on this processor: .* \(.*\) `cvt.d.s \$f8,\$f7'
+.*:9: Error: opcode not supported on this processor: .* \(.*\) `cvt.d.w \$f8,\$f7'
+.*:10: Error: opcode not supported on this processor: .* \(.*\) `cvt.s.d \$f7,\$f8'
+.*:11: Error: opcode not supported on this processor: .* \(.*\) `trunc.w.d \$f7,\$f8'
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
+#name: MIPS MIPS32r2 fp instructions
+#as: -32
+
+# Check MIPS32 Release 2 (mips32r2) FP instruction assembly
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 44710000 mfhc1 \$17,\$f0
+0+0004 <[^>]*> 44f10000 mthc1 \$17,\$f0
+#pass
--- /dev/null
+.*: Assembler messages:
+.*:12: Error: opcode not supported on this processor: .* \(.*\) `mfhc1 \$17,\$f0'
+.*:13: Error: opcode not supported on this processor: .* \(.*\) `mthc1 \$17,\$f0'
--- /dev/null
+# source file to test assembly of mips32r2 FP instructions
+
+ .text
+text_label:
+
+ # FPU (cp1) instructions
+ #
+ # Even registers are supported w/ 32-bit FPU, odd
+ # registers supported only for 64-bit FPU.
+ # Only the 32-bit FPU instructions are tested here.
+
+ mfhc1 $17, $f0
+ mthc1 $17, $f0
--- /dev/null
+.*: Assembler messages:
+.*:12: Error: Improper position \([0-9]*\)
+.*:15: Error: Improper position \(32\)
+.*:18: Error: Improper extract size \(0, position 0\)
+.*:21: Error: Improper extract size \(33, position 0\)
+.*:24: Error: Improper extract size \(0, position 0\)
+.*:27: Error: Improper extract size \(2, position 31\)
+.*:30: Error: Improper position \([0-9]*\)
+.*:33: Error: Improper position \(32\)
+.*:36: Error: Improper insert size \(0, position 0\)
+.*:39: Error: Improper insert size \(33, position 0\)
+.*:42: Error: Improper insert size \(0, position 0\)
+.*:45: Error: Improper insert size \(2, position 31\)
--- /dev/null
+# source file to test illegal mips32r2 instructions
+
+ .set noreorder
+ .set noat
+
+ .text
+text_label:
+
+ # insert and extract position/size checks:
+
+ # ext constraint: 0 <= pos < 32
+ ext $4, $5, -1, 1 # error
+ ext $4, $5, 0, 1
+ ext $4, $5, 31, 1
+ ext $4, $5, 32, 1 # error
+
+ # ext constraint: 0 < size <= 32
+ ext $4, $5, 0, 0 # error
+ ext $4, $5, 0, 1
+ ext $4, $5, 0, 32
+ ext $4, $5, 0, 33 # error
+
+ # ext constraint: 0 < (pos+size) <= 32
+ ext $4, $5, 0, 0 # error
+ ext $4, $5, 0, 1
+ ext $4, $5, 31, 1
+ ext $4, $5, 31, 2 # error
+
+ # ins constraint: 0 <= pos < 32
+ ins $4, $5, -1, 1 # error
+ ins $4, $5, 0, 1
+ ins $4, $5, 31, 1
+ ins $4, $5, 32, 1 # error
+
+ # ins constraint: 0 < size <= 32
+ ins $4, $5, 0, 0 # error
+ ins $4, $5, 0, 1
+ ins $4, $5, 0, 32
+ ins $4, $5, 0, 33 # error
+
+ # ins constraint: 0 < (pos+size) <= 32
+ ins $4, $5, 0, 0 # error
+ ins $4, $5, 0, 1
+ ins $4, $5, 31, 1
+ ins $4, $5, 31, 2 # error
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .space 8
#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
-#name: MIPS MIPS32r2 instructions
+#name: MIPS MIPS32r2 non-fp instructions
#as: -32
-# Check MIPS32 Release 2 (mips32r2) instruction assembly
+# Check MIPS32 Release 2 (mips32r2) *non-fp* instruction assembly
.*: +file format .*mips.*
0+0078 <[^>]*> 416a6020 ei \$10
0+007c <[^>]*> 41595000 rdpgpr \$10,\$25
0+0080 <[^>]*> 41d95000 wrpgpr \$10,\$25
-0+0084 <[^>]*> 44710000 mfhc1 \$17,\$f0
-0+0088 <[^>]*> 44f10000 mthc1 \$17,\$f0
-0+008c <[^>]*> 48715555 mfhc2 \$17,0x5555
-0+0090 <[^>]*> 48f15555 mthc2 \$17,0x5555
+0+0084 <[^>]*> 48715555 mfhc2 \$17,0x5555
+0+0088 <[^>]*> 48f15555 mthc2 \$17,0x5555
...
-# source file to test assembly of mips32r2 instructions
+# source file to test assembly of mips32r2 *non-fp* instructions
.set noreorder
.set noat
wrpgpr $10, $25
- # FPU (cp1) instructions
- #
- # Even registers are supported w/ 32-bit FPU, odd
- # registers supported only for 64-bit FPU.
- # Only the 32-bit FPU instructions are tested here.
-
- mfhc1 $17, $f0
- mthc1 $17, $f0
-
# cp2 instructions
mfhc2 $17, 0x5555
--- /dev/null
+#objdump: -dr --prefix-addresses
+#name: MIPS mips4 fp
+
+# Test mips4 fp instructions.
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> bc1f 00000000+ <text_label>
+0+0004 <[^>]*> nop
+0+0008 <[^>]*> bc1f \$fcc1,00000000+ <text_label>
+0+000c <[^>]*> nop
+0+0010 <[^>]*> bc1fl \$fcc1,00000000+ <text_label>
+0+0014 <[^>]*> nop
+0+0018 <[^>]*> bc1t \$fcc1,00000000+ <text_label>
+0+001c <[^>]*> nop
+0+0020 <[^>]*> bc1tl \$fcc2,00000000+ <text_label>
+0+0024 <[^>]*> nop
+0+0028 <[^>]*> c.f.d \$f4,\$f6
+0+002c <[^>]*> c.f.d \$fcc1,\$f4,\$f6
+0+0030 <[^>]*> ldxc1 \$f2,a0\(a1\)
+0+0034 <[^>]*> lwxc1 \$f2,a0\(a1\)
+0+0038 <[^>]*> madd.d \$f0,\$f2,\$f4,\$f6
+0+003c <[^>]*> madd.s \$f10,\$f8,\$f2,\$f0
+0+0040 <[^>]*> movf a0,a1,\$fcc4
+0+0044 <[^>]*> movf.d \$f4,\$f6,\$fcc0
+0+0048 <[^>]*> movf.s \$f4,\$f6,\$fcc0
+0+004c <[^>]*> movn.d \$f4,\$f6,a2
+0+0050 <[^>]*> movn.s \$f4,\$f6,a2
+0+0054 <[^>]*> movt a0,a1,\$fcc4
+0+0058 <[^>]*> movt.d \$f4,\$f6,\$fcc0
+0+005c <[^>]*> movt.s \$f4,\$f6,\$fcc0
+0+0060 <[^>]*> movz.d \$f4,\$f6,a2
+0+0064 <[^>]*> movz.s \$f4,\$f6,a2
+0+0068 <[^>]*> msub.d \$f0,\$f2,\$f4,\$f6
+0+006c <[^>]*> msub.s \$f0,\$f2,\$f4,\$f6
+0+0070 <[^>]*> nmadd.d \$f0,\$f2,\$f4,\$f6
+0+0074 <[^>]*> nmadd.s \$f0,\$f2,\$f4,\$f6
+0+0078 <[^>]*> nmsub.d \$f0,\$f2,\$f4,\$f6
+0+007c <[^>]*> nmsub.s \$f0,\$f2,\$f4,\$f6
+0+0080 <[^>]*> prefx 0x4,a0\(a1\)
+0+0084 <[^>]*> recip.d \$f4,\$f6
+0+0088 <[^>]*> recip.s \$f4,\$f6
+0+008c <[^>]*> rsqrt.d \$f4,\$f6
+0+0090 <[^>]*> rsqrt.s \$f4,\$f6
+0+0094 <[^>]*> sdxc1 \$f4,a0\(a1\)
+0+0098 <[^>]*> swxc1 \$f4,a0\(a1\)
+ ...
--- /dev/null
+.*: Assembler messages:
+.*:4: Error: opcode not supported on this processor: .* \(.*\) `bc1f text_label'
+.*:5: Error: opcode not supported on this processor: .* \(.*\) `bc1f \$fcc1,text_label'
+.*:6: Error: opcode not supported on this processor: .* \(.*\) `bc1fl \$fcc1,text_label'
+.*:7: Error: opcode not supported on this processor: .* \(.*\) `bc1t \$fcc1,text_label'
+.*:8: Error: opcode not supported on this processor: .* \(.*\) `bc1tl \$fcc2,text_label'
+.*:9: Error: opcode not supported on this processor: .* \(.*\) `c.f.d \$f4,\$f6'
+.*:10: Error: opcode not supported on this processor: .* \(.*\) `c.f.d \$fcc1,\$f4,\$f6'
+.*:11: Error: opcode not supported on this processor: .* \(.*\) `ldxc1 \$f2,\$4\(\$5\)'
+.*:12: Error: opcode not supported on this processor: .* \(.*\) `lwxc1 \$f2,\$4\(\$5\)'
+.*:13: Error: opcode not supported on this processor: .* \(.*\) `madd.d \$f0,\$f2,\$f4,\$f6'
+.*:15: Error: opcode not supported on this processor: .* \(.*\) `madd.s \$f10,\$f8,\$f2,\$f0'
+.*:16: Error: opcode not supported on this processor: .* \(.*\) `movf \$4,\$5,\$fcc4'
+.*:17: Error: opcode not supported on this processor: .* \(.*\) `movf.d \$f4,\$f6,\$fcc0'
+.*:18: Error: opcode not supported on this processor: .* \(.*\) `movf.s \$f4,\$f6,\$fcc0'
+.*:19: Error: opcode not supported on this processor: .* \(.*\) `movn.d \$f4,\$f6,\$6'
+.*:20: Error: opcode not supported on this processor: .* \(.*\) `movn.s \$f4,\$f6,\$6'
+.*:21: Error: opcode not supported on this processor: .* \(.*\) `movt \$4,\$5,\$fcc4'
+.*:22: Error: opcode not supported on this processor: .* \(.*\) `movt.d \$f4,\$f6,\$fcc0'
+.*:23: Error: opcode not supported on this processor: .* \(.*\) `movt.s \$f4,\$f6,\$fcc0'
+.*:24: Error: opcode not supported on this processor: .* \(.*\) `movz.d \$f4,\$f6,\$6'
+.*:25: Error: opcode not supported on this processor: .* \(.*\) `movz.s \$f4,\$f6,\$6'
+.*:26: Error: opcode not supported on this processor: .* \(.*\) `msub.d \$f0,\$f2,\$f4,\$f6'
+.*:27: Error: opcode not supported on this processor: .* \(.*\) `msub.s \$f0,\$f2,\$f4,\$f6'
+.*:28: Error: opcode not supported on this processor: .* \(.*\) `nmadd.d \$f0,\$f2,\$f4,\$f6'
+.*:29: Error: opcode not supported on this processor: .* \(.*\) `nmadd.s \$f0,\$f2,\$f4,\$f6'
+.*:30: Error: opcode not supported on this processor: .* \(.*\) `nmsub.d \$f0,\$f2,\$f4,\$f6'
+.*:31: Error: opcode not supported on this processor: .* \(.*\) `nmsub.s \$f0,\$f2,\$f4,\$f6'
+.*:33: Error: opcode not supported on this processor: .* \(.*\) `prefx 4,\$4\(\$5\)'
+.*:34: Error: opcode not supported on this processor: .* \(.*\) `recip.d \$f4,\$f6'
+.*:35: Error: opcode not supported on this processor: .* \(.*\) `recip.s \$f4,\$f6'
+.*:36: Error: opcode not supported on this processor: .* \(.*\) `rsqrt.d \$f4,\$f6'
+.*:37: Error: opcode not supported on this processor: .* \(.*\) `rsqrt.s \$f4,\$f6'
+.*:38: Error: opcode not supported on this processor: .* \(.*\) `sdxc1 \$f4,\$4\(\$5\)'
+.*:39: Error: opcode not supported on this processor: .* \(.*\) `swxc1 \$f4,\$4\(\$5\)'
--- /dev/null
+# Source file used to test -mips4 fp instructions.
+
+text_label:
+ bc1f text_label
+ bc1f $fcc1,text_label
+ bc1fl $fcc1,text_label
+ bc1t $fcc1,text_label
+ bc1tl $fcc2,text_label
+ c.f.d $f4,$f6
+ c.f.d $fcc1,$f4,$f6
+ ldxc1 $f2,$4($5)
+ lwxc1 $f2,$4($5)
+ madd.d $f0,$f2,$f4,$f6
+ # This choice of arguments is so that it matches bc3f on pre-mips4.
+ madd.s $f10,$f8,$f2,$f0
+ movf $4,$5,$fcc4
+ movf.d $f4,$f6,$fcc0
+ movf.s $f4,$f6,$fcc0
+ movn.d $f4,$f6,$6
+ movn.s $f4,$f6,$6
+ movt $4,$5,$fcc4
+ movt.d $f4,$f6,$fcc0
+ movt.s $f4,$f6,$fcc0
+ movz.d $f4,$f6,$6
+ movz.s $f4,$f6,$6
+ msub.d $f0,$f2,$f4,$f6
+ msub.s $f0,$f2,$f4,$f6
+ nmadd.d $f0,$f2,$f4,$f6
+ nmadd.s $f0,$f2,$f4,$f6
+ nmsub.d $f0,$f2,$f4,$f6
+ nmsub.s $f0,$f2,$f4,$f6
+ # It used to be disabled due to a clash with lwc3.
+ prefx 4,$4($5)
+ recip.d $f4,$f6
+ recip.s $f4,$f6
+ rsqrt.d $f4,$f6
+ rsqrt.s $f4,$f6
+ sdxc1 $f4,$4($5)
+ swxc1 $f4,$4($5)
+
+# Round to a 16 byte boundary, for ease in testing multiple targets.
+ nop
+ nop
+ nop
#objdump: -dr --prefix-addresses
-#name: MIPS mips4
+#name: MIPS mips4 non-fp
-# Test the mips4 macros.
+# Test mips4 *non-fp* insturctions.
.*: +file format .*mips.*
Disassembly of section .text:
-0+0000 <[^>]*> bc1f 00000000+ <text_label>
-0+0004 <[^>]*> nop
-0+0008 <[^>]*> bc1f \$fcc1,00000000+ <text_label>
-0+000c <[^>]*> nop
-0+0010 <[^>]*> bc1fl \$fcc1,00000000+ <text_label>
-0+0014 <[^>]*> nop
-0+0018 <[^>]*> bc1t \$fcc1,00000000+ <text_label>
-0+001c <[^>]*> nop
-0+0020 <[^>]*> bc1tl \$fcc2,00000000+ <text_label>
-0+0024 <[^>]*> nop
-0+0028 <[^>]*> c.f.d \$f4,\$f6
-0+002c <[^>]*> c.f.d \$fcc1,\$f4,\$f6
-0+0030 <[^>]*> ldxc1 \$f2,a0\(a1\)
-0+0034 <[^>]*> lwxc1 \$f2,a0\(a1\)
-0+0038 <[^>]*> madd.d \$f0,\$f2,\$f4,\$f6
-0+003c <[^>]*> madd.s \$f10,\$f8,\$f2,\$f0
-0+0040 <[^>]*> movf a0,a1,\$fcc4
-0+0044 <[^>]*> movf.d \$f4,\$f6,\$fcc0
-0+0048 <[^>]*> movf.s \$f4,\$f6,\$fcc0
-0+004c <[^>]*> movn a0,a2,a2
-0+0050 <[^>]*> movn.d \$f4,\$f6,a2
-0+0054 <[^>]*> movn.s \$f4,\$f6,a2
-0+0058 <[^>]*> movt a0,a1,\$fcc4
-0+005c <[^>]*> movt.d \$f4,\$f6,\$fcc0
-0+0060 <[^>]*> movt.s \$f4,\$f6,\$fcc0
-0+0064 <[^>]*> movz a0,a2,a2
-0+0068 <[^>]*> movz.d \$f4,\$f6,a2
-0+006c <[^>]*> movz.s \$f4,\$f6,a2
-0+0070 <[^>]*> msub.d \$f0,\$f2,\$f4,\$f6
-0+0074 <[^>]*> msub.s \$f0,\$f2,\$f4,\$f6
-0+0078 <[^>]*> nmadd.d \$f0,\$f2,\$f4,\$f6
-0+007c <[^>]*> nmadd.s \$f0,\$f2,\$f4,\$f6
-0+0080 <[^>]*> nmsub.d \$f0,\$f2,\$f4,\$f6
-0+0084 <[^>]*> nmsub.s \$f0,\$f2,\$f4,\$f6
-0+0088 <[^>]*> pref 0x4,0\(a0\)
-0+008c <[^>]*> prefx 0x4,a0\(a1\)
-0+0090 <[^>]*> recip.d \$f4,\$f6
-0+0094 <[^>]*> recip.s \$f4,\$f6
-0+0098 <[^>]*> rsqrt.d \$f4,\$f6
-0+009c <[^>]*> rsqrt.s \$f4,\$f6
-0+00a0 <[^>]*> sdxc1 \$f4,a0\(a1\)
-0+00a4 <[^>]*> swxc1 \$f4,a0\(a1\)
+0+0000 <[^>]*> movn a0,a2,a2
+0+0004 <[^>]*> movz a0,a2,a2
+0+0008 <[^>]*> pref 0x4,0\(a0\)
...
-# Source file used to test -mips4 instructions.
+# Source file used to test -mips4 *non-fp* instructions.
text_label:
- bc1f text_label
- bc1f $fcc1,text_label
- bc1fl $fcc1,text_label
- bc1t $fcc1,text_label
- bc1tl $fcc2,text_label
- c.f.d $f4,$f6
- c.f.d $fcc1,$f4,$f6
- ldxc1 $f2,$4($5)
- lwxc1 $f2,$4($5)
- madd.d $f0,$f2,$f4,$f6
- # This choice of arguments is so that it matches bc3f on pre-mips4.
- madd.s $f10,$f8,$f2,$f0
- movf $4,$5,$fcc4
- movf.d $f4,$f6,$fcc0
- movf.s $f4,$f6,$fcc0
movn $4,$6,$6
- movn.d $f4,$f6,$6
- movn.s $f4,$f6,$6
- movt $4,$5,$fcc4
- movt.d $f4,$f6,$fcc0
- movt.s $f4,$f6,$fcc0
movz $4,$6,$6
- movz.d $f4,$f6,$6
- movz.s $f4,$f6,$6
- msub.d $f0,$f2,$f4,$f6
- msub.s $f0,$f2,$f4,$f6
- nmadd.d $f0,$f2,$f4,$f6
- nmadd.s $f0,$f2,$f4,$f6
- nmsub.d $f0,$f2,$f4,$f6
- nmsub.s $f0,$f2,$f4,$f6
# It used to be disabled due to a clash with lwc3.
pref 4,0($4)
- prefx 4,$4($5)
- recip.d $f4,$f6
- recip.s $f4,$f6
- rsqrt.d $f4,$f6
- rsqrt.s $f4,$f6
- sdxc1 $f4,$4($5)
- swxc1 $f4,$4($5)
# Round to a 16 byte boundary, for ease in testing multiple targets.
nop
projects / binutils-gdb.git / commitdiff