import binascii
+
def insert_crc(i_filename, fbi_mode=False, o_filename=None):
if o_filename is None:
o_filename = i_filename
from misoc_import import misoc_import
+
def _get_args():
parser = argparse.ArgumentParser(formatter_class=argparse.RawDescriptionHelpFormatter,
description="""\
import sys, importlib
+
def misoc_import(default, external, name):
if external:
try:
from migen.genlib.cdc import MultiReg
from migen.bank.description import *
+
class GPIOIn(Module, AutoCSR):
def __init__(self, signal):
self._in = CSRStatus(flen(signal))
self.specials += MultiReg(signal, self._in.status)
+
class GPIOOut(Module, AutoCSR):
def __init__(self, signal):
self._out = CSRStorage(flen(signal))
self.comb += signal.eq(self._out.storage)
+
class GPIOInOut(Module):
def __init__(self, in_signal, out_signal):
self.submodules.gpio_in = GPIOIn(in_signal)
def get_csrs(self):
return self.gpio_in.get_csrs() + self.gpio_out.get_csrs()
+
class Blinker(Module):
def __init__(self, signal, divbits=26):
counter = Signal(divbits)
from migen.bank.description import *
from migen.genlib.fsm import FSM, NextState
+
class SPIMaster(Module, AutoCSR):
def __init__(self, pads, width=24, div=2, cpha=1):
self.pads = pads
from misoclib.com.spi import SPIMaster
+
class SPISlave(Module):
def __init__(self, pads, width):
self.pads = pads
while not (selfp.spi_master._status.status & 0x1):
yield
+
class TB(Module):
def __init__(self):
pads = Record([("cs_n", 1), ("clk", 1), ("mosi", 1), ("miso", 1)])
from migen.genlib.record import Record
from migen.flow.actor import Sink, Source
+
class UART(Module, AutoCSR):
def __init__(self, phy):
self._rxtx = CSR(8)
from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.generic import *
+
def UARTPHY(pads, *args, **kwargs):
# Autodetect PHY
if hasattr(pads, "source_stb"):
from migen.bank.description import *
from migen.flow.actor import Sink, Source
+
class UARTPHYSerialRX(Module):
def __init__(self, pads, tuning_word):
self.source = Source([("data", 8)])
Cat(phase_accumulator_rx, uart_clk_rxen).eq(2**31)
)
+
class UARTPHYSerialTX(Module):
def __init__(self, pads, tuning_word):
self.sink = Sink([("data", 8)])
)
]
+
class UARTPHYSerial(Module, AutoCSR):
def __init__(self, pads, clk_freq, baudrate=115200):
self._tuning_word = CSRStorage(32, reset=int((baudrate/clk_freq)*2**32))
from migen.fhdl.std import *
from migen.flow.actor import Sink, Source
+
class UARTPHYSim(Module):
def __init__(self, pads, *args, **kwargs):
self.sink = Sink([("data", 8)])
from migen.fhdl.std import *
from migen.bus import wishbone
+
class LM32(Module):
def __init__(self, platform, eba_reset):
self.ibus = i = wishbone.Interface()
from migen.fhdl.std import *
from migen.bus import wishbone
+
class MOR1KX(Module):
def __init__(self, platform, reset_pc):
self.ibus = i = wishbone.Interface()
from misoclib.cpu.peripherals.identifier import git
+
class Identifier(Module, AutoCSR):
def __init__(self, sysid, frequency, revision=None):
self._sysid = CSRStatus(16)
import subprocess
+
def get_id():
output = subprocess.check_output(["git", "rev-parse", "HEAD"]).decode("ascii")
return int(output[:8], 16)
from migen.bank.description import *
from migen.bank.eventmanager import *
+
class Timer(Module, AutoCSR):
def __init__(self, width=32):
self._load = CSRStorage(width)
from migen.bus import wishbone
from migen.genlib.fsm import FSM, NextState
+
class NorFlash16(Module):
def __init__(self, pads, rd_timing, wr_timing):
self.bus = wishbone.Interface()
_DIOFR = 0xbb
_QIOFR = 0xeb
+
def _format_cmd(cmd, spi_width):
"""
`cmd` is the read instruction. Since everything is transmitted on all
c &= ~(1<<(b*spi_width))
return c
+
class SpiFlash(Module, AutoCSR):
def __init__(self, pads, dummy=15, div=2, with_bitbang=True):
"""
self.sync += timeline(bus.cyc & bus.stb & (i == div - 1), tseq)
+
class SpiFlashTB(Module):
def __init__(self):
self.submodules.master = wishbone.Initiator(self.gen_reads())
from misoclib.mem.sdram.core import minicon, lasmicon
from misoclib.mem.sdram.core import lasmixbar
+
class SDRAMCore(Module, AutoCSR):
def __init__(self, phy, geom_settings, timing_settings, controller_settings, **kwargs):
# DFI
from migen.genlib.record import *
from migen.genlib.misc import optree
+
class Interface(Record):
def __init__(self, aw, dw, nbanks, req_queue_size, read_latency, write_latency):
self.aw = aw
]
Record.__init__(self, layout)
+
class Initiator(Module):
def __init__(self, generator, bus):
self.generator = generator
else:
selfp.bus.we = 1
+
class TargetModel:
def __init__(self):
self.last_bank = 0
self.last_bank += 1
return self.last_bank
+
class _ReqFIFO(Module):
def __init__(self, req_queue_size, bank):
self.req_queue_size = req_queue_size
selfp.bank.lock = bool(self.contents)
do_simulation.passive = True
+
class Target(Module):
def __init__(self, model, *ifargs, **ifkwargs):
self.model = model
from misoclib.mem.sdram.core.lasmicon.bankmachine import *
from misoclib.mem.sdram.core.lasmicon.multiplexer import *
+
class LASMIconSettings:
def __init__(self, req_queue_size=8,
read_time=32, write_time=16,
self.with_memtest = with_memtest
self.with_refresh = with_refresh
+
class LASMIcon(Module):
def __init__(self, phy_settings, geom_settings, timing_settings, controller_settings, **kwargs):
if phy_settings.memtype in ["SDR"]:
from misoclib.mem.sdram.core.lasmicon.multiplexer import *
+
class _AddressSlicer:
def __init__(self, colbits, address_align):
self.colbits = colbits
else:
return Cat(Replicate(0, self.address_align), address[:split])
+
class BankMachine(Module):
def __init__(self, geom_settings, timing_settings, controller_settings, address_align, bankn, req):
self.refresh_req = Signal()
from misoclib.mem.sdram.core.lasmicon.perf import Bandwidth
+
class CommandRequest:
def __init__(self, a, ba):
self.a = Signal(a)
self.ras_n = Signal(reset=1)
self.we_n = Signal(reset=1)
+
class CommandRequestRW(CommandRequest):
def __init__(self, a, ba):
CommandRequest.__init__(self, a, ba)
self.is_read = Signal()
self.is_write = Signal()
+
class _CommandChooser(Module):
def __init__(self, requests):
self.want_reads = Signal()
for i, req in enumerate(requests)]
self.comb += rr.ce.eq(self.cmd.ack)
+
class _Steerer(Module):
def __init__(self, commands, dfi):
ncmd = len(commands)
phase.wrdata_en.eq(Array(stb_and(cmd, "is_write") for cmd in commands)[sel])
]
+
class Multiplexer(Module, AutoCSR):
def __init__(self, phy_settings, geom_settings, timing_settings, controller_settings, bank_machines, refresher, dfi, lasmic,
with_bandwidth=False):
from migen.fhdl.std import *
from migen.bank.description import *
+
class Bandwidth(Module, AutoCSR):
def __init__(self, cmd, data_width, period_bits=24):
self._update = CSR()
from misoclib.mem.sdram.core.lasmicon.multiplexer import *
+
class Refresher(Module):
def __init__(self, a, ba, tRP, tREFI, tRFC, enabled=True):
self.req = Signal()
from misoclib.mem.sdram.core.lasmibus import Interface
+
def _getattr_all(l, attr):
it = iter(l)
r = getattr(next(it), attr)
raise ValueError
return r
+
class LASMIxbar(Module):
def __init__(self, controllers, cba_shift):
self._controllers = controllers
from misoclib.mem.sdram.phy import dfi as dfibus
+
class _AddressSlicer:
def __init__(self, colbits, bankbits, rowbits, address_align):
self.colbits = colbits
else:
return Cat(Replicate(0, self.address_align), address[:split])
+
class MiniconSettings:
def __init__(self):
pass
+
class Minicon(Module):
def __init__(self, phy_settings, geom_settings, timing_settings):
if phy_settings.memtype in ["SDR"]:
from migen.flow.actor import *
from migen.genlib.fifo import SyncFIFO
+
class Reader(Module):
def __init__(self, lasmim, fifo_depth=None):
self.address = Sink([("a", lasmim.aw)])
from misoclib.mem.sdram.frontend import dma_lasmi
+
@DecorateModule(InsertReset)
@DecorateModule(InsertCE)
class LFSR(Module):
memtest_magic = 0x361f
+
class MemtestWriter(Module):
def __init__(self, lasmim):
self._magic = CSRStatus(16)
def get_csrs(self):
return [self._magic, self._reset, self._shoot] + self._dma.get_csrs()
+
class MemtestReader(Module):
def __init__(self, lasmim):
self._magic = CSRStatus(16)
def get_csrs(self):
return [self._magic, self._reset, self._error_count] + self._dma.get_csrs()
+
class _LFSRTB(Module):
def __init__(self, *args, **kwargs):
self.submodules.dut = LFSR(*args, **kwargs)
from migen.genlib.misc import split, displacer, chooser
from migen.genlib.record import Record, layout_len
+
# cachesize (in 32-bit words) is the size of the data store, must be a power of 2
class WB2LASMI(Module, AutoCSR):
def __init__(self, cachesize, lasmim):
from migen.fhdl.std import *
from misoclib.mem import sdram
+
class SDRAMModule:
def __init__(self, clk_freq, memtype, geom_settings, timing_settings):
self.clk_freq = clk_freq
t += clk_period_ns/2
return ceil(t/clk_period_ns)
+
# SDR
class IS42S16160(SDRAMModule):
geom_settings = {
SDRAMModule.__init__(self, clk_freq, "SDR", self.geom_settings,
self.timing_settings)
+
class MT48LC4M16(SDRAMModule):
geom_settings = {
"nbanks": 4,
SDRAMModule.__init__(self, clk_freq, "SDR", self.geom_settings,
self.timing_settings)
+
class AS4C16M16(SDRAMModule):
geom_settings = {
"nbanks": 4,
SDRAMModule.__init__(self, clk_freq, "SDR", self.geom_settings,
self.timing_settings)
+
# DDR
class MT46V32M16(SDRAMModule):
geom_settings = {
SDRAMModule.__init__(self, clk_freq, "DDR", self.geom_settings,
self.timing_settings)
+
# LPDDR
class MT46H32M16(SDRAMModule):
geom_settings = {
SDRAMModule.__init__(self, clk_freq, "LPDDR", self.geom_settings,
self.timing_settings)
+
# DDR2
class MT47H128M8(SDRAMModule):
geom_settings = {
SDRAMModule.__init__(self, clk_freq, "DDR2", self.geom_settings,
self.timing_settings)
+
# DDR3
class MT8JTF12864(SDRAMModule):
geom_settings = {
from migen.fhdl.std import *
from migen.genlib.record import *
+
def phase_cmd_description(addressbits, bankbits):
return [
("address", addressbits, DIR_M_TO_S),
("reset_n", 1, DIR_M_TO_S)
]
+
def phase_wrdata_description(databits):
return [
("wrdata", databits, DIR_M_TO_S),
("wrdata_mask", databits//8, DIR_M_TO_S)
]
+
def phase_rddata_description(databits):
return [
("rddata_en", 1, DIR_M_TO_S),
("rddata_valid", 1, DIR_S_TO_M)
]
+
def phase_description(addressbits, bankbits, databits):
r = phase_cmd_description(addressbits, bankbits)
r += phase_wrdata_description(databits)
r += phase_rddata_description(databits)
return r
+
class Interface(Record):
def __init__(self, addressbits, bankbits, databits, nphases=1):
layout = [("p"+str(i), phase_description(addressbits, bankbits, databits)) for i in range(nphases)]
r.append(("dfi_" + field + suffix, getattr(phase, field)))
return r
+
class Interconnect(Module):
def __init__(self, master, slave):
self.comb += master.connect(slave)
from misoclib.mem.sdram.phy import dfi
+
class PhaseInjector(Module, AutoCSR):
def __init__(self, phase):
self._command = CSRStorage(6) # cs, we, cas, ras, wren, rden
]
self.sync += If(phase.rddata_valid, self._rddata.status.eq(phase.rddata))
+
class DFIInjector(Module, AutoCSR):
def __init__(self, addressbits, bankbits, databits, nphases=1):
inti = dfi.Interface(addressbits, bankbits, databits, nphases)
from misoclib.mem.sdram.phy.dfi import *
from misoclib.mem import sdram
+
class GENSDRPHY(Module):
def __init__(self, pads, module):
addressbits = flen(pads.a)
from migen.fhdl.std import log2_int
+
def get_sdram_phy_header(sdram_phy_settings):
r = "#ifndef __GENERATED_SDRAM_PHY_H\n#define __GENERATED_SDRAM_PHY_H\n"
r += "#include <hw/common.h>\n#include <generated/csr.h>\n#include <hw/flags.h>\n\n"
from misoclib.mem.sdram.phy.dfi import *
from misoclib.mem import sdram
+
class K7DDRPHY(Module, AutoCSR):
def __init__(self, pads, module):
addressbits = flen(pads.a)
from misoclib.mem.sdram.phy.dfi import *
from misoclib.mem import sdram
+
class S6DDRPHY(Module):
def __init__(self, pads, module, rd_bitslip, wr_bitslip, dqs_ddr_alignment):
if module.memtype not in ["DDR", "LPDDR", "DDR2"]:
from misoclib.mem.sdram.phy.dfi import *
from misoclib.mem import sdram
+
class Bank(Module):
def __init__(self, data_width, nrows, ncols):
self.activate = Signal()
)
]
+
class DFIPhase(Module):
def __init__(self, dfi, n):
phase = getattr(dfi, "p"+str(n))
)
]
+
class SDRAMPHYSim(Module):
def __init__(self, module, settings):
addressbits = module.geom_settings.addressbits
from misoclib.mem.sdram.core import lasmibus
+
def my_generator(n):
bank = n % 4
for x in range(4):
print("{0}: Read {1:x} in {2} cycle(s)".format(n, t.data, t.latency))
assert(t.data == 0x1000*bank + 0x100*x)
+
class MyModel(lasmibus.TargetModel):
def read(self, bank, address):
r = 0x1000*bank + 0x100*address
print("write to bank {0} address {1:x} data {2:x}".format(bank, address, data))
assert(data == 0x1000*bank + 0x100*address)
+
class TB(Module):
def __init__(self):
self.submodules.controller = lasmibus.Target(MyModel(), aw=4, dw=32, nbanks=4, req_queue_size=4,
from common import sdram_phy, sdram_geom, sdram_timing, CommandLogger
+
def my_generator():
for x in range(10):
yield True, x
for x in range(10):
yield False, 128*x
+
class TB(Module):
def __init__(self):
self.req = Interface(32, 32, 1,
clk_freq = (83 + Fraction(1, 3))*MHz
clk_period_ns = 1000000000/clk_freq
+
+
def ns(t, margin=True):
if margin:
t += clk_period_ns/2
write_time=16
)
+
def decode_sdram(ras_n, cas_n, we_n, bank, address):
elts = []
if not ras_n and cas_n and we_n:
elts.append("LMR")
return elts
+
class CommandLogger(Module):
def __init__(self, cmd, rw=False):
self.cmd = cmd
print("\t".join(elts))
do_simulation.passive = True
+
class DFILogger(Module):
def __init__(self, dfi):
self.dfi = dfi
from common import sdram_phy, sdram_geom, sdram_timing, DFILogger
+
class TB(Module):
def __init__(self):
self.submodules.ctler = LASMIcon(sdram_phy, sdram_geom, sdram_timing)
from common import sdram_phy, sdram_geom, sdram_timing, DFILogger
+
def my_generator_r(n):
for x in range(10):
t = TRead(128*n + 48*n*x)
yield t
print("{0:3}: reads done".format(n))
+
def my_generator_w(n):
for x in range(10):
t = TWrite(128*n + 48*n*x, x)
yield t
print("{0:3}: writes done".format(n))
+
def my_generator(n):
if n % 2:
return my_generator_w(n // 2)
else:
return my_generator_r(n // 2)
+
class TB(Module):
def __init__(self):
self.submodules.dut = LASMIcon(sdram_phy, sdram_geom, sdram_timing)
l2_size = 8192 # in bytes
+
def my_generator():
for x in range(20):
t = TWrite(x, x)
yield t
print(str(t) + " delay=" + str(t.latency))
+
class TB(Module):
def __init__(self):
self.submodules.ctler = LASMIcon(sdram_phy, sdram_geom, sdram_timing)
from math import ceil
+
def ns(t, margin=True):
clk_period_ns = 1000000000/clk_freq
if margin:
t += clk_period_ns/2
return ceil(t/clk_period_ns)
+
class MiniconTB(Module):
def __init__(self, sdrphy, dfi, sdram_geom, sdram_timing, pads, sdram_clk):
while True:
yield
+
class MyTopLevel:
def __init__(self, vcd_name=None, vcd_level=1,
top_name="top", dut_type="dut", dut_name="dut",
from common import CommandLogger
+
class Granter(Module):
def __init__(self, req, ack):
self.req = req
if len(elts) > 1:
print("\t".join(elts))
+
class TB(Module):
def __init__(self):
self.submodules.dut = Refresher(13, 2, tRP=3, tREFI=100, tRFC=5)
from migen.fhdl.std import *
+
class MXCRG(Module):
def __init__(self, pads, outfreq1x):
self.clock_domains.cd_sys = ClockDomain()
from misoclib.cpu import lm32, mor1kx
from misoclib.cpu.peripherals import identifier, timer
+
def mem_decoder(address, start=26, end=29):
return lambda a: a[start:end] == ((address >> (start+2)) & (2**(end-start))-1)
+
class SoC(Module):
csr_map = {
"crg": 0, # user
from migen.fhdl.std import *
from migen.bank.description import CSRStatus
+
def get_cpu_mak(cpu_type):
if cpu_type == "lm32":
cpuflags = "-mbarrel-shift-enabled -mmultiply-enabled -mdivide-enabled -msign-extend-enabled"
raise ValueError("Unsupported CPU type: "+cpu_type)
return "CPU={}\nCPUFLAGS={}\n".format(cpu_type, cpuflags)
+
def get_linker_output_format(cpu_type):
return "OUTPUT_FORMAT(\"elf32-{}\")\n".format(cpu_type)
+
def get_linker_regions(regions):
r = "MEMORY {\n"
for name, origin, length in regions:
r += "}\n"
return r
+
def get_mem_header(regions, flash_boot_address):
r = "#ifndef __GENERATED_MEM_H\n#define __GENERATED_MEM_H\n\n"
for name, base, size in regions:
r += "#endif\n"
return r
+
def _get_rw_functions(reg_name, reg_base, nwords, busword, read_only):
r = ""
r += "}\n"
return r
+
def get_csr_header(regions, constants):
r = "#ifndef __GENERATED_CSR_H\n#define __GENERATED_CSR_H\n#include <hw/common.h>\n"
for name, origin, busword, obj in regions:
r += "\n#endif\n"
return r
+
def get_csr_csv(regions):
r = ""
for name, origin, busword, obj in regions:
from misoclib.mem.sdram.frontend import memtest, wishbone2lasmi
from misoclib.soc import SoC
+
class SDRAMSoC(SoC):
csr_map = {
"sdram": 8,
from misoclib.video.dvisampler.analysis import SyncPolarity, ResolutionDetection, FrameExtraction
from misoclib.video.dvisampler.dma import DMA
+
class DVISampler(Module, AutoCSR):
def __init__(self, pads, lasmim, n_dma_slots=2):
self.submodules.edid = EDID(pads)
from misoclib.video.dvisampler.common import channel_layout
+
class SyncPolarity(Module):
def __init__(self):
self.valid_i = Signal()
)
]
+
class ResolutionDetection(Module, AutoCSR):
def __init__(self, nbits=11):
self.valid_i = Signal()
)
self.specials += MultiReg(vcounter_st, self._vres.status)
+
class FrameExtraction(Module, AutoCSR):
def __init__(self, word_width):
# in pix clock domain
from misoclib.video.dvisampler.common import channel_layout
+
class _SyncBuffer(Module):
def __init__(self, width, depth):
self.din = Signal(width)
]
self.sync += If(self.re, _inc(consume, depth))
+
class ChanSync(Module, AutoCSR):
def __init__(self, nchan=3, depth=8):
self.valid_i = Signal()
)
self.specials += MultiReg(self.chan_synced, self._channels_synced.status)
+
class _TB(Module):
def __init__(self, test_seq_it):
self.test_seq_it = test_seq_it
from misoclib.video.dvisampler.common import control_tokens
+
class CharSync(Module, AutoCSR):
def __init__(self, required_controls=8):
self.raw_data = Signal(10)
from migen.genlib.cdc import MultiReg
from migen.bank.description import *
+
class Clocking(Module, AutoCSR):
def __init__(self, pads):
self._pll_reset = CSRStorage(reset=1)
from migen.genlib.cdc import MultiReg, PulseSynchronizer
from migen.bank.description import *
+
class DataCapture(Module, AutoCSR):
def __init__(self, pad_p, pad_n, ntbits):
self.serdesstrobe = Signal()
from misoclib.video.dvisampler.clocking import Clocking
from misoclib.video.dvisampler.datacapture import DataCapture
+
class RawDVISampler(Module, AutoCSR):
def __init__(self, pads, asmiport):
self.submodules.edid = EDID(pads)
from misoclib.video.dvisampler.common import control_tokens, channel_layout
+
class Decoding(Module):
def __init__(self):
self.valid_i = Signal()
from misoclib.mem.sdram.frontend import dma_lasmi
+
# Slot status: EMPTY=0 LOADED=1 PENDING=2
class _Slot(Module, AutoCSR):
def __init__(self, addr_bits, alignment_bits):
self.ev_source.trigger.eq(self._status.storage[1])
]
+
class _SlotArray(Module, AutoCSR):
def __init__(self, nslots, addr_bits, alignment_bits):
self.submodules.ev = EventManager()
self.comb += [slot.address_reached.eq(self.address_reached) for slot in slots]
self.comb += [slot.address_done.eq(self.address_done & (current_slot == n)) for n, slot in enumerate(slots)]
+
class DMA(Module):
def __init__(self, lasmim, nslots):
bus_aw = lasmim.aw
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x34,
]
+
class EDID(Module, AutoCSR):
def __init__(self, pads, default=_default_edid):
self._hpd_notif = CSRStatus()
from misoclib.video.dvisampler.common import control_tokens
+
class WER(Module, AutoCSR):
def __init__(self, period_bits=24):
self.data = Signal(10)
from misoclib.video.framebuffer.format import bpp, pixel_layout, FrameInitiator, VTG
from misoclib.video.framebuffer.phy import Driver
+
class Framebuffer(Module, AutoCSR):
def __init__(self, pads_vga, pads_dvi, lasmim):
pack_factor = lasmim.dw//bpp
control_tokens = [0b1101010100, 0b0010101011, 0b0101010100, 0b1010101011]
+
class Encoder(Module):
def __init__(self):
self.d = Signal(8)
cnt.eq(0)
)
+
class _EncoderSerializer(Module):
def __init__(self, serdesstrobe, pad_p, pad_n):
self.submodules.encoder = RenameClockDomains(Encoder(), "pix")
self.es2.de.eq(self.de),
]
+
class _EncoderTB(Module):
def __init__(self, inputs):
self.outs = []
if selfp.simulator.cycle_counter > 4:
self.outs.append(selfp.dut.out)
+
def _bit(i, n):
return (i >> n) & 1
+
def _decode_tmds(b):
try:
c = control_tokens.index(b)
("g", bpc),
("b", bpc)
]
+
+
def pixel_layout(pack_factor):
return [("p"+str(i), pixel_layout_s) for i in range(pack_factor)]
("g", bpc_phy),
("b", bpc_phy)
]
+
+
def phy_layout(pack_factor):
r = [("hsync", 1), ("vsync", 1), ("de", 1)]
for i in range(pack_factor):
r.append(("p"+str(i), phy_layout_s))
return r
+
class FrameInitiator(spi.SingleGenerator):
def __init__(self, bus_aw, pack_factor, ndmas=1):
h_alignment_bits = log2_int(pack_factor)
def dma_subr(self, i=0):
return ["length", "base"+str(i)]
+
class VTG(Module):
def __init__(self, pack_factor):
hbits_dyn = _hbits - log2_int(pack_factor)
from misoclib.video.framebuffer.format import bpc_phy, phy_layout
from misoclib.video.framebuffer import dvi
+
class _FIFO(Module):
def __init__(self, pack_factor):
self.phy = Sink(phy_layout(pack_factor))
)
self.comb += fifo.re.eq(unpack_counter == (pack_factor - 1))
+
# This assumes a 50MHz base clock
class _Clocking(Module, AutoCSR):
def __init__(self, pads_vga, pads_dvi):
self.specials += Instance("OBUFDS", i_I=dvi_clk_se,
o_O=pads_dvi.clk_p, o_OB=pads_dvi.clk_n)
+
class Driver(Module, AutoCSR):
def __init__(self, pack_factor, pads_vga, pads_dvi):
fifo = _FIFO(pack_factor)
from misoclib.mem.sdram.core.lasmicon import LASMIconSettings
from misoclib.soc.sdram import SDRAMSoC
+
class _PLL(Module):
def __init__(self, period_in, name, phase_shift, operation_mode):
self.clk_in = Signal()
i_scanwrite=0
)
+
class _CRG(Module):
def __init__(self, platform):
self.clock_domains.cd_sys = ClockDomain()
self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
+
class BaseSoC(SDRAMSoC):
default_platform = "de0nano"
from misoclib.com.liteeth.phy import LiteEthPHY
from misoclib.com.liteeth.mac import LiteEthMAC
+
class _CRG(Module):
def __init__(self, platform):
self.clock_domains.cd_sys = ClockDomain()
)
self.specials += Instance("IDELAYCTRL", i_REFCLK=ClockSignal("clk200"), i_RST=ic_reset)
+
class BaseSoC(SDRAMSoC):
default_platform = "kc705"
self.flash_boot_address = 0xb00000
self.register_rom(self.spiflash.bus)
+
class MiniSoC(BaseSoC):
csr_map = {
"ethphy": 18,
from misoclib.mem.sdram.core.lasmicon import LASMIconSettings
from misoclib.soc.sdram import SDRAMSoC
+
class _CRG(Module):
def __init__(self, platform, clk_freq):
self.clock_domains.cd_sys = ClockDomain()
i_C0=self.cd_sys.clk, i_C1=~self.cd_sys.clk,
o_Q=platform.request("sdram_clock"))
+
class BaseSoC(SDRAMSoC):
default_platform = "minispartan6"
from misoclib.com.liteeth.phy import LiteEthPHY
from misoclib.com.liteeth.mac import LiteEthMAC
+
class _MXClockPads:
def __init__(self, platform):
self.clk50 = platform.request("clk50")
self.ddr_clk_p = ddram_clock.p
self.ddr_clk_n = ddram_clock.n
+
class BaseSoC(SDRAMSoC):
default_platform = "mixxeo" # also supports m1
""")
platform.add_source_dir(os.path.join("misoclib", "others", "mxcrg"))
+
class MiniSoC(BaseSoC):
csr_map = {
"ethphy": 16,
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"]+0x80000000, 0x2000)
+
def get_vga_dvi(platform):
try:
pads_vga = platform.request("vga_out")
""")
return pads_vga, pads_dvi
+
def add_vga_tig(platform, fb):
platform.add_platform_command("""
NET "{vga_clk}" TNM_NET = "GRPvga_clk";
TIMESPEC "TSise_sucks2" = FROM "GRPsys_clk" TO "GRPvga_clk" TIG;
""", vga_clk=fb.driver.clocking.cd_pix.clk)
+
class FramebufferSoC(MiniSoC):
csr_map = {
"fb": 18,
from misoclib.mem.flash import spiflash
from misoclib.soc.sdram import SDRAMSoC
+
class _CRG(Module):
def __init__(self, platform, clk_freq):
self.clock_domains.cd_sys = ClockDomain()
i_C0=clk_sdram_half_shifted, i_C1=~clk_sdram_half_shifted,
o_Q=clk.n)
+
class BaseSoC(SDRAMSoC):
default_platform = "pipistrello"
from misoclib.mem.flash import spiflash
from misoclib.soc.sdram import SDRAMSoC
+
class _CRG(Module):
def __init__(self, platform, clk_freq):
self.clock_domains.cd_sys = ClockDomain()
i_C0=self.cd_sys.clk, i_C1=~self.cd_sys.clk,
o_Q=platform.request("sdram_clock"))
+
class BaseSoC(SDRAMSoC):
default_platform = "papilio_pro"
from misoclib.com.liteeth.phy import LiteEthPHY
from misoclib.com.liteeth.mac import LiteEthMAC
+
class BaseSoC(SoC):
def __init__(self, platform, **kwargs):
SoC.__init__(self, platform,
**kwargs)
self.submodules.crg = CRG(platform.request(platform.default_clk_name))
+
class MiniSoC(BaseSoC):
csr_map = {
"ethphy": 20,
from misoclib.soc import SoC
+
class BaseSoC(SoC):
default_platform = "versa"
def __init__(self, platform, **kwargs):
0x6E17, 0x7E36, 0x4E55, 0x5E74, 0x2E93, 0x3EB2, 0x0ED1, 0x1EF0
]
+
def crc16(l):
crc = 0
for d in l:
crc = crc16_table[((crc >> 8) ^ d) & 0xff] ^ (crc << 8)
return crc
+
class SFLFrame:
def __init__(self):
self.length = None
for d in self.payload:
self.raw.append(d)
+
def get_file_data(filename):
with open(filename, "rb") as f:
data = []
data.append(int.from_bytes(w, "big"))
return data
+
class Flterm:
def __init__(self, kernel_image, kernel_address):
self.kernel_image = kernel_image
if not writer_only:
self.reader_thread.join()
+
def _get_args():
parser = argparse.ArgumentParser()
parser.add_argument("--port", default="2", help="serial port")
projects / litex.git / commitdiff