i965: Add a couple SNB state packets I saw in other batchbuffer dumps.

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 50c4d6d0a469f0dd7f6a28070f869f9a47bddcde..52cd12df5983db9e89ecf0fa13f07e94747d7f8b 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1024,6 +1024,8 @@
 # define GEN6_CONSTANT_BUFFER_1_ENABLE                 (1 << 13)
 # define GEN6_CONSTANT_BUFFER_0_ENABLE                 (1 << 12)
 
+#define CMD_3D_SAMPLE_MASK                     0x7818 /* GEN6+ */
+
 #define CMD_DRAW_RECT                 0x7900
 #define CMD_BLEND_CONSTANT_COLOR      0x7901
 #define CMD_CHROMA_KEY                0x7904
@@ -1034,6 +1036,25 @@
 #define CMD_GLOBAL_DEPTH_OFFSET_CLAMP 0x7909
 #define CMD_AA_LINE_PARAMETERS        0x790a
 
+#define CMD_GS_SVB_INDEX                       0x790b /* CTG+ */
+/* DW1 */
+# define SVB_INDEX_SHIFT                               29
+# define SVB_LOAD_INTERNAL_VERTEX_COUNT                        (1 << 0) /* SNB+ */
+/* DW2: SVB index */
+/* DW3: SVB maximum index */
+
+#define CMD_3D_MULTISAMPLE                     0x790d /* SNB+ */
+/* DW1 */
+# define MS_PIXEL_LOCATION_CENTER                      (0 << 4)
+# define MS_PIXEL_LOCATION_UPPER_LEFT                  (1 << 4)
+# define MS_NUMSAMPLES_1                               (0 << 1)
+# define MS_NUMSAMPLES_4                               (2 << 1)
+# define MS_NUMSAMPLES_8                               (3 << 1)
+
+#define CMD_3D_CLEAR_PARAMS                    0x7910 /* ILK+ */
+# define DEPTH_CLEAR_VALID                             (1 << 15)
+/* DW1: depth clear value */
+
 #define CMD_PIPE_CONTROL              0x7a00
 
 #define CMD_3D_PRIM                   0x7b00

diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index b4e7dd547f3b1fcc0baa576d153f9f6f4ad0adf2..d030ed41f4a4552a2e7ebb74e4f3ca6e2871863e 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -314,6 +314,14 @@ static void emit_depthbuffer(struct brw_context *brw)
 
       ADVANCE_BATCH();
    }
+
+   /* Initialize it for safety. */
+   if (intel->gen >= 6) {
+      BEGIN_BATCH(2);
+      OUT_BATCH(CMD_3D_CLEAR_PARAMS << 16 | (2 - 2));
+      OUT_BATCH(0);
+      ADVANCE_BATCH();
+   }
 }
 
 const struct brw_tracked_state brw_depthbuffer = {
@@ -511,6 +519,32 @@ static void upload_invarient_state( struct brw_context *brw )
       BRW_BATCH_STRUCT(brw, &gdo);
    }
 
+   intel_batchbuffer_emit_mi_flush(intel->batch);
+
+   if (intel->gen >= 6) {
+      int i;
+
+      BEGIN_BATCH(3);
+      OUT_BATCH(CMD_3D_MULTISAMPLE << 16 | (3 - 2));
+      OUT_BATCH(MS_PIXEL_LOCATION_CENTER |
+               MS_NUMSAMPLES_1);
+      OUT_BATCH(0); /* positions for 4/8-sample */
+      ADVANCE_BATCH();
+
+      BEGIN_BATCH(2);
+      OUT_BATCH(CMD_3D_SAMPLE_MASK << 16 | (2 - 2));
+      OUT_BATCH(1);
+      ADVANCE_BATCH();
+
+      for (i = 0; i < 4; i++) {
+        BEGIN_BATCH(4);
+        OUT_BATCH(CMD_GS_SVB_INDEX << 16 | (4 - 2));
+        OUT_BATCH(i << SVB_INDEX_SHIFT);
+        OUT_BATCH(0);
+        OUT_BATCH(0xffffffff);
+        ADVANCE_BATCH();
+      }
+   }
 
    /* 0x61020000  State Instruction Pointer */
    {