[aarch64] PR target/91386 Use copy_rtx to avoid modifying original insns in peep2...

PR target/91386 is a situation where a peephole2 pattern substitution
is discarded late because the selected instructions contain
frame-related notes that we cannot redistribute (because the pattern
has more than one insn in the output).  Unfortunately, the original
insns were being modified during the generation, so after the undo we
are left with corrupt RTL.

We avoid this by ensuring that the modifications are always made on a
copy, so that the original insns are never changed.

	PR target/91386
	* config/aarch64/aarch64.c (aarch64_gen_adjusted_ldpstp): Use copy_rtx
	to preserve the contents of the original insns.

From-SVN: r274238

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index e19322b5a9ecc5282145b75ec0697696db3e365b..de5a347d5a3cee37b748cbb9afa73336f75896c4 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,6 +1,12 @@
+2019-09-09  Richard Earnshaw  <rearnsha@arm.com>
+
+       PR target/91386
+       * config/aarch64/aarch64.c (aarch64_gen_adjusted_ldpstp): Use copy_rtx
+       to preserve the contents of the original insns.
+
 2019-08-09  Richard Earnshaw  <rearnsha@arm.com>
 
-       *confit/arm/arm.md (addsi3_compare_op1): Add 16-bit thumb-2 variants.
+       *config/arm/arm.md (addsi3_compare_op1): Add 16-bit thumb-2 variants.
        (addsi3_compare_op2): Likewise.
 
 2019-08-09  Martin Liska  <mliska@suse.cz>

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index b99d5ec0e2b06521bd5b59df22926a9a56d2688d..48ec1ac5d5ed15adb773012c30b6515ba5cbc80f 100644 (file)
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -18546,19 +18546,21 @@ aarch64_gen_adjusted_ldpstp (rtx *operands, bool load,
   /* Sort the operands.  */
   qsort (temp_operands, 4, 2 * sizeof (rtx *), aarch64_ldrstr_offset_compare);
 
+  /* Copy the memory operands so that if we have to bail for some
+     reason the original addresses are unchanged.  */
   if (load)
     {
-      mem_1 = temp_operands[1];
-      mem_2 = temp_operands[3];
-      mem_3 = temp_operands[5];
-      mem_4 = temp_operands[7];
+      mem_1 = copy_rtx (temp_operands[1]);
+      mem_2 = copy_rtx (temp_operands[3]);
+      mem_3 = copy_rtx (temp_operands[5]);
+      mem_4 = copy_rtx (temp_operands[7]);
     }
   else
     {
-      mem_1 = temp_operands[0];
-      mem_2 = temp_operands[2];
-      mem_3 = temp_operands[4];
-      mem_4 = temp_operands[6];
+      mem_1 = copy_rtx (temp_operands[0]);
+      mem_2 = copy_rtx (temp_operands[2]);
+      mem_3 = copy_rtx (temp_operands[4]);
+      mem_4 = copy_rtx (temp_operands[6]);
       gcc_assert (code == UNKNOWN);
     }