i965: Remove unused PIPE_CONTROL defines.

Both brw_defines.h and intel_reg.h defined PIPE_CONTROL fields, which
had similar names, but couldn't be used in the same way.  (One had
built-in shifts, and the other didn't...)

Delete the unused set to preserve sanity.

(Eric wrote an almost identical patch back in August, so I believe he
approves.)

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index dc38acea21ba8157db2c7574e1d249745b901c67..0fc24a7ede99341e615d42585cfa69740f750a05 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -38,14 +38,6 @@
 
 /* 3D state:
  */
-#define PIPE_CONTROL_NOWRITE          0x00
-#define PIPE_CONTROL_WRITEIMMEDIATE   0x01
-#define PIPE_CONTROL_WRITEDEPTH       0x02
-#define PIPE_CONTROL_WRITETIMESTAMP   0x03
-
-#define PIPE_CONTROL_GTTWRITE_PROCESS_LOCAL 0x00
-#define PIPE_CONTROL_GTTWRITE_GLOBAL        0x01
-
 #define CMD_3D_PRIM                                 0x7b00 /* 3DPRIMITIVE */
 /* DW0 */
 # define GEN4_3DPRIM_TOPOLOGY_TYPE_SHIFT            10
@@ -1919,8 +1911,6 @@ enum brw_wm_barycentric_interp_mode {
 /* DW2: start address */
 /* DW3: end address. */
 
-#define CMD_PIPE_CONTROL              0x7a00
-
 #define CMD_MI_FLUSH                  0x0200
 
 #define GEN5_MI_REPORT_PERF_COUNT ((0x26 << 23) | (3 - 2))