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Update CHANGELOG
authorEddie Hung <eddie@fpgeh.com>
Mon, 8 Apr 2019 23:22:07 +0000 (16:22 -0700)
committerEddie Hung <eddie@fpgeh.com>
Mon, 8 Apr 2019 23:22:07 +0000 (16:22 -0700)
CHANGELOG patch | blob | history

diff --git a/CHANGELOG b/CHANGELOG
index 95bbb3f33d44a2ec86fa19cf165a7a4115dae669..36b64e111e9ac8bc09b03ceb3de9d9aff6ee1eeb 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -16,7 +16,7 @@ Yosys 0.8 .. Yosys 0.8-dev
     - Added "gate2lut.v" techmap rule
     - Added "rename -src"
     - Added "equiv_opt" pass
-    - Added "shregmap -tech xilinx", used by "synth_xilinx"
+    - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"
 
 
 Yosys 0.7 .. Yosys 0.8