ac/surface: remove RADEON_SURF_TC_COMPATIBLE_HTILE and assume it's always set

So that drivers can enable it without worrying how the texture was
allocated.

v2: reworked the mechanism, hopefully fixes now
    added Bas Nieuwenhuizen's diff to fix radv

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> (v1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4697>

diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 55595a66781b6db79b28faf075e2ffc5339a39d2..9b1ccca7371861d9781835009da913abf42780cb 100644 (file)
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -652,7 +652,8 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
        AddrSurfInfoIn.flags.cube = config->is_cube;
        AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
        AddrSurfInfoIn.flags.pow2Pad = config->info.levels > 1;
-       AddrSurfInfoIn.flags.tcCompatible = (surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) != 0;
+       AddrSurfInfoIn.flags.tcCompatible = info->chip_class >= GFX8 &&
+                                           AddrSurfInfoIn.flags.depth;
 
        /* Only degrade the tile mode for space if TC-compatible HTILE hasn't been
         * requested, because TC-compatible HTILE requires 2D tiling.
@@ -773,6 +774,7 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
        surf->htile_size = 0;
        surf->htile_slice_size = 0;
        surf->htile_alignment = 1;
+       surf->tc_compatible_htile_allowed = AddrSurfInfoIn.flags.tcCompatible;
 
        const bool only_stencil = (surf->flags & RADEON_SURF_SBUFFER) &&
                                  !(surf->flags & RADEON_SURF_ZBUFFER);
@@ -789,10 +791,11 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
                        if (level > 0)
                                continue;
 
-                       if (!AddrSurfInfoOut.tcCompatible) {
+                       if (!AddrSurfInfoOut.tcCompatible)
                                AddrSurfInfoIn.flags.tcCompatible = 0;
-                               surf->flags &= ~RADEON_SURF_TC_COMPATIBLE_HTILE;
-                       }
+
+                       if (!AddrSurfInfoOut.tcCompatible || !surf->htile_size)
+                               surf->tc_compatible_htile_allowed = false;
 
                        if (AddrSurfInfoIn.flags.matchStencilTileCfg) {
                                AddrSurfInfoIn.flags.matchStencilTileCfg = 0;
@@ -938,7 +941,7 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
         * TC-compatible HTILE even for levels where it's disabled by DB.
         */
        if (surf->htile_size && config->info.levels > 1 &&
-           surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) {
+           surf->tc_compatible_htile_allowed) {
                /* MSAA can't occur with levels > 1, so ignore the sample count. */
                const unsigned total_pixels = surf->surf_size / surf->bpe;
                const unsigned htile_block_size = 8 * 8;
@@ -1487,14 +1490,12 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
                AddrSurfInfoIn.bpp = surf->bpe * 8;
        }
 
-       bool is_color_surface = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
-       AddrSurfInfoIn.flags.color = is_color_surface &&
+       AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
                                     !(surf->flags & RADEON_SURF_NO_RENDER_TARGET);
        AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
        AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
        /* flags.texture currently refers to TC-compatible HTILE */
-       AddrSurfInfoIn.flags.texture = is_color_surface ||
-                                      surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
+       AddrSurfInfoIn.flags.texture = 1;
        AddrSurfInfoIn.flags.opt4space = 1;
 
        AddrSurfInfoIn.numMipLevels = config->info.levels;
@@ -1535,7 +1536,7 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
         * PIPE_ALIGNED is optional, but PIPE_ALIGNED=0 requires L2 flushes
         * after rendering, so PIPE_ALIGNED=1 is recommended.
         */
-       if (info->use_display_dcc_unaligned && is_color_surface &&
+       if (info->use_display_dcc_unaligned &&
            AddrSurfInfoIn.flags.display) {
                AddrSurfInfoIn.flags.metaPipeUnaligned = 1;
                AddrSurfInfoIn.flags.metaRbUnaligned = 1;
@@ -1608,6 +1609,7 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
        }
 
        surf->is_linear = surf->u.gfx9.surf.swizzle_mode == ADDR_SW_LINEAR;
+       surf->tc_compatible_htile_allowed = surf->htile_size != 0;
 
        /* Query whether the surface is displayable. */
        bool displayable = false;

diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index 56b2cb9aa5a470147b0e30ac886f1117df7a0218..a5e28c1a69c56130b4ec49b58b9528268b99523a 100644 (file)
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -67,7 +67,7 @@ enum radeon_micro_mode {
 /* bits 19 and 20 are reserved for libdrm_radeon, don't use them */
 #define RADEON_SURF_FMASK                       (1 << 21)
 #define RADEON_SURF_DISABLE_DCC                 (1 << 22)
-#define RADEON_SURF_TC_COMPATIBLE_HTILE         (1 << 23)
+/* gap */
 #define RADEON_SURF_IMPORTED                    (1 << 24)
 #define RADEON_SURF_OPTIMIZE_FOR_SPACE          (1 << 25)
 #define RADEON_SURF_SHAREABLE                   (1 << 26)
@@ -189,6 +189,7 @@ struct radeon_surf {
     unsigned                    has_stencil:1;
     /* This might be true even if micro_tile_mode isn't displayable or rotated. */
     unsigned                    is_displayable:1;
+    unsigned                    tc_compatible_htile_allowed:1;
     /* Displayable, thin, depth, rotated. AKA D,S,Z,R swizzle modes. */
     unsigned                    micro_tile_mode:3;
     uint32_t                    flags;

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 7bfd34041cdd49acf0f8331e5166a5e7c4693819..9633710bfdfd793cf3036b765c0142130650aa4a 100644 (file)
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -437,11 +437,8 @@ radv_init_surface(struct radv_device *device,
                unreachable("unhandled image type");
        }
 
-       if (is_depth) {
+       if (is_depth)
                surface->flags |= RADEON_SURF_ZBUFFER;
-               if (radv_use_tc_compat_htile_for_image(device, pCreateInfo, image_format))
-                       surface->flags |= RADEON_SURF_TC_COMPATIBLE_HTILE;
-       }
 
        if (is_stencil)
                surface->flags |= RADEON_SURF_SBUFFER;
@@ -1353,6 +1350,8 @@ static void radv_image_disable_htile(struct radv_image *image)
 {
        for (unsigned i = 0; i < image->plane_count; ++i)
                image->planes[i].surface.htile_size = 0;
+
+       image->tc_compatible_htile = false;
 }
 
 VkResult
@@ -1424,7 +1423,8 @@ radv_image_create_layout(struct radv_device *device,
                        /* Otherwise, try to enable HTILE for depth surfaces. */
                        if (radv_image_can_enable_htile(image) &&
                            !(device->instance->debug_flags & RADV_DEBUG_NO_HIZ)) {
-                               image->tc_compatible_htile = image->planes[0].surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
+                               if (!image->planes[0].surface.tc_compatible_htile_allowed)
+                                       image->tc_compatible_htile = false;
                                radv_image_alloc_htile(device, image);
                        } else {
                                radv_image_disable_htile(image);
@@ -1502,6 +1502,10 @@ radv_image_create(VkDevice _device,
                image->info.surf_index = &device->image_mrt_offset_counter;
        }
 
+       image->tc_compatible_htile =
+               radv_use_tc_compat_htile_for_image(device, create_info->vk_info,
+                                                  image->vk_format);
+
        for (unsigned plane = 0; plane < image->plane_count; ++plane) {
                radv_init_surface(device, image, &image->planes[plane].surface, plane, pCreateInfo, format);
        }

diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c
index 6b4ff99b0891cd426ab10ee2bf636f5122f31633..bf919b75981d37bca9ab32efe25d961267c872db 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_texture.c
+++ b/src/gallium/drivers/radeonsi/si_texture.c
@@ -241,8 +241,6 @@ static int si_init_surface(struct si_screen *sscreen, struct radeon_surf *surfac
           */
          if (sscreen->info.chip_class == GFX8)
             bpe = 4;
-
-         flags |= RADEON_SURF_TC_COMPATIBLE_HTILE;
       }
 
       if (is_stencil)
@@ -1198,7 +1196,8 @@ static struct si_texture *si_texture_create_object(struct pipe_screen *screen,
                                                    const struct radeon_surf *surface,
                                                    const struct si_texture *plane0,
                                                    struct pb_buffer *imported_buf, uint64_t offset,
-                                                   uint64_t alloc_size, unsigned alignment)
+                                                   uint64_t alloc_size, unsigned alignment,
+                                                   bool tc_compatible_htile)
 {
    struct si_texture *tex;
    struct si_resource *resource;
@@ -1217,8 +1216,8 @@ static struct si_texture *si_texture_create_object(struct pipe_screen *screen,
    /* don't include stencil-only formats which we don't support for rendering */
    tex->is_depth = util_format_has_depth(util_format_description(tex->buffer.b.b.format));
    tex->surface = *surface;
-   tex->tc_compatible_htile =
-      tex->surface.htile_size != 0 && (tex->surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE);
+   tex->tc_compatible_htile = tex->surface.tc_compatible_htile_allowed &&
+                              tc_compatible_htile;
 
    /* TC-compatible HTILE:
     * - GFX8 only supports Z32_FLOAT.
@@ -1579,7 +1578,8 @@ struct pipe_resource *si_texture_create(struct pipe_screen *screen,
    for (unsigned i = 0; i < num_planes; i++) {
       struct si_texture *tex =
          si_texture_create_object(screen, &plane_templ[i], &surface[i], plane0, NULL,
-                                  plane_offset[i], total_size, max_alignment);
+                                  plane_offset[i], total_size, max_alignment,
+                                  tc_compatible_htile);
       if (!tex) {
          si_texture_reference(&plane0, NULL);
          return NULL;
@@ -1651,7 +1651,7 @@ static struct pipe_resource *si_texture_from_winsys_buffer(struct si_screen *ssc
    if (r)
       return NULL;
 
-   tex = si_texture_create_object(&sscreen->b, templ, &surface, NULL, buf, offset, 0, 0);
+   tex = si_texture_create_object(&sscreen->b, templ, &surface, NULL, buf, offset, 0, 0, false);
    if (!tex)
       return NULL;