[rs6000] Fix ambiguous .md attribute uses

This patch is part of a series that fixes ambiguous attribute
uses in .md files, i.e. cases in which attributes didn't use
<ITER:ATTR> to specify an iterator, and in which <ATTR> could
have different values depending on the iterator chosen.

No behavioural change -- produces the same code as before except
for formatting and line numbers.

2019-07-16  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/rs6000/rs6000.md (*mov<mode>_update1): Explicitly
	use <SFDF:mode>, <SFDF:MODE>, <SFDF:Ff> and <SFDF:bits> rather than
	leaving the choice between SFDF and P implicit.
	(*mov<mode>_update2): Likewise.
	(*cmp<IBM128:mode>_internal2): Explicitly use <IBM128:MODE>
	rather than leaving the choice betweem IBM128 and GPR implicit.
	(*fix<uns>_trunc<IEEE128:mode><QHSI:mode>2_mem): Explicitly use
	<IEEE128:MODE> rather than leaving the choice between IEEE128 and
	QHSI implicit.
	(AltiVec define_peephole2s): Explicitly use <ALTIVEC_DFORM:MODE>
	rather than leaving the choice between ALTIVEC_DFORM and P implicit.
	* config/rs6000/vsx.md
	(*vsx_ext_<VSX_EXTRACT_I:VS_scalar>_fl_<FL_CONV:mode>)
	(*vsx_ext_<VSX_EXTRACT_I:VS_scalar>_ufl_<FL_CONV:mode>): Explicitly
	use <FL_CONV:VSisa> rather than leaving the choice between FL_CONV
	and VSX_EXTRACT_I implicit.

From-SVN: r273509

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 69a7f8e7f858e1b763355bbf55b4d1758ee6878d..d8998f6b8088de8241096e937aaf8d48b40d92f0 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,22 @@
+2019-07-16  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * config/rs6000/rs6000.md (*mov<mode>_update1): Explicitly
+       use <SFDF:mode>, <SFDF:MODE>, <SFDF:Ff> and <SFDF:bits> rather than
+       leaving the choice between SFDF and P implicit.
+       (*mov<mode>_update2): Likewise.
+       (*cmp<IBM128:mode>_internal2): Explicitly use <IBM128:MODE>
+       rather than leaving the choice betweem IBM128 and GPR implicit.
+       (*fix<uns>_trunc<IEEE128:mode><QHSI:mode>2_mem): Explicitly use
+       <IEEE128:MODE> rather than leaving the choice between IEEE128 and
+       QHSI implicit.
+       (AltiVec define_peephole2s): Explicitly use <ALTIVEC_DFORM:MODE>
+       rather than leaving the choice between ALTIVEC_DFORM and P implicit.
+       * config/rs6000/vsx.md
+       (*vsx_ext_<VSX_EXTRACT_I:VS_scalar>_fl_<FL_CONV:mode>)
+       (*vsx_ext_<VSX_EXTRACT_I:VS_scalar>_ufl_<FL_CONV:mode>): Explicitly
+       use <FL_CONV:VSisa> rather than leaving the choice between FL_CONV
+       and VSX_EXTRACT_I implicit.
+
 2019-07-16  Richard Sandiford  <richard.sandiford@arm.com>
 
        * config/mips/micromips.md (*movep<MOVEP1:mode><MOVEP2:mode>):

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index e1f0b0a43a510fdbc384731a677e37809db45f34..4ef199346526cf88215791a467fcecc11d0150de 100644 (file)
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -9311,14 +9311,14 @@
    (set_attr "update" "yes")
    (set_attr "indexed" "yes,no")])
 
-(define_insn "*mov<mode>_update1"
-  [(set (match_operand:SFDF 3 "gpc_reg_operand" "=<Ff>,<Ff>")
+(define_insn "*mov<SFDF:mode>_update1"
+  [(set (match_operand:SFDF 3 "gpc_reg_operand" "=<SFDF:Ff>,<SFDF:Ff>")
        (mem:SFDF (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
                          (match_operand:P 2 "reg_or_short_operand" "r,I"))))
    (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
        (plus:P (match_dup 1) (match_dup 2)))]
   "TARGET_HARD_FLOAT && TARGET_UPDATE
-   && (!avoiding_indexed_address_p (<MODE>mode)
+   && (!avoiding_indexed_address_p (<SFDF:MODE>mode)
        || !gpc_reg_operand (operands[2], Pmode))"
   "@
    lf<sd>ux %3,%0,%2
@@ -9326,16 +9326,16 @@
   [(set_attr "type" "fpload")
    (set_attr "update" "yes")
    (set_attr "indexed" "yes,no")
-   (set_attr "size" "<bits>")])
+   (set_attr "size" "<SFDF:bits>")])
 
-(define_insn "*mov<mode>_update2"
+(define_insn "*mov<SFDF:mode>_update2"
   [(set (mem:SFDF (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
                          (match_operand:P 2 "reg_or_short_operand" "r,I")))
-       (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,<Ff>"))
+       (match_operand:SFDF 3 "gpc_reg_operand" "<SFDF:Ff>,<SFDF:Ff>"))
    (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
        (plus:P (match_dup 1) (match_dup 2)))]
   "TARGET_HARD_FLOAT && TARGET_UPDATE
-   && (!avoiding_indexed_address_p (<MODE>mode)
+   && (!avoiding_indexed_address_p (<SFDF:MODE>mode)
        || !gpc_reg_operand (operands[2], Pmode))"
   "@
    stf<sd>ux %3,%0,%2
@@ -9343,7 +9343,7 @@
   [(set_attr "type" "fpstore")
    (set_attr "update" "yes")
    (set_attr "indexed" "yes,no")
-   (set_attr "size" "<bits>")])
+   (set_attr "size" "<SFDF:bits>")])
 
 (define_insn "*movsf_update3"
   [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
@@ -11557,7 +11557,7 @@
   [(set_attr "type" "fpcompare")
    (set_attr "length" "12")])
 
-(define_insn_and_split "*cmp<mode>_internal2"
+(define_insn_and_split "*cmp<IBM128:mode>_internal2"
   [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
        (compare:CCFP (match_operand:IBM128 1 "gpc_reg_operand" "d")
                      (match_operand:IBM128 2 "gpc_reg_operand" "d")))
@@ -11570,7 +11570,7 @@
     (clobber (match_scratch:DF 9 "=d"))
     (clobber (match_scratch:DF 10 "=d"))
     (clobber (match_scratch:GPR 11 "=b"))]
-  "TARGET_XL_COMPAT && FLOAT128_IBM_P (<MODE>mode)
+  "TARGET_XL_COMPAT && FLOAT128_IBM_P (<IBM128:MODE>mode)
    && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
   "#"
   "&& reload_completed"
@@ -11594,10 +11594,14 @@
   const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
   const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
 
-  operands[5] = simplify_gen_subreg (DFmode, operands[1], <MODE>mode, hi_word);
-  operands[6] = simplify_gen_subreg (DFmode, operands[1], <MODE>mode, lo_word);
-  operands[7] = simplify_gen_subreg (DFmode, operands[2], <MODE>mode, hi_word);
-  operands[8] = simplify_gen_subreg (DFmode, operands[2], <MODE>mode, lo_word);
+  operands[5] = simplify_gen_subreg (DFmode, operands[1],
+                                    <IBM128:MODE>mode, hi_word);
+  operands[6] = simplify_gen_subreg (DFmode, operands[1],
+                                    <IBM128:MODE>mode, lo_word);
+  operands[7] = simplify_gen_subreg (DFmode, operands[2],
+                                    <IBM128:MODE>mode, hi_word);
+  operands[8] = simplify_gen_subreg (DFmode, operands[2],
+                                    <IBM128:MODE>mode, lo_word);
   operands[12] = gen_label_rtx ();
   operands[13] = gen_label_rtx ();
   real_inf (&rv);
@@ -13596,7 +13600,7 @@
   new_addr = gen_rtx_PLUS (Pmode, add_op0, tmp_reg);
 
   operands[4] = add_op1;
-  operands[5] = change_address (mem, <MODE>mode, new_addr);
+  operands[5] = change_address (mem, <ALTIVEC_DFORM:MODE>mode, new_addr);
 })
 
 ;; Optimize cases were want to do a D-form store on ISA 2.06/2.07 from an
@@ -13632,7 +13636,7 @@
   new_addr = gen_rtx_PLUS (Pmode, add_op0, tmp_reg);
 
   operands[4] = add_op1;
-  operands[5] = change_address (mem, <MODE>mode, new_addr);
+  operands[5] = change_address (mem, <ALTIVEC_DFORM:MODE>mode, new_addr);
 })
    
 \f
@@ -14072,7 +14076,7 @@
        (any_fix:QHSI
         (match_operand:IEEE128 1 "altivec_register_operand" "v")))
    (clobber (match_scratch:QHSI 2 "=v"))]
-  "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+  "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<IEEE128:MODE>mode)"
   "#"
   "&& reload_completed"
   [(set (match_dup 2)

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index c33b45a334f745c89657ef735b50042026b779ec..7633171df9c8ff24bbda39e0b419989ed0bcf3a4 100644 (file)
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3828,7 +3828,7 @@
 {
   operands[4] = gen_rtx_REG (DImode, REGNO (operands[3]));
 }
-  [(set_attr "isa" "<VSisa>")])
+  [(set_attr "isa" "<FL_CONV:VSisa>")])
 
 (define_insn_and_split "*vsx_ext_<VSX_EXTRACT_I:VS_scalar>_ufl_<FL_CONV:mode>"
   [(set (match_operand:FL_CONV 0 "gpc_reg_operand" "=wa")
@@ -3851,7 +3851,7 @@
 {
   operands[4] = gen_rtx_REG (DImode, REGNO (operands[3]));
 }
-  [(set_attr "isa" "<VSisa>")])
+  [(set_attr "isa" "<FL_CONV:VSisa>")])
 
 ;; V4SI/V8HI/V16QI set operation on ISA 3.0
 (define_insn "vsx_set_<mode>_p9"