dev/disk_image.cc
dev/io_device.cc
dev/isa_fake.cc
+ dev/pciconfigall.cc
dev/platform.cc
dev/simconsole.cc
dev/simple_disk.cc
# dev/ide_ctrl.cc
# dev/ide_disk.cc
# dev/ns_gige.cc
-# dev/pciconfigall.cc
# dev/pcidev.cc
# dev/pcifake.cc
# dev/pktfifo.cc
}
SimpleCPU::SimpleCPU(Params *p)
-#if !FULL_SYSTEM
: BaseCPU(p), mem(p->mem), icachePort(this),
dcachePort(this), tickEvent(this, p->width), cpuXC(NULL)
-#else
- : BaseCPU(p), icachePort(this), dcachePort(this),
- tickEvent(this, p->width), cpuXC(NULL)
-#endif
{
_status = Idle;
Param<Counter> max_insts_all_threads;
Param<Counter> max_loads_any_thread;
Param<Counter> max_loads_all_threads;
+ SimObjectParam<MemObject *> mem;
#if FULL_SYSTEM
SimObjectParam<AlphaITB *> itb;
Param<int> cpu_id;
Param<Tick> profile;
#else
- SimObjectParam<MemObject *> mem;
SimObjectParam<Process *> workload;
#endif // FULL_SYSTEM
"terminate when any thread reaches this load count"),
INIT_PARAM(max_loads_all_threads,
"terminate when all threads have reached this load count"),
+ INIT_PARAM(mem, "memory"),
#if FULL_SYSTEM
INIT_PARAM(itb, "Instruction TLB"),
INIT_PARAM(cpu_id, "processor ID"),
INIT_PARAM(profile, ""),
#else
- INIT_PARAM(mem, "memory"),
INIT_PARAM(workload, "processes to run"),
#endif // FULL_SYSTEM
params->functionTrace = function_trace;
params->functionTraceStart = function_trace_start;
params->width = width;
+ params->mem = mem;
#if FULL_SYSTEM
params->itb = itb;
params->cpu_id = cpu_id;
params->profile = profile;
#else
- params->mem = mem;
params->process = workload;
#endif
struct Params : public BaseCPU::Params
{
int width;
+ MemObject *mem;
#if FULL_SYSTEM
AlphaITB *itb;
AlphaDTB *dtb;
#else
- MemObject *mem;
Process *process;
#endif
};
#include <vector>
#include "base/trace.hh"
-#include "cpu/exec_context.hh"
#include "dev/baddev.hh"
#include "dev/platform.hh"
-#include "mem/bus/bus.hh"
-#include "mem/bus/pio_interface.hh"
-#include "mem/bus/pio_interface_impl.hh"
-#include "mem/functional/memory_control.hh"
+#include "mem/port.hh"
#include "sim/builder.hh"
#include "sim/system.hh"
using namespace TheISA;
BadDevice::BadDevice(Params *p)
- : BasicPioDevice(p), devname(p->devic_ename)
+ : BasicPioDevice(p), devname(p->device_name)
{
pioSize = 0xf;
}
Param<string> devicename;
Param<Addr> pio_addr;
- SimObjectParam<AlphaSystem *> system;
+ SimObjectParam<System *> system;
SimObjectParam<Platform *> platform;
Param<Tick> pio_latency;
p->pio_addr = pio_addr;
p->pio_delay = pio_latency;
p->system = system;
- p->devicename = devicename;
+ p->device_name = devicename;
return new BadDevice(p);
}
delete pioPort;
}
+void
PioDevice::init()
{
if (!pioPort)
#define __DEV_IO_DEVICE_HH__
#include "base/chunk_generator.hh"
-#include "mem/port.hh"
+#include "mem/mem_object.hh"
#include "sim/eventq.hh"
#include "sim/sim_object.hh"
* bother.
*/
-class PioDevice : public SimObject
+class PioDevice : public MemObject
{
protected:
const Params *params() const { return _params; }
PioDevice(Params *p)
- : SimObject(params()->name), platform(p->platform), _params(p)
+ : MemObject(p->name), platform(p->platform), pioPort(NULL),
+ _params(p)
{}
virtual ~PioDevice();
/** return the address ranges that this device responds to.
* @params range_list range list to populate with ranges
*/
- addressRanges(AddrRangeList &range_list);
+ void addressRanges(AddrRangeList &range_list);
};
#include <string>
#include <vector>
-#include "arch/alpha/ev5.hh"
#include "base/trace.hh"
-#include "cpu/exec_context.hh"
-#include "dev/tsunami_fake.hh"
-#include "mem/bus/bus.hh"
-#include "mem/bus/pio_interface.hh"
-#include "mem/bus/pio_interface_impl.hh"
-#include "mem/functional/memory_control.hh"
+#include "dev/isa_fake.hh"
+#include "mem/packet.hh"
#include "sim/builder.hh"
#include "sim/system.hh"
assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
pkt.time = curTick + pioDelay;
- Addr daddr = pkt.addr - pioAddr;
DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt.addr, pkt.size);
uint32_t *data32;
uint64_t *data64;
- switch (req->size) {
+ switch (pkt.size) {
case sizeof(uint64_t):
if (!pkt.data) {
data64 = new uint64_t;
data32 = new uint32_t;
pkt.data = (uint8_t*)data32;
} else {
- data32 = (uint64_t*)pkt.data;
+ data32 = (uint32_t*)pkt.data;
}
*data32 = 0xFFFFFFFF;
break;
data16 = new uint16_t;
pkt.data = (uint8_t*)data16;
} else {
- data16 = (uint64_t*)pkt.data;
+ data16 = (uint16_t*)pkt.data;
}
*data16 = 0xFFFF;
break;
return pioDelay;
}
-Fault
+Tick
IsaFake::write(Packet &pkt)
{
pkt.time = curTick + pioDelay;
#include <vector>
#include <bitset>
-#include "arch/alpha/ev5.hh"
#include "base/trace.hh"
#include "dev/pciconfigall.hh"
-#include "dev/pcidev.hh"
+//#include "dev/pcidev.hh"
#include "dev/pcireg.h"
-#include "mem/bus/bus.hh"
-#include "mem/bus/pio_interface.hh"
-#include "mem/bus/pio_interface_impl.hh"
-#include "mem/functional/memory_control.hh"
+#include "dev/platform.hh"
+#include "mem/packet.hh"
#include "sim/builder.hh"
#include "sim/system.hh"
using namespace std;
-using namespace TheISA;
-PciConfigAll::PciConfigAll(const string &name,
- Addr a, MemoryController *mmu,
- HierParams *hier, Bus *pio_bus, Tick pio_latency)
- : PioDevice(name, NULL), addr(a)
+PciConfigAll::PciConfigAll(Params *p)
+ : BasicPioDevice(p)
{
- mmu->add_child(this, RangeSize(addr, size));
+ pioSize = 0xffffff;
- if (pio_bus) {
- pioInterface = newPioInterface(name + ".pio", hier, pio_bus, this,
- &PciConfigAll::cacheAccess);
- pioInterface->addAddrRange(RangeSize(addr, size));
- pioLatency = pio_latency * pio_bus->clockRate;
- }
+ // Set backpointer for pci config. Really the config stuff should be able to
+ // automagically do this
+ p->platform->pciconfig = this;
// Make all the pointers to devices null
for(int x=0; x < MAX_PCI_DEV; x++)
void
PciConfigAll::startup()
{
- bitset<256> intLines;
+/* bitset<256> intLines;
PciDev *tempDev;
uint8_t intline;
} // devices != NULL
} // PCI_FUNC
} // PCI_DEV
-
+ */
}
-Fault
-PciConfigAll::read(MemReqPtr &req, uint8_t *data)
+Tick
+PciConfigAll::read(Packet &pkt)
{
+ assert(pkt.result == Unknown);
+ assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
- Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask));
-
- DPRINTF(PciConfigAll, "read va=%#x da=%#x size=%d\n",
- req->vaddr, daddr, req->size);
-
+ Addr daddr = pkt.addr - pioAddr;
int device = (daddr >> 11) & 0x1F;
int func = (daddr >> 8) & 0x7;
- int reg = daddr & 0xFF;
-
- if (devices[device][func] == NULL) {
- switch (req->size) {
- // case sizeof(uint64_t):
- // *(uint64_t*)data = 0xFFFFFFFFFFFFFFFF;
- // return NoFault;
- case sizeof(uint32_t):
- *(uint32_t*)data = 0xFFFFFFFF;
- return NoFault;
- case sizeof(uint16_t):
- *(uint16_t*)data = 0xFFFF;
- return NoFault;
- case sizeof(uint8_t):
- *(uint8_t*)data = 0xFF;
- return NoFault;
- default:
- panic("invalid access size(?) for PCI configspace!\n");
- }
- } else {
- switch (req->size) {
- case sizeof(uint32_t):
- case sizeof(uint16_t):
- case sizeof(uint8_t):
- devices[device][func]->readConfig(reg, req->size, data);
- return NoFault;
- default:
- panic("invalid access size(?) for PCI configspace!\n");
- }
+ //int reg = daddr & 0xFF;
+
+ pkt.time = curTick + pioDelay;
+
+ DPRINTF(PciConfigAll, "read va=%#x da=%#x size=%d\n", pkt.addr, daddr,
+ pkt.size);
+
+ uint8_t *data8;
+ uint16_t *data16;
+ uint32_t *data32;
+
+ switch (pkt.size) {
+/* case sizeof(uint64_t):
+ if (!pkt.data) {
+ data64 = new uint64_t;
+ pkt.data = (uint8_t*)data64;
+ } else {
+ data64 = (uint64_t*)pkt.data;
+ }
+ if (devices[device][func] == NULL)
+ *data64 = 0xFFFFFFFFFFFFFFFFULL;
+ else
+ devices[device][func]->readConfig(reg, req.size, data64);
+ break;*/
+ case sizeof(uint32_t):
+ if (!pkt.data) {
+ data32 = new uint32_t;
+ pkt.data = (uint8_t*)data32;
+ } else {
+ data32 = (uint32_t*)pkt.data;
+ }
+ if (devices[device][func] == NULL)
+ *data32 = 0xFFFFFFFF;
+ else
+ ;//devices[device][func]->readConfig(reg, req.size, data32);
+ break;
+ case sizeof(uint16_t):
+ if (!pkt.data) {
+ data16 = new uint16_t;
+ pkt.data = (uint8_t*)data16;
+ } else {
+ data16 = (uint16_t*)pkt.data;
+ }
+ if (devices[device][func] == NULL)
+ *data16 = 0xFFFF;
+ else
+ ;//devices[device][func]->readConfig(reg, req.size, data16);
+ break;
+ case sizeof(uint8_t):
+ if (!pkt.data) {
+ data8 = new uint8_t;
+ pkt.data = data8;
+ } else {
+ data8 = (uint8_t*)pkt.data;
+ }
+ if (devices[device][func] == NULL)
+ *data8 = 0xFF;
+ else
+ ;//devices[device][func]->readConfig(reg, req.size, data8);
+ break;
+ default:
+ panic("invalid access size(?) for PCI configspace!\n");
}
-
- DPRINTFN("PCI Configspace ERROR: read daddr=%#x size=%d\n",
- daddr, req->size);
-
- return NoFault;
+ pkt.result = Success;
+ return pioDelay;
}
-Fault
-PciConfigAll::write(MemReqPtr &req, const uint8_t *data)
+Tick
+PciConfigAll::write(Packet &pkt)
{
- Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask));
+ pkt.time = curTick + pioDelay;
+
+ assert(pkt.result == Unknown);
+ assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
+ assert(pkt.size == sizeof(uint8_t) || pkt.size == sizeof(uint16_t) ||
+ pkt.size == sizeof(uint32_t));
+ Addr daddr = pkt.addr - pioAddr;
int device = (daddr >> 11) & 0x1F;
int func = (daddr >> 8) & 0x7;
- int reg = daddr & 0xFF;
+// int reg = daddr & 0xFF;
if (devices[device][func] == NULL)
panic("Attempting to write to config space on non-existant device\n");
- else if (req->size != sizeof(uint8_t) &&
- req->size != sizeof(uint16_t) &&
- req->size != sizeof(uint32_t))
- panic("invalid access size(?) for PCI configspace!\n");
DPRINTF(PciConfigAll, "write - va=%#x size=%d data=%#x\n",
- req->vaddr, req->size, *(uint32_t*)data);
+ pkt.addr, pkt.size, *(uint32_t*)pkt.data);
- devices[device][func]->writeConfig(reg, req->size, data);
+// devices[device][func]->writeConfig(reg, req->size, data);
- return NoFault;
+ return pioDelay;
}
void
*/
}
-Tick
-PciConfigAll::cacheAccess(MemReqPtr &req)
-{
- return curTick + pioLatency;
-}
-
#ifndef DOXYGEN_SHOULD_SKIP_THIS
BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll)
- SimObjectParam<MemoryController *> mmu;
- Param<Addr> addr;
- Param<Addr> mask;
- SimObjectParam<Bus*> pio_bus;
+ Param<Addr> pio_addr;
Param<Tick> pio_latency;
- SimObjectParam<HierParams *> hier;
+ SimObjectParam<Platform *> platform;
+ SimObjectParam<System *> system;
END_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll)
BEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigAll)
- INIT_PARAM(mmu, "Memory Controller"),
- INIT_PARAM(addr, "Device Address"),
- INIT_PARAM(mask, "Address Mask"),
- INIT_PARAM_DFLT(pio_bus, "The IO Bus to attach to", NULL),
- INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
- INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
+ INIT_PARAM(pio_addr, "Device Address"),
+ INIT_PARAM(pio_latency, "Programmed IO latency"),
+ INIT_PARAM(platform, "platform"),
+ INIT_PARAM(system, "system object")
END_INIT_SIM_OBJECT_PARAMS(PciConfigAll)
CREATE_SIM_OBJECT(PciConfigAll)
{
- return new PciConfigAll(getInstanceName(), addr, mmu, hier, pio_bus,
- pio_latency);
+ BasicPioDevice::Params *p = new BasicPioDevice::Params;
+ p->pio_addr = pio_addr;
+ p->pio_delay = pio_latency;
+ p->platform = platform;
+ p->system = system;
+ return new PciConfigAll(p);
}
REGISTER_SIM_OBJECT("PciConfigAll", PciConfigAll)
static const uint32_t MAX_PCI_FUNC = 8;
class PciDev;
-class MemoryController;
/**
* PCI Config Space
* space and passes the requests on to TsunamiPCIDev devices as
* appropriate.
*/
-class PciConfigAll : public PioDevice
+class PciConfigAll : public BasicPioDevice
{
private:
- Addr addr;
static const Addr size = 0xffffff;
/**
public:
/**
* Constructor for PCIConfigAll
- * @param name name of the object
- * @param a base address of the write
- * @param mmu the memory controller
- * @param hier object to store parameters universal the device hierarchy
- * @param bus The bus that this device is attached to
+ * @param p parameters structure
*/
- PciConfigAll(const std::string &name, Addr a, MemoryController *mmu,
- HierParams *hier, Bus *pio_bus, Tick pio_latency);
-
+ PciConfigAll(Params *p);
/**
* Check if a device exists.
* Read something in PCI config space. If the device does not exist
* -1 is returned, if the device does exist its PciDev::ReadConfig (or the
* virtual function that overrides) it is called.
- * @param req Contains the address of the field to read.
- * @param data Return the field read.
- * @return The fault condition of the access.
+ * @param pkt Contains the address of the field to read.
+ * @return Amount of time to do the read
*/
- virtual Fault read(MemReqPtr &req, uint8_t *data);
+ virtual Tick read(Packet &pkt);
/**
* Write to PCI config spcae. If the device does not exit the simulator
* @return The fault condition of the access.
*/
- virtual Fault write(MemReqPtr &req, const uint8_t *data);
+ virtual Tick write(Packet &pkt);
/**
* Start up function to check if more than one person is using an interrupt line
* @param section The section name of this object
*/
virtual void unserialize(Checkpoint *cp, const std::string §ion);
-
- /**
- * Return how long this access will take.
- * @param req the memory request to calcuate
- * @return Tick when the request is done
- */
- Tick cacheAccess(MemReqPtr &req);
-
};
#endif // __PCICONFIGALL_HH__
using namespace std;
using namespace TheISA;
-Platform::Platform(const string &name, IntrControl *intctrl, PciConfigAll *pci)
- : SimObject(name), intrctrl(intctrl), pciconfig(pci)
+Platform::Platform(const string &name, IntrControl *intctrl)
+ : SimObject(name), intrctrl(intctrl)
{
}
System *system;
public:
- Platform(const std::string &name, IntrControl *intctrl, PciConfigAll *pci);
+ Platform(const std::string &name, IntrControl *intctrl);
virtual ~Platform();
+ virtual void init() { if (pciconfig == NULL) panic("PCI Config not set"); }
virtual void postConsoleInt() = 0;
virtual void clearConsoleInt() = 0;
virtual Tick intrFrequency() = 0;
#include "cpu/intr_control.hh"
#include "dev/simconsole.hh"
-#include "dev/ide_ctrl.hh"
#include "dev/tsunami_cchip.hh"
#include "dev/tsunami_pchip.hh"
#include "dev/tsunami_io.hh"
#include "dev/tsunami.hh"
-#include "dev/pciconfigall.hh"
#include "sim/builder.hh"
#include "sim/system.hh"
//Should this be AlphaISA?
using namespace TheISA;
-Tsunami::Tsunami(const string &name, System *s, IntrControl *ic,
- PciConfigAll *pci)
- : Platform(name, ic, pci), system(s)
+Tsunami::Tsunami(const string &name, System *s, IntrControl *ic)
+ : Platform(name, ic), system(s)
{
// set the back pointer from the system to myself
system->platform = this;
SimObjectParam<System *> system;
SimObjectParam<IntrControl *> intrctrl;
- SimObjectParam<PciConfigAll *> pciconfig;
END_DECLARE_SIM_OBJECT_PARAMS(Tsunami)
BEGIN_INIT_SIM_OBJECT_PARAMS(Tsunami)
INIT_PARAM(system, "system"),
- INIT_PARAM(intrctrl, "interrupt controller"),
- INIT_PARAM(pciconfig, "PCI configuration")
+ INIT_PARAM(intrctrl, "interrupt controller")
END_INIT_SIM_OBJECT_PARAMS(Tsunami)
CREATE_SIM_OBJECT(Tsunami)
{
- return new Tsunami(getInstanceName(), system, intrctrl, pciconfig);
+ return new Tsunami(getInstanceName(), system, intrctrl);
}
REGISTER_SIM_OBJECT("Tsunami", Tsunami)
#include "dev/platform.hh"
class IdeController;
-class TlaserClock;
-class NSGigE;
class TsunamiCChip;
class TsunamiPChip;
class TsunamiIO;
-class PciConfigAll;
class System;
/**
* @param name name of the object
* @param intrctrl pointer to the interrupt controller
*/
- Tsunami(const std::string &name, System *s, IntrControl *intctrl,
- PciConfigAll *pci);
+ Tsunami(const std::string &name, System *s, IntrControl *intctrl);
/**
* Return the interrupting frequency to AlphaAccess
Tick
TsunamiCChip::read(Packet &pkt)
{
- DPRINTF(Tsunami, "read va=%#x size=%d\n", req->vaddr, req->size);
+ DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt.addr, pkt.size);
assert(pkt.result == Unknown);
assert(pkt.addr > pioAddr && pkt.addr < pioAddr + pioSize);
pkt.time = curTick + pioDelay;
- Addr regnum = (req->paddr - pioAddr) >> 6;
- Addr daddr = (req->paddr - pioAddr);
+ Addr regnum = (pkt.addr - pioAddr) >> 6;
+ Addr daddr = (pkt.addr - pioAddr);
- uint32_t *data32;
uint64_t *data64;
switch (pkt.size) {
break;
case TSDEV_CC_MISC:
*data64 = (ipint << 8) & 0xF | (itint << 4) & 0xF |
- (pkt.req->cpuId & 0x3);
+ (pkt.req->getCpuNum() & 0x3);
break;
case TSDEV_CC_AAR0:
case TSDEV_CC_AAR1:
panic("invalid access size(?) for tsunami register!\n");
}
DPRINTFN("Tsunami CChip: read regnum=%#x size=%d data=%lld\n", regnum,
- req->size, *data);
+ pkt.size, *data64);
pkt.result = Success;
return pioDelay;
uint64_t val = *(uint64_t *)pkt.data;
assert(pkt.size == sizeof(uint64_t));
- DPRINTF(Tsunami, "write - addr=%#x value=%#x\n", req->addr, val);
+ DPRINTF(Tsunami, "write - addr=%#x value=%#x\n", pkt.addr, val);
bool supportedWrite = false;
case TSDEV_CC_AAR2:
case TSDEV_CC_AAR3:
panic("TSDEV_CC_AARx write not implemeted\n");
- return NoFault;
case TSDEV_CC_DIM0:
case TSDEV_CC_DIM1:
case TSDEV_CC_DIM2:
DPRINTF(Tsunami, "Spurrious clear? interrupt %d\n", interrupt);
}
-Tick
-TsunamiCChip::cacheAccess(MemReqPtr &req)
-{
- return curTick + pioLatency;
-}
-
void
TsunamiCChip::serialize(std::ostream &os)
#include <string>
#include <vector>
-#include "arch/alpha/ev5.hh"
#include "base/trace.hh"
-#include "dev/tsunami_io.hh"
-#include "dev/tsunami.hh"
#include "dev/pitreg.h"
-#include "mem/bus/port.hh"
-#include "sim/builder.hh"
+#include "dev/rtcreg.h"
#include "dev/tsunami_cchip.hh"
+#include "dev/tsunami.hh"
+#include "dev/tsunami_io.hh"
#include "dev/tsunamireg.h"
-#include "dev/rtcreg.h"
+#include "mem/port.hh"
+#include "sim/builder.hh"
+#include "sim/system.hh"
using namespace std;
//Should this be AlphaISA?
void
TsunamiIO::RTC::writeAddr(const uint8_t data)
{
- if (*data <= RTC_STAT_REGD)
+ if (data <= RTC_STAT_REGD)
addr = data;
else
panic("RTC addresses over 0xD are not implemented.\n");
case RTC_STAT_REGA:
if (data != (RTCA_32768HZ | RTCA_1024HZ))
panic("Unimplemented RTC register A value write!\n");
- stat_regA = *data;
+ stat_regA = data;
break;
case RTC_STAT_REGB:
if ((data & ~(RTCB_PRDC_IE | RTCB_SQWE)) != (RTCB_BIN | RTCB_24HR))
panic("Write to RTC reg B bits that are not implemented!\n");
- if (*data & RTCB_PRDC_IE) {
+ if (data & RTCB_PRDC_IE) {
if (!event.scheduled())
event.scheduleIntr();
} else {
if (sel == PIT_READ_BACK)
panic("PITimer Read-Back Command is not implemented.\n");
- rw = GET_CTRL_RW(*data);
+ rw = GET_CTRL_RW(data);
if (rw == PIT_RW_LATCH_COMMAND)
counter[sel]->latchCount();
TsunamiIO::TsunamiIO(Params *p)
: BasicPioDevice(p), tsunami(p->tsunami), pitimer(p->name + "pitimer"),
- rtc(name + ".rtc", p->tsunami, p->frequency)
+ rtc(p->name + ".rtc", p->tsunami, p->frequency)
{
pioSize = 0xff;
tsunami->io = this;
timerData = 0;
- rtc.set_time(p->init_time == 0 ? time(NULL) : init_time);
+ rtc.set_time(p->init_time == 0 ? time(NULL) : p->init_time);
picr = 0;
picInterrupting = false;
}
return Clock::Frequency / params()->frequency;
}
-Fault
+Tick
TsunamiIO::read(Packet &pkt)
{
assert(pkt.result == Unknown);
break;
case TSDEV_TMR0_DATA:
pitimer.counter0.read(data8);
- return NoFault;
+ break;
case TSDEV_TMR1_DATA:
pitimer.counter1.read(data8);
- return NoFault;
+ break;
case TSDEV_TMR2_DATA:
pitimer.counter2.read(data8);
break;
data64 = new uint64_t;
pkt.data = (uint8_t*)data64;
} else
- data8 = (uint64_t*)pkt.data;
+ data64 = (uint64_t*)pkt.data;
if (daddr == TSDEV_PIC1_ISR)
- data64 = (uint64_t)picr;
+ *data64 = picr;
else
panic("I/O Read - invalid addr - va %#x size %d\n",
- req.addr, req.size);
+ pkt.addr, pkt.size);
} else {
- panic("I/O Read - invalid size - va %#x size %d\n", req.addr, req.size);
+ panic("I/O Read - invalid size - va %#x size %d\n", pkt.addr, pkt.size);
}
pkt.result = Success;
return pioDelay;
#endif
DPRINTF(Tsunami, "io write - va=%#x size=%d IOPort=%#x Data=%#x\n",
- req->vaddr, req->size, req->vaddr & 0xfff, dt64);
+ pkt.addr, pkt.size, pkt.addr & 0xfff, dt64);
assert(pkt.size == sizeof(uint8_t));
BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiIO)
- INIT_PARAM(frequency, "clock interrupt frequency"),
INIT_PARAM(pio_addr, "Device Address"),
INIT_PARAM(pio_latency, "Programmed IO latency"),
- INIT_PARAM(pio_size, "Size of address range"),
+ INIT_PARAM(frequency, "clock interrupt frequency"),
INIT_PARAM(platform, "platform"),
INIT_PARAM(system, "system object"),
INIT_PARAM(time, "System time to use (0 for actual time"),
* Tsunami I/O device is a catch all for all the south bridge stuff we care
* to implement.
*/
-class TsunamiIO : public PioDevice
+class TsunamiIO : public BasicPioDevice
{
private:
struct tm tm;
*/
TsunamiIO(Params *p);
- virtual Fault read(Packet &pkt);
- virtual Fault write(Packet &pkt);
+ virtual Tick read(Packet &pkt);
+ virtual Tick write(Packet &pkt);
/**
* Post an PIC interrupt to the CPU via the CChip
#include <string>
#include <vector>
-#include "arch/alpha/ev5.hh"
#include "base/trace.hh"
#include "dev/tsunami_pchip.hh"
#include "dev/tsunamireg.h"
#include "dev/tsunami.hh"
-#include "mem/bus/bus.hh"
-#include "mem/bus/pio_interface.hh"
-#include "mem/bus/pio_interface_impl.hh"
-#include "mem/functional/memory_control.hh"
-#include "mem/functional/physical.hh"
+#include "mem/packet.hh"
#include "sim/builder.hh"
#include "sim/system.hh"
using namespace TheISA;
TsunamiPChip::TsunamiPChip(Params *p)
-: BasicPioDevice(p),
+: BasicPioDevice(p)
{
pioSize = 0xfff;
case TSDEV_PC_TBA2:
*data64 = tba[2];
break;
- case Tbreak;
+ case TSDEV_PC_TBA3:
*data64 = tba[3];
break;
case TSDEV_PC_PCTL:
}
-Fault
+Tick
TsunamiPChip::write(Packet &pkt)
{
pkt.time = curTick + pioDelay;
assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
Addr daddr = pkt.addr - pioAddr;
- uint64_t val = *(uint64_t *)pkt.data;
+ uint64_t data64 = *(uint64_t *)pkt.data;
assert(pkt.size == sizeof(uint64_t));
DPRINTF(Tsunami, "write - va=%#x size=%d \n", pkt.addr, pkt.size);
baMask = (wsm[i] & (ULL(0xfff) << 20)) | (ULL(0x7f) << 13);
pteAddr = (tba[i] & tbaMask) | ((busAddr & baMask) >> 10);
- pioPort->readBlob(&pteEntry, pteAddr, sizeof(uint64_t));
+ pioPort->readBlob(pteAddr, (uint8_t*)&pteEntry, sizeof(uint64_t));
dmaAddr = ((pteEntry & ~ULL(0x1)) << 12) | (busAddr & ULL(0x1fff));
UNSERIALIZE_ARRAY(tba, 4);
}
-Tick
-TsunamiPChip::cacheAccess(MemReqPtr &req)
-{
- return curTick + pioLatency;
-}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
*/
Addr translatePciToDma(Addr busAddr);
- virtual Fault read(Packet &pkt);
- virtual Fault write(Packet &pkt);
+ virtual Tick read(Packet &pkt);
+ virtual Tick write(Packet &pkt);
/**
* Serialize this object to the given output stream.
BEGIN_DECLARE_SIM_OBJECT_PARAMS(Uart8250)
- Param<Addr> addr;
+ Param<Addr> pio_addr;
Param<Tick> pio_latency;
SimObjectParam<Platform *> platform;
SimObjectParam<SimConsole *> sim_console;
BEGIN_INIT_SIM_OBJECT_PARAMS(Uart8250)
- INIT_PARAM(addr, "Device Address"),
+ INIT_PARAM(pio_addr, "Device Address"),
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency", 1000),
INIT_PARAM(platform, "platform"),
INIT_PARAM(sim_console, "The Simulator Console"),
{
Uart8250::Params *p = new Uart8250::Params;
p->name = getInstanceName();
- p->pio_addr = addr;
+ p->pio_addr = pio_addr;
p->pio_delay = pio_latency;
p->platform = platform;
p->cons = sim_console;
from m5 import *
-from Device import PioDevice
+from Device import BasicPioDevice
-class AlphaConsole(PioDevice):
+class AlphaConsole(BasicPioDevice):
type = 'AlphaConsole'
cpu = Param.BaseCPU(Parent.any, "Processor")
disk = Param.SimpleDisk("Simple Disk")
sim_console = Param.SimConsole(Parent.any, "The Simulator Console")
- system = Param.System(Parent.any, "system object")
+ system = Param.AlphaSystem(Parent.any, "system object")
from m5 import *
-from Device import PioDevice
+from Device import BasicPioDevice
-class BadDevice(PioDevice):
+class BadDevice(BasicPioDevice):
type = 'BadDevice'
devicename = Param.String("Name of device to error on")
class BaseCPU(SimObject):
type = 'BaseCPU'
abstract = True
+ mem = Param.MemObject("memory")
if build_env['FULL_SYSTEM']:
dtb = Param.AlphaDTB("Data TLB")
system = Param.System(Parent.any, "system object")
cpu_id = Param.Int(-1, "CPU identifier")
else:
- mem = Param.MemObject("memory")
workload = VectorParam.Process("processes to run")
max_insts_all_threads = Param.Counter(0,
from m5 import *
-from FunctionalMemory import FunctionalMemory
+from MemObject import MemObject
-# This device exists only because there are some devices that I don't
-# want to have a Platform parameter because it would cause a cycle in
-# the C++ that cannot be easily solved.
-#
-# The real solution to this problem is to pass the ParamXXX structure
-# to the constructor, but with the express condition that SimObject
-# parameter values are not to be available at construction time. If
-# some further configuration must be done, it must be done during the
-# initialization phase at which point all SimObject pointers will be
-# valid.
-class FooPioDevice(FunctionalMemory):
+class PioDevice(MemObject):
type = 'PioDevice'
abstract = True
- addr = Param.Addr("Device Address")
- mmu = Param.MemoryController(Parent.any, "Memory Controller")
- pio_bus = Param.Bus(NULL, "Bus to attach to for PIO")
- pio_latency = Param.Tick(1, "Programmed IO latency in bus cycles")
+ platform = Param.Platform(Parent.any, "Platform this device is part of")
+ system = Param.System(Parent.any, "System this device is part of")
-class FooDmaDevice(FooPioDevice):
- type = 'DmaDevice'
+class BasicPioDevice(PioDevice):
+ type = 'BasicPioDevice'
abstract = True
- dma_bus = Param.Bus(Self.pio_bus, "Bus to attach to for DMA")
-
-class PioDevice(FooPioDevice):
- type = 'PioDevice'
- abstract = True
- platform = Param.Platform(Parent.any, "Platform")
-
-class DmaDevice(PioDevice):
- type = 'DmaDevice'
- abstract = True
- dma_bus = Param.Bus(Self.pio_bus, "Bus to attach to for DMA")
+ pio_addr = Param.Addr("Device Address")
+ pio_latency = Param.Tick(1, "Programmed IO latency in simticks")
from m5 import *
-from Device import FooPioDevice, DmaDevice
+from Device import BasicPioDevice
+#, DmaDevice
class PciConfigData(SimObject):
type = 'PciConfigData'
MaximumLatency = Param.UInt8(0x00, "Maximum Latency")
MinimumGrant = Param.UInt8(0x00, "Minimum Grant")
-class PciConfigAll(FooPioDevice):
+class PciConfigAll(BasicPioDevice):
type = 'PciConfigAll'
-class PciDevice(DmaDevice):
- type = 'PciDevice'
- abstract = True
- addr = 0xffffffffL
- pci_bus = Param.Int("PCI bus")
- pci_dev = Param.Int("PCI device number")
- pci_func = Param.Int("PCI function code")
- configdata = Param.PciConfigData(Parent.any, "PCI Config data")
- configspace = Param.PciConfigAll(Parent.any, "PCI Configspace")
-
-class PciFake(PciDevice):
- type = 'PciFake'
+#class PciDevice(DmaDevice):
+# type = 'PciDevice'
+# abstract = True
+# addr = 0xffffffffL
+# pci_bus = Param.Int("PCI bus")
+# pci_dev = Param.Int("PCI device number")
+# pci_func = Param.Int("PCI function code")
+# configdata = Param.PciConfigData(Parent.any, "PCI Config data")
+# configspace = Param.PciConfigAll(Parent.any, "PCI Configspace")
+#
+#class PciFake(PciDevice):
+# type = 'PciFake'
type = 'PhysicalMemory'
range = Param.AddrRange("Device Address")
file = Param.String('', "memory mapped file")
- if build_env['FULL_SYSTEM']:
- mmu = Param.MemoryController(Parent.any, "Memory Controller")
if build_env['FULL_SYSTEM']:
boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency,
"boot processor frequency")
- memctrl = Param.MemoryController(Parent.any, "memory controller")
init_param = Param.UInt64(0, "numerical value to pass into simulator")
bin = Param.Bool(False, "is this system binned")
binned_fns = VectorParam.String([], "functions broken down and binned")
from m5 import *
-from Device import FooPioDevice
+from Device import BasicPioDevice
from Platform import Platform
class Tsunami(Platform):
type = 'Tsunami'
- pciconfig = Param.PciConfigAll("PCI configuration")
+# pciconfig = Param.PciConfigAll("PCI configuration")
system = Param.System(Parent.any, "system")
-class TsunamiCChip(FooPioDevice):
+class TsunamiCChip(BasicPioDevice):
type = 'TsunamiCChip'
tsunami = Param.Tsunami(Parent.any, "Tsunami")
-class IsaFake(FooPioDevice):
+class IsaFake(BasicPioDevice):
type = 'IsaFake'
- size = Param.Addr("Size of address range")
+ pio_size = Param.Addr(0x8, "Size of address range")
-class TsunamiIO(FooPioDevice):
+class TsunamiIO(BasicPioDevice):
type = 'TsunamiIO'
time = Param.UInt64(1136073600,
"System time to use (0 for actual time, default is 1/1/06)")
tsunami = Param.Tsunami(Parent.any, "Tsunami")
frequency = Param.Frequency('1024Hz', "frequency of interrupts")
-class TsunamiPChip(FooPioDevice):
+class TsunamiPChip(BasicPioDevice):
type = 'TsunamiPChip'
tsunami = Param.Tsunami(Parent.any, "Tsunami")
from m5 import *
-from Device import PioDevice
+from Device import BasicPioDevice
-class Uart(PioDevice):
+class Uart(BasicPioDevice):
type = 'Uart'
abstract = True
- console = Param.SimConsole(Parent.any, "The console")
- size = Param.Addr(0x8, "Device size")
+ sim_console = Param.SimConsole(Parent.any, "The console")
class Uart8250(Uart):
type = 'Uart8250'
projects / gem5.git / commitdiff