2001-10-28 Joseph S. Myers <jsm28@cam.ac.uk>
+ * config/alpha/alpha.md, config/arm/arm.c, config/arm/arm.h,
+ config/d30v/d30v.h, config/fr30/fr30.c, config/i370/x-oe,
+ config/i386/i386.c, config/i386/i386-interix.h,
+ config/i386/i386.md, config/i386/i386.h, config/i386/sco5.h,
+ config/i860/i860.h, config/i860/i860.md, config/m68k/aux-exit.c,
+ config/m68k/m68k.c, config/mcore/mcore.c, config/mips/mips.md,
+ config/ns32k/ns32k.h, config/pa/pa.c, config/rs6000/rs6000.c,
+ config/sparc/sparc.c, config/m68hc11/m68hc11.c,
+ config/cris/cris.c, config/cris/cris.h, config/s390/s390.c,
+ config/s390/s390.h, config/stormy16/stormy16.h, doc/tm.texi: Fix
+ spelling errors.
+
* ChangeLog.0, ChangeLog.1, ChangeLog.2, ChangeLog.3, ChangeLog.4,
ChangeLog.5, ChangeLog, ChangeLog.lib, FSFChangeLog.10, ONEWS,
c-common.c, caller-save.c, cfg.c, cfgcleanup.c, cfgrtl.c,
;; EV6 has two symmetric pairs ("clusters") of two asymetric integer units
;; ("upper" and "lower"), yielding pipe names U0, U1, L0, L1.
-;; Conditional moves decompose into two independant primitives, each
+;; Conditional moves decompose into two independent primitives, each
;; taking one cycle. Since ev6 is out-of-order, we can't see anything
;; but two cycles.
(define_function_unit "ev6_ebox" 4 0
/* Return 1 if OP is a valid memory address, but not valid for a signed byte
memory access (architecture V4).
- MODE is QImode if called when computing contraints, or VOIDmode when
+ MODE is QImode if called when computing constraints, or VOIDmode when
emitting patterns. In this latter case we cannot use memory_operand()
because it will fail on badly formed MEMs, which is precisly what we are
trying to catch. */
/* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
value set in previous versions of this toolchain was 8, which produces more
compact structures. The command line option -mstructure_size_boundary=<n>
- can be used to change this value. For compatability with the ARM SDK
+ can be used to change this value. For compatibility with the ARM SDK
however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
0020D) page 2-20 says "Structures are aligned on word boundaries". */
#define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
{
int regno;
- /* Initial offset is 0 if we dont have a frame pointer. */
+ /* Initial offset is 0 if we don't have a frame pointer. */
int offs = 0;
/* And 4 for each register pushed. */
/* Node: Allocation Order */
/* We need this on CRIS, because call-used regs should be used first,
- (so we dont need to push). Else start using registers from r0 and up.
+ (so we don't need to push). Else start using registers from r0 and up.
This preference is mainly because if we put call-used-regs from r0
and up, then we can't use movem to push the rest, (which have to be
saved if we use them, and movem has to start with r0).
/* Some stabs encapsulation formats (in particular ECOFF), cannot
handle the `.stabs "",N_FUN,,0,0,Lscope-function-1' gdb dbx
- extention construct. On those machines, define this macro to turn
+ extension construct. On those machines, define this macro to turn
this feature off without disturbing the rest of the gdb extensions. */
/* #define NO_DBX_FUNCTION_END */
}
}
else
- /* This should have been prevented by the contraints on movdi_insn. */
+ /* This should have been prevented by the constraints on movdi_insn. */
abort ();
val = gen_sequence ();
# Host is an i370 running OpenEdition
#
-# Don't bother fixing up header files, they're wierd
+# Don't bother fixing up header files, they're weird
STMP_FIXPROTO =
/* By default, target has a 80387, uses IEEE compatible arithmetic,
and returns float values in the 387 and needs stack probes
- We also align doubles to 64-bits for MSVC default compatability */
+ We also align doubles to 64-bits for MSVC default compatibility */
#undef TARGET_SUBTARGET_DEFAULT
#define TARGET_SUBTARGET_DEFAULT \
(MASK_80387 | MASK_IEEE_FP | MASK_FLOAT_RETURNS | MASK_STACK_PROBE | \
}
/* x86-64 register passing impleemntation. See x86-64 ABI for details. Goal
- of this code is to classify each 8bytes of incomming argument by the register
+ of this code is to classify each 8bytes of incoming argument by the register
class and assign registers accordingly. */
/* Return the union class of CLASS1 and CLASS2.
/* Do some sanity checking of stack_alignment_needed and
preferred_alignment, since i386 port is the only using those features
- that may break easilly. */
+ that may break easily. */
if (size && !stack_alignment_needed)
abort ();
This code is nonsensical, but results in addressing
GOT table with pic_offset_table_rtx base. We can't
- just refuse it easilly, since it gets matched by
+ just refuse it easily, since it gets matched by
"addsi3" pattern, that later gets split to lea in the
case output register differs from input. While this
can be handled by separate addsi pattern for this case
}
/* Store OPERAND to the memory after reload is completed. This means
- that we can't easilly use assign_stack_local. */
+ that we can't easily use assign_stack_local. */
rtx
ix86_force_to_memory (mode, operand)
enum machine_mode mode;
stored in a register. This macro is only called when TYPE is a
scalar type.
- On i386 it is sometimes usefull to promote HImode and QImode
+ On i386 it is sometimes useful to promote HImode and QImode
quantities to SImode. The choice depends on target type. */
#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
(eq_attr "athlon_fpunits" "store"))
1 1)
-;; We don't need to model the Adress Generation Unit, since we don't model
+;; We don't need to model the Address Generation Unit, since we don't model
;; the re-order buffer yet and thus we never schedule more than three operations
;; at time. Later we may want to experiment with MD_SCHED macros modeling the
;; decoders independently on the functional units.
#undef INIT_SECTION_ASM_OP
#define INIT_SECTION_ASM_OP_ELF "\t.section\t.init"
-/* Rename these for COFF becuase crt1.o will try to run them. */
+/* Rename these for COFF because crt1.o will try to run them. */
#define INIT_SECTION_ASM_OP_COFF "\t.section\t.ctor ,\"x\""
#define INIT_SECTION_ASM_OP \
((TARGET_ELF) ? INIT_SECTION_ASM_OP_ELF : INIT_SECTION_ASM_OP_COFF)
#if USE_GAS
/* Leave ASM_SPEC undefined so we pick up the master copy from gcc.c
- * Undef MD_EXEC_PREFIX becuase we don't know where GAS is, but it's not
+ * Undef MD_EXEC_PREFIX because we don't know where GAS is, but it's not
* likely in /usr/ccs/bin/
*/
#undef MD_EXEC_PREFIX
when given unaligned data. */
#define STRICT_ALIGNMENT 1
-/* If bit field type is int, dont let it cross an int,
+/* If bit field type is int, don't let it cross an int,
and give entire struct the alignment of an int. */
#define PCC_BITFIELD_TYPE_MATTERS 1
\f
;; Recognize the first insn generated above.
;; This RTL looks like a fix_truncdfdi2 insn,
-;; but we dont call it that, because only 32 bits
+;; but we don't call it that, because only 32 bits
;; of the result are valid.
;; This pattern will work for the intended purposes
;; as long as we do not have any fixdfdi2 or fix_truncdfdi2.
;; Recognize the first insn generated above.
;; This RTL looks like a fix_truncsfdi2 insn,
-;; but we dont call it that, because only 32 bits
+;; but we don't call it that, because only 32 bits
;; of the result are valid.
;; This pattern will work for the intended purposes
;; as long as we do not have any fixsfdi2 or fix_truncsfdi2.
total *= GET_MODE_SIZE (mode) / 2;
/* When optimizing for size, make shift more costly so that
- multiplications are prefered. */
+ multiplications are preferred. */
if (optimize_size && (shift % 8) != 0)
total *= 2;
};
-/* staticly allocate the first block */
+/* statically allocate the first block */
static struct atexit_fn_block atexit_fns;
static struct atexit_fn_block *current_block = &atexit_fns;
rtx loperands[7];
enum rtx_code op_code = GET_CODE (op);
- /* This does not produce a usefull cc. */
+ /* This does not produce a useful cc. */
CC_STATUS_INIT;
/* The m68k cmp.l instruction requires operand1 to be a reg as used
(everything from the $ on is stripped). */
if (TREE_CODE (decl) == FUNCTION_DECL)
prefix = ".text$";
- /* For compatability with EPOC, we ignore the fact that the
+ /* For compatibility with EPOC, we ignore the fact that the
section might have relocs against it. */
else if (DECL_READONLY_SECTION (decl, 0))
prefix = ".rdata$";
;; operand zero, because then the address in the move instruction will be
;; clobbered. We mark the scratch register as early clobbered to prevent this.
-;; We need the ?X in alternative 1 so that it will be choosen only if the
+;; We need the ?X in alternative 1 so that it will be chosen only if the
;; destination is a floating point register. Otherwise, alternative 1 can
;; have lower cost than alternative 0 (because there is one less loser), and
-;; can be choosen when it won't work (because integral reloads into FP
+;; can be chosen when it won't work (because integral reloads into FP
;; registers are not supported).
(define_insn "fix_truncdfsi2"
crossing a page boundary cause unpredictable results. */
#define STRICT_ALIGNMENT 1
-/* If bit field type is int, dont let it cross an int,
+/* If bit field type is int, don't let it cross an int,
and give entire struct the alignment of an int. */
/* Required on the 386 since it doesn't have a full set of bitfield insns.
(There is no signed extv insn.) */
gen_rtx_REG (word_mode, i));
/* The incoming args pointer points just beyond the flushback area;
- normally this is not a serious concern. Howver, when we are doing
+ normally this is not a serious concern. However, when we are doing
varargs/stdargs we want to make the arg pointer point to the start
of the incoming argument area. */
emit_move_insn (virtual_incoming_args_rtx,
is 0. C++ is 9. No number defined for Obj-C, so use the
value for C for now. There is no official value for Java,
although IBM appears to be using 13. There is no official value
- for Chill, so we've choosen 44 pseudo-randomly. */
+ for Chill, so we've chosen 44 pseudo-randomly. */
if (! strcmp (language_string, "GNU C")
|| ! strcmp (language_string, "GNU Objective-C"))
i = 0;
false if implementing __builtin_varargs_va_start. NEXTARG
points to the first anonymous stack argument.
- The following global variables are used to initalize
+ The following global variables are used to initialize
the va_list structure:
current_function_args_info:
#define EMPTY_FIELD_BOUNDARY 32
-/* Alignment on even adresses for LARL instruction. */
+/* Alignment on even addresses for LARL instruction. */
#define CONSTANT_ALIGNMENT(EXP, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN)
continue;
/* If it is not FMOV, FABS, FNEG, FDIV, or FSQRT then
- we will get a stall. Loads and stores are independant
+ we will get a stall. Loads and stores are independent
of these rules. */
if (GET_CODE (SET_SRC (pat)) != ABS
&& GET_CODE (SET_SRC (pat)) != NEG
/* Some stabs encapsulation formats (in particular ECOFF), cannot
handle the `.stabs "",N_FUN,,0,0,Lscope-function-1' gdb dbx
- extention construct. On those machines, define this macro to turn
+ extension construct. On those machines, define this macro to turn
this feature off without disturbing the rest of the gdb extensions. */
/* #define NO_DBX_FUNCTION_END */
@findex JUMP_ALIGN
@item JUMP_ALIGN (@var{label})
The alignment (log base 2) to put in front of @var{label}, which is
-a common destination of jumps and has no fallthru incomming edge.
+a common destination of jumps and has no fallthru incoming edge.
This macro need not be defined if you don't want any special alignment
to be done at such a time. Most machine descriptions do not currently
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