gram.test: Use correct timing for simulations

diff --git a/gram/test/test_common.py b/gram/test/test_common.py
index f775ea1d1b669fcf3b2be7dde109b1fda6256df3..fdcd025cc35114d4a68ccceeddfc718479ba5544 100644 (file)
--- a/gram/test/test_common.py
+++ b/gram/test/test_common.py
@@ -22,7 +22,7 @@ class tXXDControllerTestCase(FHDLTestCase):
             dut = tXXDController(txxd)
 
             yield dut.valid.eq(1)
-            yield; yield Delay(1e-8)
+            yield; yield Delay(1e-9)
             self.assertFalse((yield dut.ready))
 
             yield dut.valid.eq(0)

diff --git a/gram/test/test_core_multiplexer.py b/gram/test/test_core_multiplexer.py
index 0be117f3b7676bbb767f6d071aa6095100de21f4..0bbce8ec717d9d7f30a8ca656a4e0b1e71a4a828 100644 (file)
--- a/gram/test/test_core_multiplexer.py
+++ b/gram/test/test_core_multiplexer.py
@@ -35,13 +35,13 @@ class CommandChooserTestCase(FHDLTestCase):
 
             # want_writes
             yield dut.want_writes.eq(1)
-            yield; yield Delay(1e-8)
+            yield; yield Delay(1e-9)
             self.assertEqual((yield dut.cmd.a), 7)
 
             # want_reads
             yield dut.want_writes.eq(0)
             yield dut.want_reads.eq(1)
-            yield; yield Delay(1e-8)
+            yield; yield Delay(1e-9)
             self.assertEqual((yield dut.cmd.a), 5)
 
         runSimulation(dut, process, "test_core_multiplexer_commandchooser.vcd")
@@ -65,14 +65,14 @@ class CommandChooserTestCase(FHDLTestCase):
 
             # want_writes
             yield dut.want_writes.eq(1)
-            yield; yield Delay(1e-8)
+            yield; yield Delay(1e-9)
             self.assertTrue((yield dut.write()))
             self.assertFalse((yield dut.read()))
 
             # want_reads
             yield dut.want_writes.eq(0)
             yield dut.want_reads.eq(1)
-            yield; yield Delay(1e-8)
+            yield; yield Delay(1e-9)
             self.assertTrue((yield dut.read()))
             self.assertFalse((yield dut.write()))
 

diff --git a/gram/test/test_core_refresher.py b/gram/test/test_core_refresher.py
index 6c924d1727364a031869d9ea64295b594d62d97e..ac963bfaf65aaaa7a7c14089fbec06f25e7bb379 100644 (file)
--- a/gram/test/test_core_refresher.py
+++ b/gram/test/test_core_refresher.py
@@ -13,11 +13,11 @@ class RefreshExecuterTestCase(FHDLTestCase):
 
             def process():
                 yield dut.start.eq(1)
-                yield; yield Delay(1e-8)
+                yield; yield Delay(1e-9)
                 self.assertEqual((yield dut.a), 2**10)
                 for i in range(trp):
                     yield
-                yield Delay(1e-8)
+                yield Delay(1e-9)
                 self.assertEqual((yield dut.a), 0)
 
             runSimulation(dut, process, "test_refreshexecuter.vcd")
@@ -77,7 +77,7 @@ class RefreshPostponerTestCase(FHDLTestCase):
                     yield
 
                 yield dut.req_i.eq(0)
-                yield; yield Delay(1e-8)
+                yield; yield Delay(1e-9)
 
                 self.assertFalse((yield dut.req_o))
 

diff --git a/gram/test/utils.py b/gram/test/utils.py
index aa22a39678d586db01898a4fcc507816bf45e335..ed34d11000e2f0056e3625f1b47961d4523c7ac7 100644 (file)
--- a/gram/test/utils.py
+++ b/gram/test/utils.py
@@ -17,7 +17,7 @@ from nmigen._toolchain import require_tool
 
 __all__ = ["FHDLTestCase", "runSimulation", "wb_read", "wb_write", "PulseCounter", "Delay"]
 
-def runSimulation(module, process, vcd_filename="anonymous.vcd", clock=1e-6):
+def runSimulation(module, process, vcd_filename="anonymous.vcd", clock=1e-8):
     sim = Simulator(module)
     with sim.write_vcd(vcd_filename):
         sim.add_clock(clock)