cores/cpu/vexriscv_smp fix argument parsing

diff --git a/litex/soc/cores/cpu/vexriscv_smp/core.py b/litex/soc/cores/cpu/vexriscv_smp/core.py
index 2ee26f2fdb7ecaa6aae401add09c06955c9eec33..4ebe5b3222e65eae2df575381eba587d493afddc 100644 (file)
--- a/litex/soc/cores/cpu/vexriscv_smp/core.py
+++ b/litex/soc/cores/cpu/vexriscv_smp/core.py
@@ -70,10 +70,10 @@ class VexRiscvSMP(CPU):
         if(args.without_coherent_dma): VexRiscvSMP.coherent_dma = bool(False)
         if(args.dcache_width): VexRiscvSMP.dcache_width = int(args.dcache_width)
         if(args.icache_width): VexRiscvSMP.icache_width = int(args.icache_width)
-        if(args.icache_width): VexRiscvSMP.dcache_size  = int(args.dcache_size)
-        if(args.icache_width): VexRiscvSMP.icache_size  = int(args.icache_size)
-        if(args.icache_width): VexRiscvSMP.dcache_ways  = int(args.dcache_ways)
-        if(args.icache_width): VexRiscvSMP.icache_ways  = int(args.icache_ways)
+        if(args.dcache_size): VexRiscvSMP.dcache_size  = int(args.dcache_size)
+        if(args.icache_size): VexRiscvSMP.icache_size  = int(args.icache_size)
+        if(args.dcache_ways): VexRiscvSMP.dcache_ways  = int(args.dcache_ways)
+        if(args.icache_ways): VexRiscvSMP.icache_ways  = int(args.icache_ways)
 
     @property
     def mem_map(self):