* gas/all/gas.exp: Remove a29k and m88k support.
authorAlan Modra <amodra@gmail.com>
Thu, 11 Aug 2005 01:21:22 +0000 (01:21 +0000)
committerAlan Modra <amodra@gmail.com>
Thu, 11 Aug 2005 01:21:22 +0000 (01:21 +0000)
* gas/m88k/*: Delete.
* gas/tic80/*: Delete.

51 files changed:
gas/testsuite/ChangeLog
gas/testsuite/gas/all/gas.exp
gas/testsuite/gas/m88k/allinsn.d [deleted file]
gas/testsuite/gas/m88k/allinsn.s [deleted file]
gas/testsuite/gas/m88k/init.d [deleted file]
gas/testsuite/gas/m88k/init.s [deleted file]
gas/testsuite/gas/m88k/m88k.exp [deleted file]
gas/testsuite/gas/tic80/add.d [deleted file]
gas/testsuite/gas/tic80/add.lst [deleted file]
gas/testsuite/gas/tic80/add.s [deleted file]
gas/testsuite/gas/tic80/align.d [deleted file]
gas/testsuite/gas/tic80/align.lst [deleted file]
gas/testsuite/gas/tic80/align.s [deleted file]
gas/testsuite/gas/tic80/bitnum.d [deleted file]
gas/testsuite/gas/tic80/bitnum.lst [deleted file]
gas/testsuite/gas/tic80/bitnum.s [deleted file]
gas/testsuite/gas/tic80/ccode.d [deleted file]
gas/testsuite/gas/tic80/ccode.lst [deleted file]
gas/testsuite/gas/tic80/ccode.s [deleted file]
gas/testsuite/gas/tic80/cregops.d [deleted file]
gas/testsuite/gas/tic80/cregops.lst [deleted file]
gas/testsuite/gas/tic80/cregops.s [deleted file]
gas/testsuite/gas/tic80/endmask.d [deleted file]
gas/testsuite/gas/tic80/endmask.lst [deleted file]
gas/testsuite/gas/tic80/endmask.s [deleted file]
gas/testsuite/gas/tic80/float.d [deleted file]
gas/testsuite/gas/tic80/float.lst [deleted file]
gas/testsuite/gas/tic80/float.s [deleted file]
gas/testsuite/gas/tic80/regops.d [deleted file]
gas/testsuite/gas/tic80/regops.lst [deleted file]
gas/testsuite/gas/tic80/regops.s [deleted file]
gas/testsuite/gas/tic80/regops2.d [deleted file]
gas/testsuite/gas/tic80/regops2.lst [deleted file]
gas/testsuite/gas/tic80/regops2.s [deleted file]
gas/testsuite/gas/tic80/regops3.d [deleted file]
gas/testsuite/gas/tic80/regops3.lst [deleted file]
gas/testsuite/gas/tic80/regops3.s [deleted file]
gas/testsuite/gas/tic80/regops4.d [deleted file]
gas/testsuite/gas/tic80/regops4.lst [deleted file]
gas/testsuite/gas/tic80/regops4.s [deleted file]
gas/testsuite/gas/tic80/relocs1.c [deleted file]
gas/testsuite/gas/tic80/relocs1.d [deleted file]
gas/testsuite/gas/tic80/relocs1.lst [deleted file]
gas/testsuite/gas/tic80/relocs1.s [deleted file]
gas/testsuite/gas/tic80/relocs1b.d [deleted file]
gas/testsuite/gas/tic80/relocs2.c [deleted file]
gas/testsuite/gas/tic80/relocs2.d [deleted file]
gas/testsuite/gas/tic80/relocs2.lst [deleted file]
gas/testsuite/gas/tic80/relocs2.s [deleted file]
gas/testsuite/gas/tic80/relocs2b.d [deleted file]
gas/testsuite/gas/tic80/tic80.exp [deleted file]

index ad4fd61bad0148229d0991419ab37b313c469e65..2f8cc277e69b1f66cc1b24b7f55c14d54046a469 100644 (file)
@@ -1,3 +1,56 @@
+2005-08-11  Alan Modra  <amodra@bigpond.net.au>
+
+       * gas/all/gas.exp: Remove a29k and m88k support.
+       * gas/m88k/allinsn.d: Delete.
+       * gas/m88k/allinsn.s: Delete.
+       * gas/m88k/init.d: Delete.
+       * gas/m88k/init.s: Delete.
+       * gas/m88k/m88k.exp: Delete.
+       * gas/tic80/add.d: Delete.
+       * gas/tic80/add.lst: Delete.
+       * gas/tic80/add.s: Delete.
+       * gas/tic80/align.d: Delete.
+       * gas/tic80/align.lst: Delete.
+       * gas/tic80/align.s: Delete.
+       * gas/tic80/bitnum.d: Delete.
+       * gas/tic80/bitnum.lst: Delete.
+       * gas/tic80/bitnum.s: Delete.
+       * gas/tic80/ccode.d: Delete.
+       * gas/tic80/ccode.lst: Delete.
+       * gas/tic80/ccode.s: Delete.
+       * gas/tic80/cregops.d: Delete.
+       * gas/tic80/cregops.lst: Delete.
+       * gas/tic80/cregops.s: Delete.
+       * gas/tic80/endmask.d: Delete.
+       * gas/tic80/endmask.lst: Delete.
+       * gas/tic80/endmask.s: Delete.
+       * gas/tic80/float.d: Delete.
+       * gas/tic80/float.lst: Delete.
+       * gas/tic80/float.s: Delete.
+       * gas/tic80/regops.d: Delete.
+       * gas/tic80/regops.lst: Delete.
+       * gas/tic80/regops.s: Delete.
+       * gas/tic80/regops2.d: Delete.
+       * gas/tic80/regops2.lst: Delete.
+       * gas/tic80/regops2.s: Delete.
+       * gas/tic80/regops3.d: Delete.
+       * gas/tic80/regops3.lst: Delete.
+       * gas/tic80/regops3.s: Delete.
+       * gas/tic80/regops4.d: Delete.
+       * gas/tic80/regops4.lst: Delete.
+       * gas/tic80/regops4.s: Delete.
+       * gas/tic80/relocs1.c: Delete.
+       * gas/tic80/relocs1.d: Delete.
+       * gas/tic80/relocs1.lst: Delete.
+       * gas/tic80/relocs1.s: Delete.
+       * gas/tic80/relocs1b.d: Delete.
+       * gas/tic80/relocs2.c: Delete.
+       * gas/tic80/relocs2.d: Delete.
+       * gas/tic80/relocs2.lst: Delete.
+       * gas/tic80/relocs2.s: Delete.
+       * gas/tic80/relocs2b.d: Delete.
+       * gas/tic80/tic80.exp: Delete.
+
 2005-08-05  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 
        * gas/hppa/reloc/reloc.exp (do_function_reloc_bug): Add "L%" to regexp.
index e48aba6c0fbf30b83c0943819bf0abdcb1c9e0ab..46ee56b23a12cb478b24ade0066da6d998c3b5ed 100644 (file)
@@ -116,7 +116,6 @@ case $target_triplet in {
 
 # '<' and '>' appear to have special meanings on the excluded targets
 case $target_triplet in {
-    { a29k-*-* } { }
     { frv-*-* } { }
     { hppa*-*-* } { }
     { m32r-*-* } { }
@@ -134,16 +133,11 @@ case $target_triplet in {
 }
 
 # This test is for any COFF target.
-# We omit m88k COFF because it uses weird pseudo-op names.
 # We omit the ARM toolchains because they define locals to
 #  start with '.', which eliminates .eos, .text etc from the output.
 # Omit c54x, since .tag and .def mean something different on that target
-if {   ([istarget *-*-coff*] && ![istarget m88*-*-*] && ![istarget *arm*-*-coff] && ![istarget thumb*-*-coff] && ![istarget xscale-*-coff] && ![istarget *c4x*-*-coff] && ![istarget *c54x*-*-coff]) \
+if {   ([istarget *-*-coff*] && ![istarget *arm*-*-coff] && ![istarget thumb*-*-coff] && ![istarget xscale-*-coff] && ![istarget *c4x*-*-coff] && ![istarget *c54x*-*-coff]) \
      ||([istarget *-*-pe*] && ![istarget arm*-*-pe*] && ![istarget thumb*-*-pe*]) \
-     || [istarget a29k-*-udi*] \
-     || [istarget a29k-*-ebmon*] \
-     || [istarget a29k-*-sym*] \
-     || [istarget a29k-*-vxworks*] \
      || [istarget i*86-*-aix*] \
      || [istarget i*86-*-sco*] \
      || [istarget i*86-*-isc*] \
diff --git a/gas/testsuite/gas/m88k/allinsn.d b/gas/testsuite/gas/m88k/allinsn.d
deleted file mode 100644 (file)
index 3d2c29e..0000000
+++ /dev/null
@@ -1,369 +0,0 @@
-#as:
-#objdump: -dr
-#name: allinsn
-
-.*: +file format .*
-
-Disassembly of section .text:
-
-00000000 <.text>:
-   0:  f4 01 70 02     add         r0,r1,r2
-   4:  f4 22 72 03     add.ci      r1,r2,r3
-   8:  f4 43 71 04     add.co      r2,r3,r4
-   c:  f4 64 73 05     add.cio     r3,r4,r5
-  10:  70 85 00 00     add         r4,r5,0
-  14:  70 85 10 00     add         r4,r5,0x1000
-  18:  f4 01 60 02     addu        r0,r1,r2
-  1c:  f4 22 62 03     addu.ci     r1,r2,r3
-  20:  f4 43 61 04     addu.co     r2,r3,r4
-  24:  f4 64 63 05     addu.cio    r3,r4,r5
-  28:  60 85 00 00     addu        r4,r5,0
-  2c:  60 85 10 00     addu        r4,r5,0x1000
-  30:  f4 01 40 02     and         r0,r1,r2
-  34:  f4 22 44 03     and.c       r1,r2,r3
-  38:  40 43 00 00     and         r2,r3,0
-  3c:  40 43 10 00     and         r2,r3,0x1000
-  40:  44 43 00 00     and.u       r2,r3,0
-  44:  44 43 10 00     and.u       r2,r3,0x1000
-  48:  d0 01 00 00     bb0         0,r1,48 <.text\+0x48>
-                       4a: PCR16L      \*ABS\*
-  4c:  d0 01 ff fd     bb0         0,r1,40 <.text\+0x40>
-                       4e: PCR16L      \*ABS\*
-  50:  d0 01 00 02     bb0         0,r1,58 <.text\+0x58>
-                       52: PCR16L      \*ABS\*
-  54:  d3 e1 00 00     bb0         0x1f,r1,54 <.text\+0x54>
-                       56: PCR16L      \*ABS\*
-  58:  d3 e1 ff fd     bb0         0x1f,r1,4c <.text\+0x4c>
-                       5a: PCR16L      \*ABS\*
-  5c:  d3 e1 00 02     bb0         0x1f,r1,64 <.text\+0x64>
-                       5e: PCR16L      \*ABS\*
-  60:  d4 01 00 00     bb0.n       0,r1,60 <.text\+0x60>
-                       62: PCR16L      \*ABS\*
-  64:  d8 01 00 00     bb1         0,r1,64 <.text\+0x64>
-                       66: PCR16L      \*ABS\*
-  68:  d8 01 ff fd     bb1         0,r1,5c <.text\+0x5c>
-                       6a: PCR16L      \*ABS\*
-  6c:  d8 01 00 02     bb1         0,r1,74 <.text\+0x74>
-                       6e: PCR16L      \*ABS\*
-  70:  db e1 00 00     bb1         0x1f,r1,70 <.text\+0x70>
-                       72: PCR16L      \*ABS\*
-  74:  db e1 ff fd     bb1         0x1f,r1,68 <.text\+0x68>
-                       76: PCR16L      \*ABS\*
-  78:  db e1 00 02     bb1         0x1f,r1,80 <.text\+0x80>
-                       7a: PCR16L      \*ABS\*
-  7c:  dc 01 00 00     bb1.n       0,r1,7c <.text\+0x7c>
-                       7e: PCR16L      \*ABS\*
-  80:  e8 41 00 00     bcnd        eq0,r1,80 <.text\+0x80>
-                       82: PCR16L      \*ABS\*
-  84:  e8 41 00 02     bcnd        eq0,r1,8c <.text\+0x8c>
-                       86: PCR16L      \*ABS\*
-  88:  e8 41 ff fd     bcnd        eq0,r1,7c <.text\+0x7c>
-                       8a: PCR16L      \*ABS\*
-  8c:  ec 41 00 00     bcnd.n      eq0,r1,8c <.text\+0x8c>
-                       8e: PCR16L      \*ABS\*
-  90:  ec 41 00 02     bcnd.n      eq0,r1,98 <.text\+0x98>
-                       92: PCR16L      \*ABS\*
-  94:  ec 41 ff fd     bcnd.n      eq0,r1,88 <.text\+0x88>
-                       96: PCR16L      \*ABS\*
-  98:  e9 a1 00 00     bcnd        ne0,r1,98 <.text\+0x98>
-                       9a: PCR16L      \*ABS\*
-  9c:  e9 a1 00 02     bcnd        ne0,r1,a4 <.text\+0xa4>
-                       9e: PCR16L      \*ABS\*
-  a0:  e9 a1 ff fd     bcnd        ne0,r1,94 <.text\+0x94>
-                       a2: PCR16L      \*ABS\*
-  a4:  ed a1 00 00     bcnd.n      ne0,r1,a4 <.text\+0xa4>
-                       a6: PCR16L      \*ABS\*
-  a8:  ed a1 00 02     bcnd.n      ne0,r1,b0 <.text\+0xb0>
-                       aa: PCR16L      \*ABS\*
-  ac:  ed a1 ff fd     bcnd.n      ne0,r1,a0 <.text\+0xa0>
-                       ae: PCR16L      \*ABS\*
-  b0:  e8 21 00 00     bcnd        gt0,r1,b0 <.text\+0xb0>
-                       b2: PCR16L      \*ABS\*
-  b4:  e8 21 00 02     bcnd        gt0,r1,bc <.text\+0xbc>
-                       b6: PCR16L      \*ABS\*
-  b8:  e8 21 ff fd     bcnd        gt0,r1,ac <.text\+0xac>
-                       ba: PCR16L      \*ABS\*
-  bc:  ec 21 00 00     bcnd.n      gt0,r1,bc <.text\+0xbc>
-                       be: PCR16L      \*ABS\*
-  c0:  ec 21 00 02     bcnd.n      gt0,r1,c8 <.text\+0xc8>
-                       c2: PCR16L      \*ABS\*
-  c4:  ec 21 ff fd     bcnd.n      gt0,r1,b8 <.text\+0xb8>
-                       c6: PCR16L      \*ABS\*
-  c8:  e9 81 00 00     bcnd        lt0,r1,c8 <.text\+0xc8>
-                       ca: PCR16L      \*ABS\*
-  cc:  e9 81 00 02     bcnd        lt0,r1,d4 <.text\+0xd4>
-                       ce: PCR16L      \*ABS\*
-  d0:  e9 81 ff fd     bcnd        lt0,r1,c4 <.text\+0xc4>
-                       d2: PCR16L      \*ABS\*
-  d4:  ed 81 00 00     bcnd.n      lt0,r1,d4 <.text\+0xd4>
-                       d6: PCR16L      \*ABS\*
-  d8:  ed 81 00 02     bcnd.n      lt0,r1,e0 <.text\+0xe0>
-                       da: PCR16L      \*ABS\*
-  dc:  ed 81 ff fd     bcnd.n      lt0,r1,d0 <.text\+0xd0>
-                       de: PCR16L      \*ABS\*
-  e0:  e8 61 00 00     bcnd        ge0,r1,e0 <.text\+0xe0>
-                       e2: PCR16L      \*ABS\*
-  e4:  e8 61 00 02     bcnd        ge0,r1,ec <.text\+0xec>
-                       e6: PCR16L      \*ABS\*
-  e8:  e8 61 ff fd     bcnd        ge0,r1,dc <.text\+0xdc>
-                       ea: PCR16L      \*ABS\*
-  ec:  ec 61 00 00     bcnd.n      ge0,r1,ec <.text\+0xec>
-                       ee: PCR16L      \*ABS\*
-  f0:  ec 61 00 02     bcnd.n      ge0,r1,f8 <.text\+0xf8>
-                       f2: PCR16L      \*ABS\*
-  f4:  ec 61 ff fd     bcnd.n      ge0,r1,e8 <.text\+0xe8>
-                       f6: PCR16L      \*ABS\*
-  f8:  e9 c1 00 00     bcnd        le0,r1,f8 <.text\+0xf8>
-                       fa: PCR16L      \*ABS\*
-  fc:  e9 c1 00 02     bcnd        le0,r1,104 <.text\+0x104>
-                       fe: PCR16L      \*ABS\*
- 100:  e9 c1 ff fd     bcnd        le0,r1,f4 <.text\+0xf4>
-                       102: PCR16L     \*ABS\*
- 104:  ed c1 00 00     bcnd.n      le0,r1,104 <.text\+0x104>
-                       106: PCR16L     \*ABS\*
- 108:  ed c1 00 02     bcnd.n      le0,r1,110 <.text\+0x110>
-                       10a: PCR16L     \*ABS\*
- 10c:  ed c1 ff fd     bcnd.n      le0,r1,100 <.text\+0x100>
-                       10e: PCR16L     \*ABS\*
- 110:  e8 61 00 00     bcnd        ge0,r1,110 <.text\+0x110>
-                       112: PCR16L     \*ABS\*
- 114:  e8 61 00 02     bcnd        ge0,r1,11c <.text\+0x11c>
-                       116: PCR16L     \*ABS\*
- 118:  e8 61 ff fd     bcnd        ge0,r1,10c <.text\+0x10c>
-                       11a: PCR16L     \*ABS\*
- 11c:  ec 61 00 00     bcnd.n      ge0,r1,11c <.text\+0x11c>
-                       11e: PCR16L     \*ABS\*
- 120:  ec 61 00 02     bcnd.n      ge0,r1,128 <.text\+0x128>
-                       122: PCR16L     \*ABS\*
- 124:  ec 61 ff fd     bcnd.n      ge0,r1,118 <.text\+0x118>
-                       126: PCR16L     \*ABS\*
- 128:  c0 00 00 00     br          128 <.text\+0x128>
-                       128: PCR26L     \*ABS\*
- 12c:  c3 ff ff fd     br          120 <.text\+0x120>
-                       12c: PCR26L     \*ABS\*
- 130:  c0 00 00 02     br          138 <.text\+0x138>
-                       130: PCR26L     \*ABS\*
- 134:  c4 00 00 00     br.n        134 <.text\+0x134>
-                       134: PCR26L     \*ABS\*
- 138:  c7 ff ff fd     br.n        12c <.text\+0x12c>
-                       138: PCR26L     \*ABS\*
- 13c:  c4 00 00 02     br.n        144 <.text\+0x144>
-                       13c: PCR26L     \*ABS\*
- 140:  c8 00 00 00     bsr         140 <.text\+0x140>
-                       140: PCR26L     \*ABS\*
- 144:  cb ff ff fd     bsr         138 <.text\+0x138>
-                       144: PCR26L     \*ABS\*
- 148:  c8 00 00 02     bsr         150 <.text\+0x150>
-                       148: PCR26L     \*ABS\*
- 14c:  cc 00 00 00     bsr.n       14c <.text\+0x14c>
-                       14c: PCR26L     \*ABS\*
- 150:  cf ff ff fd     bsr.n       144 <.text\+0x144>
-                       150: PCR26L     \*ABS\*
- 154:  cc 00 00 02     bsr.n       15c <.text\+0x15c>
-                       154: PCR26L     \*ABS\*
- 158:  f0 22 80 af     clr         r1,r2,5<15>
- 15c:  f4 22 80 03     clr         r1,r2,r3
- 160:  f0 22 80 06     clr         r1,r2,0<6>
- 164:  f0 22 80 06     clr         r1,r2,0<6>
- 168:  f4 01 7c 02     cmp         r0,r1,r2
- 16c:  7c 02 00 00     cmp         r0,r2,0
- 170:  7c 02 10 00     cmp         r0,r2,0x1000
- 174:  f4 01 78 02     divs        r0,r1,r2
- 178:  78 01 00 00     divs        r0,r1,0
- 17c:  78 01 10 00     divs        r0,r1,0x1000
- 180:  f4 01 68 02     divu        r0,r1,r2
- 184:  68 01 00 00     divu        r0,r1,0
- 188:  68 01 00 0a     divu        r0,r1,0x0a
- 18c:  f0 01 91 45     ext         r0,r1,10<5>
- 190:  f4 22 90 03     ext         r1,r2,r3
- 194:  f0 43 90 06     ext         r2,r3,0<6>
- 198:  f0 43 90 06     ext         r2,r3,0<6>
- 19c:  f0 01 99 45     extu        r0,r1,10<5>
- 1a0:  f4 22 98 03     extu        r1,r2,r3
- 1a4:  f0 22 98 06     extu        r1,r2,0<6>
- 1a8:  f0 22 98 06     extu        r1,r2,0<6>
- 1ac:  84 01 28 02     fadd.sss    r0,r1,r2
- 1b0:  84 01 28 82     fadd.ssd    r0,r1,r2
- 1b4:  84 01 2a 02     fadd.sds    r0,r1,r2
- 1b8:  84 01 2a 82     fadd.sdd    r0,r1,r2
- 1bc:  84 01 28 22     fadd.dss    r0,r1,r2
- 1c0:  84 01 28 a2     fadd.dsd    r0,r1,r2
- 1c4:  84 01 2a 22     fadd.dds    r0,r1,r2
- 1c8:  84 01 2a a2     fadd.ddd    r0,r1,r2
- 1cc:  84 01 38 02     fcmp.ss     r0,r1,r2
- 1d0:  84 01 38 82     fcmp.sd     r0,r1,r2
- 1d4:  84 01 3a 02     fcmp.ds     r0,r1,r2
- 1d8:  84 01 3a 82     fcmp.dd     r0,r1,r2
- 1dc:  84 01 70 02     fdiv.sss    r0,r1,r2
- 1e0:  84 01 70 82     fdiv.ssd    r0,r1,r2
- 1e4:  84 01 72 02     fdiv.sds    r0,r1,r2
- 1e8:  84 01 72 82     fdiv.sdd    r0,r1,r2
- 1ec:  84 01 70 22     fdiv.dss    r0,r1,r2
- 1f0:  84 01 70 a2     fdiv.dsd    r0,r1,r2
- 1f4:  84 01 72 22     fdiv.dds    r0,r1,r2
- 1f8:  84 01 72 a2     fdiv.ddd    r0,r1,r2
- 1fc:  f4 20 ec 07     ff0         r1,r7
- 200:  f4 60 e8 08     ff1         r3,r8
- 204:  80 00 4e 40     fldcr       r0,fcr50
- 208:  84 00 20 03     flt.s       r0,r3
- 20c:  84 00 20 2a     flt.d       r0,r10
- 210:  84 01 00 02     fmul.sss    r0,r1,r2
- 214:  84 01 00 82     fmul.ssd    r0,r1,r2
- 218:  84 01 02 02     fmul.sds    r0,r1,r2
- 21c:  84 01 02 82     fmul.sdd    r0,r1,r2
- 220:  84 01 00 22     fmul.dss    r0,r1,r2
- 224:  84 01 00 a2     fmul.dsd    r0,r1,r2
- 228:  84 01 02 22     fmul.dds    r0,r1,r2
- 22c:  84 01 02 a2     fmul.ddd    r0,r1,r2
- 230:  80 00 8e 40     fstcr       r0,fcr50
- 234:  84 01 30 02     fsub.sss    r0,r1,r2
- 238:  84 01 30 82     fsub.ssd    r0,r1,r2
- 23c:  84 01 32 02     fsub.sds    r0,r1,r2
- 240:  84 01 32 82     fsub.sdd    r0,r1,r2
- 244:  84 01 30 22     fsub.dss    r0,r1,r2
- 248:  84 01 30 a2     fsub.dsd    r0,r1,r2
- 24c:  84 01 32 22     fsub.dds    r0,r1,r2
- 250:  84 01 32 a2     fsub.ddd    r0,r1,r2
- 254:  80 01 ce 41     fxcr        r0,r1,fcr50
- 258:  84 00 48 01     int.s       r0,r1
- 25c:  85 40 48 82     int.d       r10,r2
- 260:  f4 00 c0 00     jmp         r0
- 264:  f4 00 c4 0a     jmp.n       r10
- 268:  f4 00 c8 0a     jsr         r10
- 26c:  f4 00 cc 0d     jsr.n       r13
- 270:  1c 01 00 00     ld.b        r0,r1,0
- 274:  1c 01 10 00     ld.b        r0,r1,0x1000
- 278:  0c 01 00 00     ld.bu       r0,r1,0
- 27c:  0c 01 10 00     ld.bu       r0,r1,0x1000
- 280:  18 01 00 00     ld.h        r0,r1,0
- 284:  18 01 10 00     ld.h        r0,r1,0x1000
- 288:  08 01 00 00     ld.hu       r0,r1,0
- 28c:  08 01 10 00     ld.hu       r0,r1,0x1000
- 290:  14 01 00 00     ld          r0,r1,0
- 294:  14 01 10 00     ld          r0,r1,0x1000
- 298:  10 01 00 00     ld.d        r0,r1,0
- 29c:  10 01 10 00     ld.d        r0,r1,0x1000
- 2a0:  f4 01 1c 02     ld.b        r0,r1,r2
- 2a4:  f4 22 0c 03     ld.bu       r1,r2,r3
- 2a8:  f4 43 18 04     ld.h        r2,r3,r4
- 2ac:  f4 64 08 05     ld.hu       r3,r4,r5
- 2b0:  f4 85 14 06     ld          r4,r5,r6
- 2b4:  f4 a6 10 07     ld.d        r5,r6,r7
- 2b8:  f4 c7 1d 08     word    f4c71d08
- 2bc:  f4 e8 0d 09     word    f4e80d09
- 2c0:  f5 09 19 01     word    f5091901
- 2c4:  f5 21 09 02     word    f5210902
- 2c8:  f4 22 15 03     ld.usr      r1,r2,r3
- 2cc:  f4 43 11 04     word    f4431104
- 2d0:  f4 01 1e 02     word    f4011e02
- 2d4:  f4 22 0e 03     word    f4220e03
- 2d8:  f4 43 1a 04     ld.h        r2,r3\[r4\]
- 2dc:  f4 64 0a 05     ld.hu       r3,r4\[r5\]
- 2e0:  f4 85 16 06     ld          r4,r5\[r6\]
- 2e4:  f4 a6 12 07     ld.d        r5,r6\[r7\]
- 2e8:  f4 c7 1f 08     word    f4c71f08
- 2ec:  f4 e8 0f 09     word    f4e80f09
- 2f0:  f5 09 1b 01     word    f5091b01
- 2f4:  f5 21 0b 02     word    f5210b02
- 2f8:  f4 22 17 03     ld.usr      r1,r2\[r3\]
- 2fc:  f4 43 13 04     word    f4431304
- 300:  f4 01 3a 02     lda.h       r0,r1\[r2\]
- 304:  f4 22 36 03     lda         r1,r2\[r3\]
- 308:  f4 43 32 04     lda.d       r2,r3\[r4\]
- 30c:  80 00 41 40     ldcr        r0,cr10
- 310:  f0 01 a1 45     mak         r0,r1,10<5>
- 314:  f4 01 a0 02     mak         r0,r1,r2
- 318:  f0 01 a0 06     mak         r0,r1,0<6>
- 31c:  f0 01 a0 06     mak         r0,r1,0<6>
- 320:  48 01 00 00     mask        r0,r1,0
- 324:  48 01 10 00     mask        r0,r1,0x1000
- 328:  4c 01 00 00     mask.u      r0,r1,0
- 32c:  4c 01 10 00     mask.u      r0,r1,0x1000
- 330:  f4 01 6c 02     mulu        r0,r1,r2
- 334:  6c 01 00 00     mulu        r0,r1,0
- 338:  6c 01 10 00     mulu        r0,r1,0x1000
- 33c:  84 00 50 0a     nint.s      r0,r10
- 340:  85 40 50 8c     nint.d      r10,r12
- 344:  f4 01 58 02     or          r0,r1,r2
- 348:  f4 27 5c 0a     or.c        r1,r7,r10
- 34c:  58 04 00 00     or          r0,r4,0
- 350:  58 04 10 00     or          r0,r4,0x1000
- 354:  5c 01 00 00     or.u        r0,r1,0
- 358:  5c 44 10 00     or.u        r2,r4,0x1000
- 35c:  f0 01 a8 05     rot         r0,r1,0<5>
- 360:  f4 44 a8 06     rot         r2,r4,r6
- 364:  f4 00 fc 00     rte         
- 368:  f0 01 89 45     set         r0,r1,10<5>
- 36c:  f4 44 88 06     set         r2,r4,r6
- 370:  f0 67 88 06     set         r3,r7,0<6>
- 374:  f0 67 88 06     set         r3,r7,0<6>
- 378:  2c 01 00 00     st.b        r0,r1,0
- 37c:  2c 01 10 00     st.b        r0,r1,0x1000
- 380:  28 01 00 00     st.h        r0,r1,0
- 384:  28 01 10 00     st.h        r0,r1,0x1000
- 388:  24 01 00 00     st          r0,r1,0
- 38c:  24 01 10 00     st          r0,r1,0x1000
- 390:  20 01 00 00     st.d        r0,r1,0
- 394:  20 01 10 00     st.d        r0,r1,0x1000
- 398:  f4 01 2c 02     st.b        r0,r1,r2
- 39c:  f4 43 28 04     st.h        r2,r3,r4
- 3a0:  f4 85 24 06     st          r4,r5,r6
- 3a4:  f4 a6 20 07     st.d        r5,r6,r7
- 3a8:  f4 c7 2d 08     word    f4c72d08
- 3ac:  f5 09 29 01     word    f5092901
- 3b0:  f4 22 25 03     st.usr      r1,r2,r3
- 3b4:  f4 43 21 04     word    f4432104
- 3b8:  f4 01 2e 02     word    f4012e02
- 3bc:  f4 43 2a 04     st.h        r2,r3\[r4\]
- 3c0:  f4 85 26 06     st          r4,r5\[r6\]
- 3c4:  f4 a6 22 07     st.d        r5,r6\[r7\]
- 3c8:  f4 c7 2f 08     word    f4c72f08
- 3cc:  f5 09 2b 01     word    f5092b01
- 3d0:  f4 22 27 03     st.usr      r1,r2\[r3\]
- 3d4:  f4 43 23 04     word    f4432304
- 3d8:  80 00 81 40     stcr        r0,cr10
- 3dc:  f4 01 74 02     sub         r0,r1,r2
- 3e0:  f4 22 76 03     sub.ci      r1,r2,r3
- 3e4:  f4 43 75 04     sub.co      r2,r3,r4
- 3e8:  f4 64 77 05     sub.cio     r3,r4,r5
- 3ec:  74 85 00 00     sub         r4,r5,0
- 3f0:  74 85 10 00     sub         r4,r5,0x1000
- 3f4:  f4 01 64 02     subu        r0,r1,r2
- 3f8:  f4 22 66 03     subu.ci     r1,r2,r3
- 3fc:  f4 64 65 05     subu.co     r3,r4,r5
- 400:  f4 85 67 06     subu.cio    r4,r5,r6
- 404:  64 a6 00 00     subu        r5,r6,0
- 408:  64 a6 10 00     subu        r5,r6,0x1000
- 40c:  f0 0a d0 0a     tb0         0,r10,0x0a
- 410:  f3 eb d0 0a     tb0         0x1f,r11,0x0a
- 414:  f0 0a d8 0a     tb1         0,r10,0x0a
- 418:  f3 eb d8 0a     tb1         0x1f,r11,0x0a
- 41c:  f4 00 f8 01     tbnd        r0,r1
- 420:  f8 07 00 00     tbnd        r7,0
- 424:  f8 07 10 00     tbnd        r7,0x1000
- 428:  f0 4a e8 0c     tcnd        eq0,r10,0x0c
- 42c:  f1 a9 e8 0c     tcnd        ne0,r9,0x0c
- 430:  f0 28 e8 07     tcnd        gt0,r8,0x07
- 434:  f1 87 e8 01     tcnd        lt0,r7,0x01
- 438:  f0 66 e8 23     tcnd        ge0,r6,0x23
- 43c:  f1 c5 e8 21     tcnd        le0,r5,0x21
- 440:  f1 44 e8 0c     tcnd        a,r4,0x0c
- 444:  84 00 58 01     trnc.s      r0,r1
- 448:  84 20 58 83     trnc.d      r1,r3
- 44c:  80 03 c1 43     xcr         r0,r3,cr10
- 450:  f4 01 00 02     xmem.bu     r0,r1,r2
- 454:  f4 22 04 03     xmem        r1,r2,r3
- 458:  f4 85 01 06     word    f4850106
- 45c:  f4 a6 05 07     xmem.usr    r5,r6,r7
- 460:  f4 43 02 04     word    f4430204
- 464:  f4 64 06 05     xmem        r3,r4\[r5\]
- 468:  f4 85 03 09     word    f4850309
- 46c:  f4 a6 07 0a     xmem.usr    r5,r6\[r10\]
- 470:  f4 01 50 02     xor         r0,r1,r2
- 474:  f4 22 54 03     xor.c       r1,r2,r3
- 478:  50 43 00 00     xor         r2,r3,0
- 47c:  50 44 10 00     xor         r2,r4,0x1000
- 480:  54 22 00 00     xor.u       r1,r2,0
- 484:  54 43 10 00     xor.u       r2,r3,0x1000
- 488:  f4 00 58 00     or          r0,r0,r0
- 48c:  f4 00 58 00     or          r0,r0,r0
diff --git a/gas/testsuite/gas/m88k/allinsn.s b/gas/testsuite/gas/m88k/allinsn.s
deleted file mode 100644 (file)
index 4a7e60a..0000000
+++ /dev/null
@@ -1,460 +0,0 @@
-       ;; Test all instructions in the m88k instruction set.
-       ;; Copyright 2001 Free Software Foundation, Inc.
-       ;; Contributed by Ben Elliston (bje at redhat.com).
-
-.text
-       ;; integer add
-
-       add     r0, r1, r2
-       add.ci  r1, r2, r3
-       add.co  r2, r3, r4
-       add.cio r3, r4, r5
-       add     r4, r5, 0
-       add     r4, r5, 4096
-
-       ;; unsigned integer add
-
-       addu     r0, r1, r2
-       addu.ci  r1, r2, r3
-       addu.co  r2, r3, r4
-       addu.cio r3, r4, r5
-       addu     r4, r5, 0
-       addu     r4, r5, 4096
-
-       ;; logical and
-
-       and     r0, r1, r2
-       and.c   r1, r2, r3
-       and     r2, r3, 0
-       and     r2, r3, 4096
-       and.u   r2, r3, 0
-       and.u   r2, r3, 4096
-
-       ;; branch on bit clear
-
-       bb0     0, r1, 0
-       bb0     0, r1, -10
-       bb0     0, r1, 10
-       bb0     31, r1, 0
-       bb0     31, r1, -10
-       bb0     31, r1, 10
-       bb0.n   0, r1, 0
-
-       ;; branch on bit set
-
-       bb1     0, r1, 0
-       bb1     0, r1, -10
-       bb1     0, r1, 10
-       bb1     31, r1, 0
-       bb1     31, r1, -10
-       bb1     31, r1, 10
-       bb1.n   0, r1, 0
-
-       ;;  conditional branch
-
-       bcnd    eq0, r1, 0
-       bcnd    eq0, r1, 10
-       bcnd    eq0, r1, -10    
-       bcnd.n  eq0, r1, 0
-       bcnd.n  eq0, r1, 10
-       bcnd.n  eq0, r1, -10
-       bcnd    ne0, r1, 0
-       bcnd    ne0, r1, 10
-       bcnd    ne0, r1, -10    
-       bcnd.n  ne0, r1, 0
-       bcnd.n  ne0, r1, 10
-       bcnd.n  ne0, r1, -10
-       bcnd    gt0, r1, 0
-       bcnd    gt0, r1, 10
-       bcnd    gt0, r1, -10    
-       bcnd.n  gt0, r1, 0
-       bcnd.n  gt0, r1, 10
-       bcnd.n  gt0, r1, -10
-       bcnd    lt0, r1, 0
-       bcnd    lt0, r1, 10
-       bcnd    lt0, r1, -10    
-       bcnd.n  lt0, r1, 0
-       bcnd.n  lt0, r1, 10
-       bcnd.n  lt0, r1, -10
-       bcnd    ge0, r1, 0
-       bcnd    ge0, r1, 10
-       bcnd    ge0, r1, -10    
-       bcnd.n  ge0, r1, 0
-       bcnd.n  ge0, r1, 10
-       bcnd.n  ge0, r1, -10
-       bcnd    le0, r1, 0
-       bcnd    le0, r1, 10
-       bcnd    le0, r1, -10    
-       bcnd.n  le0, r1, 0
-       bcnd.n  le0, r1, 10
-       bcnd.n  le0, r1, -10
-       ;;  using m5 field
-       bcnd    3, r1, 0
-       bcnd    3, r1, 10
-       bcnd    3, r1, -10      
-       bcnd.n  3, r1, 0
-       bcnd.n  3, r1, 10
-       bcnd.n  3, r1, -10              
-
-       ;; uncoditional branch
-
-       br 0
-       br -10
-       br 10
-       br.n 0
-       br.n -10
-       br.n 10
-
-       ;; branch to subroutine
-
-       bsr 0
-       bsr -10
-       bsr 10
-       bsr.n 0
-       bsr.n -10
-       bsr.n 10
-       
-       ;; clear bit field
-
-       clr r1, r2, 5<15>
-       clr r1, r2, r3
-       clr r1, r2, 6
-       clr r1, r2, <6>
-
-       ;; integer compare
-
-       cmp r0, r1, r2
-       cmp r0, r2, 0
-       cmp r0, r2, 4096
-
-       ;; signed integer divide
-
-       div r0, r1, r2
-       div r0, r1, 0
-       div r0, r1, 4096
-
-       ;; unsigned integer divide
-
-       divu r0, r1, r2
-       divu r0, r1, 0
-       divu r0, r1, 10
-
-       ;; extract signed bit field
-
-       ext r0, r1, 10<5>
-       ext r1, r2, r3
-       ext r2, r3, 6
-       ext r2, r3, <6>
-
-       ;; extract unsigned bit field
-
-       extu r0, r1, 10<5>
-       extu r1, r2, r3
-       extu r1, r2, 6
-       extu r1, r2, <6>
-
-       ;; floating point add
-
-       fadd.sss r0, r1, r2
-       fadd.ssd r0, r1, r2
-       fadd.sds r0, r1, r2
-       fadd.sdd r0, r1, r2
-       fadd.dss r0, r1, r2
-       fadd.dsd r0, r1, r2
-       fadd.dds r0, r1, r2
-       fadd.ddd r0, r1, r2
-
-       ;; floating point compare
-
-       fcmp.sss r0, r1, r2
-       fcmp.ssd r0, r1, r2
-       fcmp.sds r0, r1, r2
-       fcmp.sdd r0, r1, r2
-
-       ;; floating point divide
-
-       fdiv.sss r0, r1, r2
-       fdiv.ssd r0, r1, r2
-       fdiv.sds r0, r1, r2
-       fdiv.sdd r0, r1, r2
-       fdiv.dss r0, r1, r2
-       fdiv.dsd r0, r1, r2
-       fdiv.dds r0, r1, r2
-       fdiv.ddd r0, r1, r2
-
-       ;; find first bit clear
-
-       ff0 r1, r7
-
-       ;; find first bit set
-
-       ff1 r3, r8
-
-       ;; load from floating-point control register
-
-       fldcr r0, fcr50
-
-       ;; convert integer to floating point
-
-       flt.ss r0, r3
-       flt.ds r0, r10
-
-       ;; floating point multiply
-
-       fmul.sss r0, r1, r2
-       fmul.ssd r0, r1, r2
-       fmul.sds r0, r1, r2
-       fmul.sdd r0, r1, r2
-       fmul.dss r0, r1, r2
-       fmul.dsd r0, r1, r2
-       fmul.dds r0, r1, r2
-       fmul.ddd r0, r1, r2
-       
-       ;; store to floating point control register
-
-       fstcr r0, fcr50
-
-       ;; floating point subtract
-
-       fsub.sss r0, r1, r2
-       fsub.ssd r0, r1, r2
-       fsub.sds r0, r1, r2
-       fsub.sdd r0, r1, r2
-       fsub.dss r0, r1, r2
-       fsub.dsd r0, r1, r2
-       fsub.dds r0, r1, r2
-       fsub.ddd r0, r1, r2
-
-       ;; exchange floating point control register
-
-       fxcr r0, r1, fcr50
-
-       ;; round floating point to integer
-
-       int.ss r0, r1
-       int.sd r10, r2
-
-       ;; unconditional jump
-
-       jmp   r0
-       jmp.n r10
-
-       ;; jump to subroutine
-
-       jsr   r10
-       jsr.n r13
-
-       ;; load register from memory
-
-       ;; unscaled
-       ld.b    r0, r1, 0
-       ld.b    r0, r1, 4096
-       ld.bu   r0, r1, 0
-       ld.bu   r0, r1, 4096
-       ld.h    r0, r1, 0
-       ld.h    r0, r1, 4096
-       ld.hu   r0, r1, 0
-       ld.hu   r0, r1, 4096
-       ld      r0, r1, 0
-       ld      r0, r1, 4096
-       ld.d    r0, r1, 0
-       ld.d    r0, r1, 4096
-       ;; unscaled
-       ld.b      r0, r1, r2
-       ld.bu     r1, r2, r3
-       ld.h      r2, r3, r4
-       ld.hu     r3, r4, r5
-       ld        r4, r5, r6
-       ld.d      r5, r6, r7
-       ld.b.usr  r6, r7, r8
-       ld.bu.usr r7, r8, r9
-       ld.h.usr  r8, r9, r1
-       ld.hu.usr r9, r1, r2
-       ld.usr    r1, r2, r3
-       ld.d.usr  r2, r3, r4
-       ;; scaled
-       ld.b      r0, r1[r2]
-       ld.bu     r1, r2[r3]
-       ld.h      r2, r3[r4]
-       ld.hu     r3, r4[r5]
-       ld        r4, r5[r6]
-       ld.d      r5, r6[r7]
-       ld.b.usr  r6, r7[r8]
-       ld.bu.usr r7, r8[r9]
-       ld.h.usr  r8, r9[r1]
-       ld.hu.usr r9, r1[r2]
-       ld.usr    r1, r2[r3]
-       ld.d.usr  r2, r3[r4]
-
-       ;; load address
-
-       lda.h r0, r1[r2]
-       lda   r1,r2[r3]
-       lda.d r2,r3[r4]
-
-       ;; load from control register
-
-       ldcr r0, cr10
-
-       ;; make bit field
-
-       mak r0, r1, 10<5>
-       mak r0, r1, r2
-       mak r0, r1, 6
-       mak r0, r1, <6>
-       
-       ;; logical mask immediate
-
-       mask   r0, r1, 0
-       mask   r0, r1, 4096
-       mask.u r0, r1, 0
-       mask.u r0, r1, 4096
-
-       ;; integer multiply
-
-       mul r0, r1, r2
-       mul r0, r1, 0
-       mul r0, r1, 4096
-
-       ;; floating point round to nearest integer
-
-       nint.ss r0, r10
-       nint.sd r10, r12
-
-       ;; logical or
-
-       or   r0, r1, r2
-       or.c r1, r7, r10
-       or   r0, r4, 0
-       or   r0, r4, 4096
-       or.u r0, r1, 0
-       or.u r2, r4, 4096
-
-       ;; rotate register
-
-       rot r0, r1,<5>
-       rot r2, r4, r6
-       
-       ;; return from exception
-
-       rte
-
-       ;; set bit field
-
-       set r0, r1, 10<5>
-       set r2, r4, r6
-       set r3, r7, 6
-       set r3, r7, <6>
-       
-       ;; store register to memory
-
-       ;; unscaled
-       st.b    r0, r1, 0
-       st.b    r0, r1, 4096
-       st.h    r0, r1, 0
-       st.h    r0, r1, 4096
-       st      r0, r1, 0
-       st      r0, r1, 4096
-       st.d    r0, r1, 0
-       st.d    r0, r1, 4096
-       ;; unscaled
-       st.b      r0, r1, r2
-       st.h      r2, r3, r4
-       st        r4, r5, r6
-       st.d      r5, r6, r7
-       st.b.usr  r6, r7, r8
-       st.h.usr  r8, r9, r1
-       st.usr    r1, r2, r3
-       st.d.usr  r2, r3, r4
-       ;; scaled
-       st.b      r0, r1[r2]
-       st.h      r2, r3[r4]
-       st        r4, r5[r6]
-       st.d      r5, r6[r7]
-       st.b.usr  r6, r7[r8]
-       st.h.usr  r8, r9[r1]
-       st.usr    r1, r2[r3]
-       st.d.usr  r2, r3[r4]
-
-       ;; store to control register
-
-       stcr r0, cr10
-
-       ;; integer subtract
-
-       sub     r0, r1, r2
-       sub.ci  r1, r2, r3
-       sub.co  r2, r3, r4
-       sub.cio r3, r4, r5
-       sub     r4, r5, 0
-       sub     r4, r5, 4096
-
-       ;; unsigned integer subtract
-
-       subu     r0, r1, r2
-       subu.ci  r1, r2, r3
-       subu.co  r3, r4, r5
-       subu.cio r4, r5, r6
-       subu     r5, r6, 0
-       subu     r5, r6, 4096
-
-       ;; trap on bit clear
-
-       tb0     0, r10, 10
-       tb0     31, r11, 10
-
-       ;; trap on bit set
-
-       tb1     0, r10, 10
-       tb1     31, r11, 10
-
-       ;; trap on bounds check
-
-       tbnd r0, r1
-       tbnd r7, 0
-       tbnd r7, 4096
-
-       ;; conditional trap
-
-       tcnd  eq0, r10, 12
-       tcnd  ne0, r9, 12
-       tcnd  gt0, r8, 7
-       tcnd  lt0, r7, 1
-       tcnd  ge0, r6, 35
-       tcnd  le0, r5, 33
-       tcnd  10, r4, 12
-
-       ;; truncate floating point to integer
-
-       trnc.ss r0, r1
-       trnc.sd r1, r3
-
-       ;; exchange control register
-
-       xcr r0, r3, cr10
-
-       ;; exchange register with memory
-
-       ;; FIXME: these should assemble!
-       ;; xmem.bu    r0, r1, 0
-       ;; xmem.bu     r0, r1, 10
-       ;; xmem     r0, r1, 0
-       ;; xmem     r1, r2, 4096
-       xmem.bu     r0, r1, r2
-       xmem        r1, r2, r3
-       xmem.bu.usr r4, r5, r6
-       xmem.usr    r5, r6, r7
-       xmem.bu     r2, r3[r4]
-       xmem        r3, r4[r5]
-       xmem.bu.usr r4, r5[r9]
-       xmem.usr    r5, r6[r10]
-
-       ;; logical exclusive or
-
-       xor   r0, r1, r2
-       xor.c r1, r2, r3
-       xor   r2, r3, 0
-       xor   r2, r4, 4096
-       xor.u r1, r2, 0
-       xor.u r2, r3, 4096
-       
diff --git a/gas/testsuite/gas/m88k/init.d b/gas/testsuite/gas/m88k/init.d
deleted file mode 100644 (file)
index 20838f2..0000000
+++ /dev/null
@@ -1,10 +0,0 @@
-#objdump: -d --prefix-addresses
-#name: padding of .init section
-
-.*: +file format .*
-
-Disassembly of section .init:
-00000000 <.init> subu        r31,r31,0x10
-00000004 <.init\+0x4> st          r13,r31,0x20
-00000008 <.init\+0x8> or          r0,r0,r0
-0000000c <.init\+0xc> or          r0,r0,r0
diff --git a/gas/testsuite/gas/m88k/init.s b/gas/testsuite/gas/m88k/init.s
deleted file mode 100644 (file)
index 29681cb..0000000
+++ /dev/null
@@ -1,5 +0,0 @@
-; Test proper padding of the .init section
-       section  .init,"x"
-       align    4
-       subu     r31,r31,16
-       st       r13,r31,32
diff --git a/gas/testsuite/gas/m88k/m88k.exp b/gas/testsuite/gas/m88k/m88k.exp
deleted file mode 100644 (file)
index 9aede9c..0000000
+++ /dev/null
@@ -1,26 +0,0 @@
-# Copyright 2001 Free Software Foundation, Inc.
-
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
-
-# Tests for m88k svr3 targets
-
-if { [istarget m88*-*-sysv3] || [istarget m88*-*-coff* ] } then {
-    set testname "Proper padding of .init section"
-    run_dump_test init
-    set testname "All m88k instructions assemble and disassemble"
-    run_dump_test allinsn
-}
-
-if [info exists errorInfo] then { unset errorInfo }
diff --git a/gas/testsuite/gas/tic80/add.d b/gas/testsuite/gas/tic80/add.d
deleted file mode 100644 (file)
index 3dec707..0000000
+++ /dev/null
@@ -1,22 +0,0 @@
-#objdump: -d
-#name: TIc80 signed and unsigned add instructions
-
-.*: +file format .*tic80.*
-
-Disassembly of section .text:
-
-00000000 <.text>:
-   0:  0a 00 fb 62.*
-   4:  ff 3f ac 20.*
-   8:  00 40 2c 21.*
-   c:  00 10 7b 31 00 40 00 00.*
-  14:  00 10 fb 41 ff bf ff ff.*
-  1c:  00 10 bb 5a ff ff ff 7f.*
-  24:  00 10 3b 6b 00 00 00 80.*
-  2c:  0a 20 fb 62.*
-  30:  ff bf ac 20.*
-  34:  00 c0 2c 21.*
-  38:  00 30 7b 31 00 40 00 00.*
-  40:  00 30 fb 41 ff bf ff ff.*
-  48:  00 30 bb 5a ff ff ff 7f.*
-  50:  00 30 3b 6b 00 00 00 80.*
diff --git a/gas/testsuite/gas/tic80/add.lst b/gas/testsuite/gas/tic80/add.lst
deleted file mode 100644 (file)
index e12b368..0000000
+++ /dev/null
@@ -1,34 +0,0 @@
-MVP MP Macro Assembler     Version 1.13     Mon Feb 10 20:13:33 1997
-Copyright (c) 1993-1995    Texas Instruments Incorporated 
-
-add.s                                                                PAGE    1
-
-        1                     ; Test signed and unsigned addition instruction.
-        2                     ; Test boundary conditions to ensure proper handling.
-        3                     ; Note that unsigned addition still uses signed immediates.
-        4                     
-        5 00000000   62FB000A         add     r10,r11,r12             ; Register form
-        6 00000004   20AC3FFF         add     16383,r2,r4             ; Maximum positive short signed immediate
-        7 00000008   212C4000         add     -16384,r4,r4            ; Minimum negative short signed immediate
-        8 0000000C   317B1000         add     16384,r5,r6             ; Minimum positive long signed immediate
-          00000010   00004000 
-        9 00000014   41FB1000         add     -16385,r7,r8            ; Maximum negative short signed immediate
-          00000018   FFFFBFFF 
-       10 0000001C   5ABB1000         add     2147483647,r10,r11      ; Maximum positive long signed immediate
-          00000020   7FFFFFFF 
-       11 00000024   6B3B1000         add     -2147483648,r12,r13     ; Minimum positive long signed immediate
-          00000028   80000000 
-       12                     
-       13 0000002C   62FB200A         addu    r10,r11,r12             ; Register form
-       14 00000030   20ACBFFF         addu    16383,r2,r4             ; Maximum positive short signed immediate
-       15 00000034   212CC000         addu    -16384,r4,r4            ; Minimum negative short signed immediate
-       16 00000038   317B3000         addu    16384,r5,r6             ; Minimum positive long signed immediate
-          0000003C   00004000 
-       17 00000040   41FB3000         addu    -16385,r7,r8            ; Maximum negative short signed immediate
-          00000044   FFFFBFFF 
-       18 00000048   5ABB3000         addu    2147483647,r10,r11      ; Maximum positive long signed immediate
-          0000004C   7FFFFFFF 
-       19 00000050   6B3B3000         addu    -2147483648,r12,r13     ; Minimum positive long signed immediate
-          00000054   80000000 
-
- No Errors,  No Warnings
diff --git a/gas/testsuite/gas/tic80/add.s b/gas/testsuite/gas/tic80/add.s
deleted file mode 100644 (file)
index 6c229ed..0000000
+++ /dev/null
@@ -1,19 +0,0 @@
-; Test signed and unsigned addition instruction.
-; Test boundary conditions to ensure proper handling.
-; Note that unsigned addition still uses signed immediates.
-
-       add     r10,r11,r12             ; Register form
-       add     16383,r2,r4             ; Maximum positive short signed immediate
-       add     -16384,r4,r4            ; Minimum negative short signed immediate
-       add     16384,r5,r6             ; Minimum positive long signed immediate
-       add     -16385,r7,r8            ; Maximum negative long signed immediate
-       add     2147483647,r10,r11      ; Maximum positive long signed immediate
-       add     -2147483648,r12,r13     ; Minimum negative long signed immediate
-
-       addu    r10,r11,r12             ; Register form
-       addu    16383,r2,r4             ; Maximum positive short signed immediate
-       addu    -16384,r4,r4            ; Minimum negative short signed immediate
-       addu    16384,r5,r6             ; Minimum positive long signed immediate
-       addu    -16385,r7,r8            ; Maximum negative long signed immediate
-       addu    2147483647,r10,r11      ; Maximum positive long signed immediate
-       addu    -2147483648,r12,r13     ; Minimum negative long signed immediate
diff --git a/gas/testsuite/gas/tic80/align.d b/gas/testsuite/gas/tic80/align.d
deleted file mode 100644 (file)
index 88f9610..0000000
+++ /dev/null
@@ -1,19 +0,0 @@
-#objdump: -d
-#name: TIc80 .align pseudo op
-
-.*: +file format .*tic80.*
-
-Disassembly of section .text:
-
-00000000 <.text>:
-   0:  ab 00 00 00.*
-   4:  cd 00 ef 00.*
-   8:  f1 00 00 00.*
-   c:  ee 00 00 00.*
-  10:  ac 00 00 00.*
-  14:  00 00 00 00.*
-  18:  ab 00 00 00.*
-  1c:  00 00 00 00.*
-  20:  fe 00 00 00.*
-       \.\.\.
-  30:  de ad be ef.*
diff --git a/gas/testsuite/gas/tic80/align.lst b/gas/testsuite/gas/tic80/align.lst
deleted file mode 100644 (file)
index 915415a..0000000
+++ /dev/null
@@ -1,47 +0,0 @@
-MVP MP Macro Assembler     Version 1.13     Thu Feb 27 17:02:23 1997
-Copyright (c) 1993-1995    Texas Instruments Incorporated 
-
-align.s                                                              PAGE    1
-
-        1                     ;;      Test the .align directive.
-        2                     
-        3 00000000                    .text
-        4                             
-        5                             ;; This should generate 0xAB000000
-        6 00000000   AB               .byte   0xAB
-        7 00000001                    .align                  ; Should default to 4 byte alignment
-        8                     
-        9                             ;; This should generate 0xCD00EF00
-       10 00000004   CD               .byte   0xCD
-       11                             .align  2               ;  Should align to the next 2-byte boundary (pad with one null byt
-       12 00000006   EF               .byte   0xEF
-       13                             .align  1
-       14                     
-       15                             ;; This should generate 0xF1000000
-       16 00000007                    .align  4               ;  Should not affect alignment (already on 4)
-       17 00000008   F1               .byte   0xF1
-       18 00000009                    .align  4               ;  Should align to next 4 byte boundary
-       19                     
-       20                             ;; This should generate 0xEE000000 since we are already on 4 byte alignment
-       21 0000000C   EE               .byte 0xEE
-       22 0000000D                    .align  8
-       23                     
-       24                             ;; This should generate 0xAC000000 0x00000000
-       25 00000010   AC               .byte   0xAC
-       26 00000011                    .align  8
-       27                             
-       28                             ;; This should generate 0xAB000000 0x00000000 since we are at 8 byte alignment
-       29 00000018   AB               .byte   0xAB
-       30 00000019                    .align  16
-       31                     
-       32                             ;; This should generate 0xFE000000 0x00000000 0x00000000 0x00000000
-       33 00000020   FE               .byte   0xFE
-       34 00000021                    .align  16
-       35                             
-       36                             ;; This just forces the disassembler to not print ... for trailing nulls
-       37 00000030   DE               .byte 0xDE, 0xAD, 0xBE, 0xEF
-          00000031   AD       
-          00000032   BE       
-          00000033   EF       
-
- No Errors,  No Warnings
diff --git a/gas/testsuite/gas/tic80/align.s b/gas/testsuite/gas/tic80/align.s
deleted file mode 100644 (file)
index 02c1256..0000000
+++ /dev/null
@@ -1,37 +0,0 @@
-;;     Test the .align directive.
-
-       .text
-       
-       ;; This should generate 0xAB000000
-       .byte   0xAB
-       .align                  ; Should default to 4 byte alignment
-
-       ;; This should generate 0xCD00EF00
-       .byte   0xCD
-       .align  2               ;  Should align to the next 2-byte boundary (pad with one null byte)
-       .byte   0xEF
-       .align  1
-
-       ;; This should generate 0xF1000000
-       .align  4               ;  Should not affect alignment (already on 4)
-       .byte   0xF1
-       .align  4               ;  Should align to next 4 byte boundary
-
-       ;; This should generate 0xEE000000 since we are already on 4 byte alignment
-       .byte 0xEE
-       .align  8
-
-       ;; This should generate 0xAC000000 0x00000000
-       .byte   0xAC
-       .align  8
-       
-       ;; This should generate 0xAB000000 0x00000000 since we are at 8 byte alignment
-       .byte   0xAB
-       .align  16
-
-       ;; This should generate 0xFE000000 0x00000000 0x00000000 0x00000000
-       .byte   0xFE
-       .align  16
-       
-       ;; This just forces the disassembler to not print ... for trailing nulls
-       .byte 0xDE, 0xAD, 0xBE, 0xEF
diff --git a/gas/testsuite/gas/tic80/bitnum.d b/gas/testsuite/gas/tic80/bitnum.d
deleted file mode 100644 (file)
index fcaee8b..0000000
+++ /dev/null
@@ -1,82 +0,0 @@
-#objdump: -d
-#name: TIc80 coverage of symbolic BITNUM values
-
-.*: +file format .*tic80.*
-
-Disassembly of section .text:
-
-00000000 <.text>:
-   0:  0a 40 39 fa.*
-   4:  0a 40 39 f2.*
-   8:  0a 40 39 ea.*
-   c:  0a 40 39 e2.*
-  10:  0a 40 39 da.*
-  14:  0a 40 39 d2.*
-  18:  0a 40 39 ca.*
-  1c:  0a 40 39 c2.*
-  20:  0a 40 39 ba.*
-  24:  0a 40 39 b2.*
-  28:  0a 40 39 aa.*
-  2c:  0a 40 39 a2.*
-  30:  0a 40 39 9a.*
-  34:  0a 40 39 92.*
-  38:  0a 40 39 8a.*
-  3c:  0a 40 39 82.*
-  40:  0a 40 39 7a.*
-  44:  0a 40 39 72.*
-  48:  0a 40 39 6a.*
-  4c:  0a 40 39 62.*
-  50:  0a 40 39 5a.*
-  54:  0a 40 39 52.*
-  58:  0a 40 39 4a.*
-  5c:  0a 40 39 42.*
-  60:  0a 40 39 3a.*
-  64:  0a 40 39 32.*
-  68:  0a 40 39 2a.*
-  6c:  0a 40 39 22.*
-  70:  0a 40 39 1a.*
-  74:  0a 40 39 12.*
-  78:  0a 40 39 5a.*
-  7c:  0a 40 39 52.*
-  80:  0a 40 39 4a.*
-  84:  0a 40 39 42.*
-  88:  0a 40 39 3a.*
-  8c:  0a 40 39 32.*
-  90:  0a 40 39 2a.*
-  94:  0a 40 39 22.*
-  98:  0a 40 39 1a.*
-  9c:  0a 40 39 12.*
-  a0:  0a 40 39 0a.*
-  a4:  0a 40 39 02.*
-  a8:  0a 40 39 fa.*
-  ac:  0a 40 39 f2.*
-  b0:  0a 40 39 ea.*
-  b4:  0a 40 39 e2.*
-  b8:  0a 40 39 da.*
-  bc:  0a 40 39 d2.*
-  c0:  0a 40 39 ca.*
-  c4:  0a 40 39 c2.*
-  c8:  0a 40 39 ba.*
-  cc:  0a 40 39 b2.*
-  d0:  0a 40 39 aa.*
-  d4:  0a 40 39 a2.*
-  d8:  0a 40 39 9a.*
-  dc:  0a 40 39 92.*
-  e0:  0a 40 39 8a.*
-  e4:  0a 40 39 82.*
-  e8:  0a 40 39 7a.*
-  ec:  0a 40 39 72.*
-  f0:  0a 40 39 6a.*
-  f4:  0a 40 39 62.*
-  f8:  0a 40 39 5a.*
-  fc:  0a 40 39 52.*
- 100:  0a 40 39 4a.*
- 104:  0a 40 39 42.*
- 108:  0a 40 39 3a.*
- 10c:  0a 40 39 32.*
- 110:  0a 40 39 2a.*
- 114:  0a 40 39 22.*
- 118:  0a 40 39 1a.*
- 11c:  0a 40 39 12.*
- 120:  0a 40 39 0a.*
- 124:  0a 40 39 02.*
diff --git a/gas/testsuite/gas/tic80/bitnum.lst b/gas/testsuite/gas/tic80/bitnum.lst
deleted file mode 100644 (file)
index acc268b..0000000
+++ /dev/null
@@ -1,97 +0,0 @@
-MVP MP Macro Assembler     Version 1.13     Sat Feb 22 21:37:15 1997
-Copyright (c) 1993-1995    Texas Instruments Incorporated 
-
-bitnum.s                                                             PAGE    1
-
-        1                     ;; Test that all the predefined symbol names for the BITNUM field
-        2                     ;; are properly accepted and translated to numeric values.  Also
-        3                     ;; verifies that they are disassembled correctly as symbolics, and
-        4                     ;; that the raw numeric values are handled correctly (stored as
-        5                     ;; the one's complement of the operand numeric value.
-        6                     
-        7 00000000   FA39400A         bbo     r10,r8,eq.b     ; (~0 & 0x1F)
-        8 00000004   F239400A         bbo     r10,r8,ne.b     ; (~1 & 0x1F)
-        9 00000008   EA39400A         bbo     r10,r8,gt.b     ; (~2 & 0x1F)
-       10 0000000C   E239400A         bbo     r10,r8,le.b     ; (~3 & 0x1F)
-       11 00000010   DA39400A         bbo     r10,r8,lt.b     ; (~4 & 0x1F)
-       12 00000014   D239400A         bbo     r10,r8,ge.b     ; (~5 & 0x1F)
-       13 00000018   CA39400A         bbo     r10,r8,hi.b     ; (~6 & 0x1F)
-       14 0000001C   C239400A         bbo     r10,r8,ls.b     ; (~7 & 0x1F)
-       15 00000020   BA39400A         bbo     r10,r8,lo.b     ; (~8 & 0x1F)
-       16 00000024   B239400A         bbo     r10,r8,hs.b     ; (~9 & 0x1F)
-       17                     
-       18 00000028   AA39400A         bbo     r10,r8,eq.h     ; (~10 & 0x1F)
-       19 0000002C   A239400A         bbo     r10,r8,ne.h     ; (~11 & 0x1F)
-       20 00000030   9A39400A         bbo     r10,r8,gt.h     ; (~12 & 0x1F)
-       21 00000034   9239400A         bbo     r10,r8,le.h     ; (~13 & 0x1F)
-       22 00000038   8A39400A         bbo     r10,r8,lt.h     ; (~14 & 0x1F)
-       23 0000003C   8239400A         bbo     r10,r8,ge.h     ; (~15 & 0x1F)
-       24 00000040   7A39400A         bbo     r10,r8,hi.h     ; (~16 & 0x1F)
-       25 00000044   7239400A         bbo     r10,r8,ls.h     ; (~17 & 0x1F)
-       26 00000048   6A39400A         bbo     r10,r8,lo.h     ; (~18 & 0x1F)
-       27 0000004C   6239400A         bbo     r10,r8,hs.h     ; (~19 & 0x1F)
-       28                     
-       29 00000050   5A39400A         bbo     r10,r8,eq.w     ; (~20 & 0x1F)
-       30 00000054   5239400A         bbo     r10,r8,ne.w     ; (~21 & 0x1F)
-       31 00000058   4A39400A         bbo     r10,r8,gt.w     ; (~22 & 0x1F)
-       32 0000005C   4239400A         bbo     r10,r8,le.w     ; (~23 & 0x1F)
-       33 00000060   3A39400A         bbo     r10,r8,lt.w     ; (~24 & 0x1F)
-       34 00000064   3239400A         bbo     r10,r8,ge.w     ; (~25 & 0x1F)
-       35 00000068   2A39400A         bbo     r10,r8,hi.w     ; (~26 & 0x1F)
-       36 0000006C   2239400A         bbo     r10,r8,ls.w     ; (~27 & 0x1F)
-       37 00000070   1A39400A         bbo     r10,r8,lo.w     ; (~28 & 0x1F)
-       38 00000074   1239400A         bbo     r10,r8,hs.w     ; (~29 & 0x1F)
-       39                     
-       40 00000078   5A39400A         bbo     r10,r8,eq.f     ; (~20 & 0x1F)
-       41 0000007C   5239400A         bbo     r10,r8,ne.f     ; (~21 & 0x1F)
-       42 00000080   4A39400A         bbo     r10,r8,gt.f     ; (~22 & 0x1F)
-       43 00000084   4239400A         bbo     r10,r8,le.f     ; (~23 & 0x1F)
-       44 00000088   3A39400A         bbo     r10,r8,lt.f     ; (~24 & 0x1F)
-       45 0000008C   3239400A         bbo     r10,r8,ge.f     ; (~25 & 0x1F)
-       46 00000090   2A39400A         bbo     r10,r8,ou.f     ; (~26 & 0x1F)
-       47 00000094   2239400A         bbo     r10,r8,in.f     ; (~27 & 0x1F)
-       48 00000098   1A39400A         bbo     r10,r8,ib.f     ; (~28 & 0x1F)
-       49 0000009C   1239400A         bbo     r10,r8,ob.f     ; (~29 & 0x1F)
-       50 000000A0   0A39400A         bbo     r10,r8,uo.f     ; (~30 & 0x1F)
-       51 000000A4   0239400A         bbo     r10,r8,or.f     ; (~31 & 0x1F)
-       52                     
-       53 000000A8   FA39400A         bbo     r10,r8,0
-       54 000000AC   F239400A         bbo     r10,r8,1
-       55 000000B0   EA39400A         bbo     r10,r8,2
-\fMVP MP Macro Assembler     Version 1.13     Sat Feb 22 21:37:15 1997
-Copyright (c) 1993-1995    Texas Instruments Incorporated 
-
-bitnum.s                                                             PAGE    2
-
-       56 000000B4   E239400A         bbo     r10,r8,3
-       57 000000B8   DA39400A         bbo     r10,r8,4
-       58 000000BC   D239400A         bbo     r10,r8,5
-       59 000000C0   CA39400A         bbo     r10,r8,6
-       60 000000C4   C239400A         bbo     r10,r8,7
-       61 000000C8   BA39400A         bbo     r10,r8,8
-       62 000000CC   B239400A         bbo     r10,r8,9
-       63 000000D0   AA39400A         bbo     r10,r8,10
-       64 000000D4   A239400A         bbo     r10,r8,11
-       65 000000D8   9A39400A         bbo     r10,r8,12
-       66 000000DC   9239400A         bbo     r10,r8,13
-       67 000000E0   8A39400A         bbo     r10,r8,14
-       68 000000E4   8239400A         bbo     r10,r8,15
-       69 000000E8   7A39400A         bbo     r10,r8,16
-       70 000000EC   7239400A         bbo     r10,r8,17
-       71 000000F0   6A39400A         bbo     r10,r8,18
-       72 000000F4   6239400A         bbo     r10,r8,19
-       73 000000F8   5A39400A         bbo     r10,r8,20
-       74 000000FC   5239400A         bbo     r10,r8,21
-       75 00000100   4A39400A         bbo     r10,r8,22
-       76 00000104   4239400A         bbo     r10,r8,23
-       77 00000108   3A39400A         bbo     r10,r8,24
-       78 0000010C   3239400A         bbo     r10,r8,25
-       79 00000110   2A39400A         bbo     r10,r8,26
-       80 00000114   2239400A         bbo     r10,r8,27
-       81 00000118   1A39400A         bbo     r10,r8,28
-       82 0000011C   1239400A         bbo     r10,r8,29
-       83 00000120   0A39400A         bbo     r10,r8,30
-       84 00000124   0239400A         bbo     r10,r8,31
-       85                     
-
- No Errors,  No Warnings
diff --git a/gas/testsuite/gas/tic80/bitnum.s b/gas/testsuite/gas/tic80/bitnum.s
deleted file mode 100644 (file)
index 2526e06..0000000
+++ /dev/null
@@ -1,85 +0,0 @@
-;; Test that all the predefined symbol names for the BITNUM field
-;; are properly accepted and translated to numeric values.  Also
-;; verifies that they are disassembled correctly as symbolics, and
-;; that the raw numeric values are handled correctly (stored as
-;; the one's complement of the operand numeric value.
-
-       bbo     r10,r8,eq.b     ; (~0 & 0x1F)
-       bbo     r10,r8,ne.b     ; (~1 & 0x1F)
-       bbo     r10,r8,gt.b     ; (~2 & 0x1F)
-       bbo     r10,r8,le.b     ; (~3 & 0x1F)
-       bbo     r10,r8,lt.b     ; (~4 & 0x1F)
-       bbo     r10,r8,ge.b     ; (~5 & 0x1F)
-       bbo     r10,r8,hi.b     ; (~6 & 0x1F)
-       bbo     r10,r8,ls.b     ; (~7 & 0x1F)
-       bbo     r10,r8,lo.b     ; (~8 & 0x1F)
-       bbo     r10,r8,hs.b     ; (~9 & 0x1F)
-
-       bbo     r10,r8,eq.h     ; (~10 & 0x1F)
-       bbo     r10,r8,ne.h     ; (~11 & 0x1F)
-       bbo     r10,r8,gt.h     ; (~12 & 0x1F)
-       bbo     r10,r8,le.h     ; (~13 & 0x1F)
-       bbo     r10,r8,lt.h     ; (~14 & 0x1F)
-       bbo     r10,r8,ge.h     ; (~15 & 0x1F)
-       bbo     r10,r8,hi.h     ; (~16 & 0x1F)
-       bbo     r10,r8,ls.h     ; (~17 & 0x1F)
-       bbo     r10,r8,lo.h     ; (~18 & 0x1F)
-       bbo     r10,r8,hs.h     ; (~19 & 0x1F)
-
-       bbo     r10,r8,eq.w     ; (~20 & 0x1F)
-       bbo     r10,r8,ne.w     ; (~21 & 0x1F)
-       bbo     r10,r8,gt.w     ; (~22 & 0x1F)
-       bbo     r10,r8,le.w     ; (~23 & 0x1F)
-       bbo     r10,r8,lt.w     ; (~24 & 0x1F)
-       bbo     r10,r8,ge.w     ; (~25 & 0x1F)
-       bbo     r10,r8,hi.w     ; (~26 & 0x1F)
-       bbo     r10,r8,ls.w     ; (~27 & 0x1F)
-       bbo     r10,r8,lo.w     ; (~28 & 0x1F)
-       bbo     r10,r8,hs.w     ; (~29 & 0x1F)
-
-       bbo     r10,r8,eq.f     ; (~20 & 0x1F)
-       bbo     r10,r8,ne.f     ; (~21 & 0x1F)
-       bbo     r10,r8,gt.f     ; (~22 & 0x1F)
-       bbo     r10,r8,le.f     ; (~23 & 0x1F)
-       bbo     r10,r8,lt.f     ; (~24 & 0x1F)
-       bbo     r10,r8,ge.f     ; (~25 & 0x1F)
-       bbo     r10,r8,ou.f     ; (~26 & 0x1F)
-       bbo     r10,r8,in.f     ; (~27 & 0x1F)
-       bbo     r10,r8,ib.f     ; (~28 & 0x1F)
-       bbo     r10,r8,ob.f     ; (~29 & 0x1F)
-       bbo     r10,r8,uo.f     ; (~30 & 0x1F)
-       bbo     r10,r8,or.f     ; (~31 & 0x1F)
-
-       bbo     r10,r8,0
-       bbo     r10,r8,1
-       bbo     r10,r8,2
-       bbo     r10,r8,3
-       bbo     r10,r8,4
-       bbo     r10,r8,5
-       bbo     r10,r8,6
-       bbo     r10,r8,7
-       bbo     r10,r8,8
-       bbo     r10,r8,9
-       bbo     r10,r8,10
-       bbo     r10,r8,11
-       bbo     r10,r8,12
-       bbo     r10,r8,13
-       bbo     r10,r8,14
-       bbo     r10,r8,15
-       bbo     r10,r8,16
-       bbo     r10,r8,17
-       bbo     r10,r8,18
-       bbo     r10,r8,19
-       bbo     r10,r8,20
-       bbo     r10,r8,21
-       bbo     r10,r8,22
-       bbo     r10,r8,23
-       bbo     r10,r8,24
-       bbo     r10,r8,25
-       bbo     r10,r8,26
-       bbo     r10,r8,27
-       bbo     r10,r8,28
-       bbo     r10,r8,29
-       bbo     r10,r8,30
-       bbo     r10,r8,31
-
diff --git a/gas/testsuite/gas/tic80/ccode.d b/gas/testsuite/gas/tic80/ccode.d
deleted file mode 100644 (file)
index b5a38aa..0000000
+++ /dev/null
@@ -1,32 +0,0 @@
-#objdump: -d
-#name: TIc80 coverage of symbolic condition code values
-
-.*: +file format .*tic80.*
-
-Disassembly of section .text:
-
-00000000 <.text>:
-   0:  07 a0 79 01.*
-   4:  07 a0 79 09.*
-   8:  07 a0 79 11.*
-   c:  07 a0 79 19.*
-  10:  07 a0 79 21.*
-  14:  07 a0 79 29.*
-  18:  07 a0 79 31.*
-  1c:  07 a0 79 39.*
-  20:  07 a0 79 41.*
-  24:  07 a0 79 49.*
-  28:  07 a0 79 51.*
-  2c:  07 a0 79 59.*
-  30:  07 a0 79 61.*
-  34:  07 a0 79 69.*
-  38:  07 a0 79 71.*
-  3c:  07 a0 79 79.*
-  40:  07 a0 79 81.*
-  44:  07 a0 79 89.*
-  48:  07 a0 79 91.*
-  4c:  07 a0 79 99.*
-  50:  07 a0 79 a1.*
-  54:  07 a0 79 a9.*
-  58:  07 a0 79 b1.*
-  5c:  07 a0 79 b9.*
diff --git a/gas/testsuite/gas/tic80/ccode.lst b/gas/testsuite/gas/tic80/ccode.lst
deleted file mode 100644 (file)
index 460351c..0000000
+++ /dev/null
@@ -1,37 +0,0 @@
-MVP MP Macro Assembler     Version 1.13     Mon Feb 10 17:00:49 1997
-Copyright (c) 1993-1995    Texas Instruments Incorporated 
-
-ccode.s                                                              PAGE    1
-
-        1                     ;; Test that all the predefined symbol names for the condition
-        2                     ;; codes are properly accepted and translated to numeric values.
-        3                     ;;  Also verifies that they are disassembled correctly as symbolics.
-        4                     
-        5 00000000   0179A007         bcnd.a  r7,r5,nev.b             ; 00000
-        6 00000004   0979A007         bcnd.a  r7,r5,gt0.b             ; 00001
-        7 00000008   1179A007         bcnd.a  r7,r5,eq0.b             ; 00010
-        8 0000000C   1979A007         bcnd.a  r7,r5,ge0.b             ; 00011
-        9 00000010   2179A007         bcnd.a  r7,r5,lt0.b             ; 00100
-       10 00000014   2979A007         bcnd.a  r7,r5,ne0.b             ; 00101
-       11 00000018   3179A007         bcnd.a  r7,r5,le0.b             ; 00110
-       12 0000001C   3979A007         bcnd.a  r7,r5,alw.b             ; 00111
-       13                     
-       14 00000020   4179A007         bcnd.a  r7,r5,nev.h             ; 01000
-       15 00000024   4979A007         bcnd.a  r7,r5,gt0.h             ; 01001
-       16 00000028   5179A007         bcnd.a  r7,r5,eq0.h             ; 01010
-       17 0000002C   5979A007         bcnd.a  r7,r5,ge0.h             ; 01011
-       18 00000030   6179A007         bcnd.a  r7,r5,lt0.h             ; 01100
-       19 00000034   6979A007         bcnd.a  r7,r5,ne0.h             ; 01101
-       20 00000038   7179A007         bcnd.a  r7,r5,le0.h             ; 01110
-       21 0000003C   7979A007         bcnd.a  r7,r5,alw.h             ; 01111
-       22                     
-       23 00000040   8179A007         bcnd.a  r7,r5,nev.w             ; 10000
-       24 00000044   8979A007         bcnd.a  r7,r5,gt0.w             ; 10001
-       25 00000048   9179A007         bcnd.a  r7,r5,eq0.w             ; 10010
-       26 0000004C   9979A007         bcnd.a  r7,r5,ge0.w             ; 10011
-       27 00000050   A179A007         bcnd.a  r7,r5,lt0.w             ; 10100
-       28 00000054   A979A007         bcnd.a  r7,r5,ne0.w             ; 10101
-       29 00000058   B179A007         bcnd.a  r7,r5,le0.w             ; 10110
-       30 0000005C   B979A007         bcnd.a  r7,r5,alw.w             ; 10111
-
- No Errors,  No Warnings
diff --git a/gas/testsuite/gas/tic80/ccode.s b/gas/testsuite/gas/tic80/ccode.s
deleted file mode 100644 (file)
index 9e4aac1..0000000
+++ /dev/null
@@ -1,30 +0,0 @@
-;; Test that all the predefined symbol names for the condition
-;; codes are properly accepted and translated to numeric values.
-;;  Also verifies that they are disassembled correctly as symbolics.
-
-       bcnd.a  r7,r5,nev.b             ; 00000
-       bcnd.a  r7,r5,gt0.b             ; 00001
-       bcnd.a  r7,r5,eq0.b             ; 00010
-       bcnd.a  r7,r5,ge0.b             ; 00011
-       bcnd.a  r7,r5,lt0.b             ; 00100
-       bcnd.a  r7,r5,ne0.b             ; 00101
-       bcnd.a  r7,r5,le0.b             ; 00110
-       bcnd.a  r7,r5,alw.b             ; 00111
-
-       bcnd.a  r7,r5,nev.h             ; 01000
-       bcnd.a  r7,r5,gt0.h             ; 01001
-       bcnd.a  r7,r5,eq0.h             ; 01010
-       bcnd.a  r7,r5,ge0.h             ; 01011
-       bcnd.a  r7,r5,lt0.h             ; 01100
-       bcnd.a  r7,r5,ne0.h             ; 01101
-       bcnd.a  r7,r5,le0.h             ; 01110
-       bcnd.a  r7,r5,alw.h             ; 01111
-
-       bcnd.a  r7,r5,nev.w             ; 10000
-       bcnd.a  r7,r5,gt0.w             ; 10001
-       bcnd.a  r7,r5,eq0.w             ; 10010
-       bcnd.a  r7,r5,ge0.w             ; 10011
-       bcnd.a  r7,r5,lt0.w             ; 10100
-       bcnd.a  r7,r5,ne0.w             ; 10101
-       bcnd.a  r7,r5,le0.w             ; 10110
-       bcnd.a  r7,r5,alw.w             ; 10111
diff --git a/gas/testsuite/gas/tic80/cregops.d b/gas/testsuite/gas/tic80/cregops.d
deleted file mode 100644 (file)
index 44b61e9..0000000
+++ /dev/null
@@ -1,68 +0,0 @@
-#objdump: -d
-#name: TIc80 control register operands
-
-.*: +file format .*tic80.*
-
-Disassembly of section .text:
-
-00000000 <.text>:
-   0:  34 00 02 10.*
-   4:  39 00 02 10.*
-   8:  3a 00 02 10.*
-   c:  02 00 02 10.*
-  10:  00 05 02 10.*
-  14:  00 04 02 10.*
-  18:  01 04 02 10.*
-  1c:  0a 04 02 10.*
-  20:  0b 04 02 10.*
-  24:  0c 04 02 10.*
-  28:  0d 04 02 10.*
-  2c:  0e 04 02 10.*
-  30:  0f 04 02 10.*
-  34:  02 04 02 10.*
-  38:  03 04 02 10.*
-  3c:  04 04 02 10.*
-  40:  05 04 02 10.*
-  44:  06 04 02 10.*
-  48:  07 04 02 10.*
-  4c:  08 04 02 10.*
-  50:  09 04 02 10.*
-  54:  33 00 02 10.*
-  58:  01 00 02 10.*
-  5c:  00 00 02 10.*
-  60:  11 00 02 10.*
-  64:  14 00 02 10.*
-  68:  13 00 02 10.*
-  6c:  10 00 02 10.*
-  70:  12 00 02 10.*
-  74:  08 00 02 10.*
-  78:  06 00 02 10.*
-  7c:  00 03 02 10.*
-  80:  00 40 02 10.*
-  84:  01 40 02 10.*
-  88:  04 00 02 10.*
-  8c:  00 02 02 10.*
-  90:  01 02 02 10.*
-  94:  0a 02 02 10.*
-  98:  0b 02 02 10.*
-  9c:  0c 02 02 10.*
-  a0:  0d 02 02 10.*
-  a4:  0e 02 02 10.*
-  a8:  0f 02 02 10.*
-  ac:  02 02 02 10.*
-  b0:  03 02 02 10.*
-  b4:  04 02 02 10.*
-  b8:  05 02 02 10.*
-  bc:  06 02 02 10.*
-  c0:  07 02 02 10.*
-  c4:  08 02 02 10.*
-  c8:  09 02 02 10.*
-  cc:  31 00 02 10.*
-  d0:  30 00 02 10.*
-  d4:  02 40 02 10.*
-  d8:  0d 00 02 10.*
-  dc:  0a 00 02 10.*
-  e0:  20 00 02 10.*
-  e4:  21 00 02 10.*
-  e8:  0e 00 02 10.*
-  ec:  0f 00 02 10.*
diff --git a/gas/testsuite/gas/tic80/cregops.lst b/gas/testsuite/gas/tic80/cregops.lst
deleted file mode 100644 (file)
index 65ea57f..0000000
+++ /dev/null
@@ -1,76 +0,0 @@
-MVP MP Macro Assembler     Version 1.13     Mon Feb 10 17:00:56 1997
-Copyright (c) 1993-1995    Texas Instruments Incorporated 
-
-cregops.s                                                            PAGE    1
-
-        1                     ;; Test that all predefined symbol names for control registers
-        2                     ;; are properly accepted and translated to numeric values.  Also
-        3                     ;; verifies that they are diassembled correctly as symbolics.
-        4                     
-        5 00000000   10020034         rdcr    ANASTAT,r2
-        6 00000004   10020039         rdcr    BRK1,r2
-        7 00000008   1002003A         rdcr    BRK2,r2
-        8 0000000C   10020002         rdcr    CONFIG,r2
-        9 00000010   10020500         rdcr    DLRU,r2
-       10 00000014   10020400         rdcr    DTAG0,r2
-       11 00000018   10020401         rdcr    DTAG1,r2
-       12 0000001C   1002040A         rdcr    DTAG10,r2
-       13 00000020   1002040B         rdcr    DTAG11,r2
-       14 00000024   1002040C         rdcr    DTAG12,r2
-       15 00000028   1002040D         rdcr    DTAG13,r2
-       16 0000002C   1002040E         rdcr    DTAG14,r2
-       17 00000030   1002040F         rdcr    DTAG15,r2
-       18 00000034   10020402         rdcr    DTAG2,r2
-       19 00000038   10020403         rdcr    DTAG3,r2
-       20 0000003C   10020404         rdcr    DTAG4,r2
-       21 00000040   10020405         rdcr    DTAG5,r2
-       22 00000044   10020406         rdcr    DTAG6,r2
-       23 00000048   10020407         rdcr    DTAG7,r2
-       24 0000004C   10020408         rdcr    DTAG8,r2
-       25 00000050   10020409         rdcr    DTAG9,r2
-       26 00000054   10020033         rdcr    ECOMCNTL,r2
-       27 00000058   10020001         rdcr    EIP,r2
-       28 0000005C   10020000         rdcr    EPC,r2
-       29 00000060   10020011         rdcr    FLTADR,r2
-       30 00000064   10020014         rdcr    FLTDTH,r2
-       31 00000068   10020013         rdcr    FLTDTL,r2
-       32 0000006C   10020010         rdcr    FLTOP,r2
-       33 00000070   10020012         rdcr    FLTTAG,r2
-       34 00000074   10020008         rdcr    FPST,r2
-       35 00000078   10020006         rdcr    IE,r2
-       36 0000007C   10020300         rdcr    ILRU,r2
-       37 00000080   10024000         rdcr    IN0P,r2
-       38 00000084   10024001         rdcr    IN1P,r2
-       39 00000088   10020004         rdcr    INTPEN,r2
-       40 0000008C   10020200         rdcr    ITAG0,r2
-       41 00000090   10020201         rdcr    ITAG1,r2
-       42 00000094   1002020A         rdcr    ITAG10,r2
-       43 00000098   1002020B         rdcr    ITAG11,r2
-       44 0000009C   1002020C         rdcr    ITAG12,r2
-       45 000000A0   1002020D         rdcr    ITAG13,r2
-       46 000000A4   1002020E         rdcr    ITAG14,r2
-       47 000000A8   1002020F         rdcr    ITAG15,r2
-       48 000000AC   10020202         rdcr    ITAG2,r2
-       49 000000B0   10020203         rdcr    ITAG3,r2
-       50 000000B4   10020204         rdcr    ITAG4,r2
-       51 000000B8   10020205         rdcr    ITAG5,r2
-       52 000000BC   10020206         rdcr    ITAG6,r2
-       53 000000C0   10020207         rdcr    ITAG7,r2
-       54 000000C4   10020208         rdcr    ITAG8,r2
-       55 000000C8   10020209         rdcr    ITAG9,r2
-\fMVP MP Macro Assembler     Version 1.13     Mon Feb 10 17:00:56 1997
-Copyright (c) 1993-1995    Texas Instruments Incorporated 
-
-cregops.s                                                            PAGE    2
-
-       56 000000CC   10020031         rdcr    MIP,r2
-       57 000000D0   10020030         rdcr    MPC,r2
-       58 000000D4   10024002         rdcr    OUTP,r2
-       59 000000D8   1002000D         rdcr    PKTREQ,r2
-       60 000000DC   1002000A         rdcr    PPERROR,r2
-       61 000000E0   10020020         rdcr    SYSSTK,r2
-       62 000000E4   10020021         rdcr    SYSTMP,r2
-       63 000000E8   1002000E         rdcr    TCOUNT,r2
-       64 000000EC   1002000F         rdcr    TSCALE,r2
-
- No Errors,  No Warnings
diff --git a/gas/testsuite/gas/tic80/cregops.s b/gas/testsuite/gas/tic80/cregops.s
deleted file mode 100644 (file)
index 8a0adcf..0000000
+++ /dev/null
@@ -1,64 +0,0 @@
-;; Test that all predefined symbol names for control registers
-;; are properly accepted and translated to numeric values.  Also
-;; verifies that they are diassembled correctly as symbolics.
-
-       rdcr    ANASTAT,r2
-       rdcr    BRK1,r2
-       rdcr    BRK2,r2
-       rdcr    CONFIG,r2
-       rdcr    DLRU,r2
-       rdcr    DTAG0,r2
-       rdcr    DTAG1,r2
-       rdcr    DTAG10,r2
-       rdcr    DTAG11,r2
-       rdcr    DTAG12,r2
-       rdcr    DTAG13,r2
-       rdcr    DTAG14,r2
-       rdcr    DTAG15,r2
-       rdcr    DTAG2,r2
-       rdcr    DTAG3,r2
-       rdcr    DTAG4,r2
-       rdcr    DTAG5,r2
-       rdcr    DTAG6,r2
-       rdcr    DTAG7,r2
-       rdcr    DTAG8,r2
-       rdcr    DTAG9,r2
-       rdcr    ECOMCNTL,r2
-       rdcr    EIP,r2
-       rdcr    EPC,r2
-       rdcr    FLTADR,r2
-       rdcr    FLTDTH,r2
-       rdcr    FLTDTL,r2
-       rdcr    FLTOP,r2
-       rdcr    FLTTAG,r2
-       rdcr    FPST,r2
-       rdcr    IE,r2
-       rdcr    ILRU,r2
-       rdcr    IN0P,r2
-       rdcr    IN1P,r2
-       rdcr    INTPEN,r2
-       rdcr    ITAG0,r2
-       rdcr    ITAG1,r2
-       rdcr    ITAG10,r2
-       rdcr    ITAG11,r2
-       rdcr    ITAG12,r2
-       rdcr    ITAG13,r2
-       rdcr    ITAG14,r2
-       rdcr    ITAG15,r2
-       rdcr    ITAG2,r2
-       rdcr    ITAG3,r2
-       rdcr    ITAG4,r2
-       rdcr    ITAG5,r2
-       rdcr    ITAG6,r2
-       rdcr    ITAG7,r2
-       rdcr    ITAG8,r2
-       rdcr    ITAG9,r2
-       rdcr    MIP,r2
-       rdcr    MPC,r2
-       rdcr    OUTP,r2
-       rdcr    PKTREQ,r2
-       rdcr    PPERROR,r2
-       rdcr    SYSSTK,r2
-       rdcr    SYSTMP,r2
-       rdcr    TCOUNT,r2
-       rdcr    TSCALE,r2
diff --git a/gas/testsuite/gas/tic80/endmask.d b/gas/testsuite/gas/tic80/endmask.d
deleted file mode 100644 (file)
index 5cd0847..0000000
+++ /dev/null
@@ -1,41 +0,0 @@
-#objdump: -d
-#name: TIc80 coverage of shift instruction ENDMASK field
-
-.*: +file format .*tic80.*
-
-Disassembly of section .text:
-
-00000000 <.text>:
-   0:  05 00 c7 49.*
-   4:  25 00 c7 49.*
-   8:  45 00 c7 49.*
-   c:  65 00 c7 49.*
-  10:  85 00 c7 49.*
-  14:  a5 00 c7 49.*
-  18:  c5 00 c7 49.*
-  1c:  e5 00 c7 49.*
-  20:  05 01 c7 49.*
-  24:  25 01 c7 49.*
-  28:  45 01 c7 49.*
-  2c:  65 01 c7 49.*
-  30:  85 01 c7 49.*
-  34:  a5 01 c7 49.*
-  38:  c5 01 c7 49.*
-  3c:  e5 01 c7 49.*
-  40:  05 02 c7 49.*
-  44:  25 02 c7 49.*
-  48:  45 02 c7 49.*
-  4c:  65 02 c7 49.*
-  50:  85 02 c7 49.*
-  54:  a5 02 c7 49.*
-  58:  c5 02 c7 49.*
-  5c:  e5 02 c7 49.*
-  60:  05 03 c7 49.*
-  64:  25 03 c7 49.*
-  68:  45 03 c7 49.*
-  6c:  65 03 c7 49.*
-  70:  85 03 c7 49.*
-  74:  a5 03 c7 49.*
-  78:  c5 03 c7 49.*
-  7c:  e5 03 c7 49.*
-  80:  05 00 c7 49.*
diff --git a/gas/testsuite/gas/tic80/endmask.lst b/gas/testsuite/gas/tic80/endmask.lst
deleted file mode 100644 (file)
index 9103b33..0000000
+++ /dev/null
@@ -1,45 +0,0 @@
-MVP MP Macro Assembler     Version 1.13     Mon Feb 10 17:00:29 1997
-Copyright (c) 1993-1995    Texas Instruments Incorporated 
-
-endmask.s                                                            PAGE    1
-
-        1                     ;; Test all possible combinations of the endmask in bits 5-9.
-        2                     ;; The mask that is used is computed as 2**bits-1 where bits
-        3                     ;; are the bits 5-9 from the instruction.  Note that 0 and 32
-        4                     ;; are treated identically, and disassembled as 0.
-        5                     
-        6 00000000   49C70005         sl.iz   5,0,r7,r9
-        7 00000004   49C70025         sl.iz   5,1,r7,r9
-        8 00000008   49C70045         sl.iz   5,2,r7,r9
-        9 0000000C   49C70065         sl.iz   5,3,r7,r9
-       10 00000010   49C70085         sl.iz   5,4,r7,r9
-       11 00000014   49C700A5         sl.iz   5,5,r7,r9
-       12 00000018   49C700C5         sl.iz   5,6,r7,r9
-       13 0000001C   49C700E5         sl.iz   5,7,r7,r9
-       14 00000020   49C70105         sl.iz   5,8,r7,r9
-       15 00000024   49C70125         sl.iz   5,9,r7,r9
-       16 00000028   49C70145         sl.iz   5,10,r7,r9
-       17 0000002C   49C70165         sl.iz   5,11,r7,r9
-       18 00000030   49C70185         sl.iz   5,12,r7,r9
-       19 00000034   49C701A5         sl.iz   5,13,r7,r9
-       20 00000038   49C701C5         sl.iz   5,14,r7,r9
-       21 0000003C   49C701E5         sl.iz   5,15,r7,r9
-       22 00000040   49C70205         sl.iz   5,16,r7,r9
-       23 00000044   49C70225         sl.iz   5,17,r7,r9
-       24 00000048   49C70245         sl.iz   5,18,r7,r9
-       25 0000004C   49C70265         sl.iz   5,19,r7,r9
-       26 00000050   49C70285         sl.iz   5,20,r7,r9
-       27 00000054   49C702A5         sl.iz   5,21,r7,r9
-       28 00000058   49C702C5         sl.iz   5,22,r7,r9
-       29 0000005C   49C702E5         sl.iz   5,23,r7,r9
-       30 00000060   49C70305         sl.iz   5,24,r7,r9
-       31 00000064   49C70325         sl.iz   5,25,r7,r9
-       32 00000068   49C70345         sl.iz   5,26,r7,r9
-       33 0000006C   49C70365         sl.iz   5,27,r7,r9
-       34 00000070   49C70385         sl.iz   5,28,r7,r9
-       35 00000074   49C703A5         sl.iz   5,29,r7,r9
-       36 00000078   49C703C5         sl.iz   5,30,r7,r9
-       37 0000007C   49C703E5         sl.iz   5,31,r7,r9
-       38 00000080   49C70005         sl.iz   5,32,r7,r9
-
- No Errors,  No Warnings
diff --git a/gas/testsuite/gas/tic80/endmask.s b/gas/testsuite/gas/tic80/endmask.s
deleted file mode 100644 (file)
index a36aede..0000000
+++ /dev/null
@@ -1,38 +0,0 @@
-;; Test all possible combinations of the endmask in bits 5-9.
-;; The mask that is used is computed as 2**bits-1 where bits
-;; are the bits 5-9 from the instruction.  Note that 0 and 32
-;; are treated identically, and disassembled as 0.
-
-       sl.iz   5,0,r7,r9
-       sl.iz   5,1,r7,r9
-       sl.iz   5,2,r7,r9
-       sl.iz   5,3,r7,r9
-       sl.iz   5,4,r7,r9
-       sl.iz   5,5,r7,r9
-       sl.iz   5,6,r7,r9
-       sl.iz   5,7,r7,r9
-       sl.iz   5,8,r7,r9
-       sl.iz   5,9,r7,r9
-       sl.iz   5,10,r7,r9
-       sl.iz   5,11,r7,r9
-       sl.iz   5,12,r7,r9
-       sl.iz   5,13,r7,r9
-       sl.iz   5,14,r7,r9
-       sl.iz   5,15,r7,r9
-       sl.iz   5,16,r7,r9
-       sl.iz   5,17,r7,r9
-       sl.iz   5,18,r7,r9
-       sl.iz   5,19,r7,r9
-       sl.iz   5,20,r7,r9
-       sl.iz   5,21,r7,r9
-       sl.iz   5,22,r7,r9
-       sl.iz   5,23,r7,r9
-       sl.iz   5,24,r7,r9
-       sl.iz   5,25,r7,r9
-       sl.iz   5,26,r7,r9
-       sl.iz   5,27,r7,r9
-       sl.iz   5,28,r7,r9
-       sl.iz   5,29,r7,r9
-       sl.iz   5,30,r7,r9
-       sl.iz   5,31,r7,r9
-       sl.iz   5,32,r7,r9
diff --git a/gas/testsuite/gas/tic80/float.d b/gas/testsuite/gas/tic80/float.d
deleted file mode 100644 (file)
index 87eb85b..0000000
+++ /dev/null
@@ -1,40 +0,0 @@
-#objdump: -d
-#name: TIc80 simple floating point operands
-
-.*: +file format .*tic80.*
-
-Disassembly of section .text:
-
-00000000 <.text>:
-   0:  80 12 be 51 16 68 a9 65.*
-   8:  00 12 be 51 16 68 a9 e5.*
-  10:  00 10 be 51 9a 6d 41 19.*
-  18:  80 b0 3e 52 9a 6d 41 99.*
-  20:  00 b0 3e 52 00 00 00 00.*
-  28:  80 72 be 51 00 00 00 40.*
-  30:  00 72 be 51 00 00 00 3f.*
-  38:  00 70 be 51 00 00 80 45.*
-  40:  80 52 be 51 00 00 80 c5.*
-  48:  00 52 be 51 00 00 00 40.*
-  50:  00 50 be 51 00 00 00 40.*
-  58:  80 93 3e 40 00 00 00 40.*
-  60:  80 95 3e 40 00 00 00 40.*
-  68:  80 91 3e 40 00 00 00 40.*
-  70:  80 97 3e 40 00 00 00 40.*
-  78:  00 92 3e 40 00 00 00 40.*
-  80:  00 94 3e 40 00 00 00 40.*
-  88:  00 90 3e 40 00 00 00 40.*
-  90:  00 96 3e 40 00 00 00 40.*
-  98:  00 93 3e 40 00 00 00 40.*
-  a0:  00 95 3e 40 00 00 00 40.*
-  a8:  00 91 3e 40 00 00 00 40.*
-  b0:  00 97 3e 40 00 00 00 40.*
-  b8:  80 92 3e 40 00 00 00 40.*
-  c0:  80 94 3e 40 00 00 00 40.*
-  c8:  80 90 3e 40 00 00 00 40.*
-  d0:  80 96 3e 40 00 00 00 40.*
-  d8:  00 f2 3e 50 00 00 00 40.*
-  e0:  00 f0 3e 50 00 00 00 40.*
-  e8:  80 32 be 51 00 00 00 40.*
-  f0:  00 32 be 51 00 00 00 40.*
-  f8:  00 30 be 51 00 00 00 40.*
diff --git a/gas/testsuite/gas/tic80/float.lst b/gas/testsuite/gas/tic80/float.lst
deleted file mode 100644 (file)
index 6134590..0000000
+++ /dev/null
@@ -1,76 +0,0 @@
-MVP MP Macro Assembler     Version 1.13     Wed Feb 26 22:09:09 1997
-Copyright (c) 1993-1995    Texas Instruments Incorporated 
-
-float.s                                                              PAGE    1
-
-        1 00000000   51BE1280         fadd.sdd        1.0E23,r6,r10   ; Immediate form
-          00000004   65A96816 
-        2 00000008   51BE1200         fadd.ssd        -1.0E23,r6,r10  ; Immediate form
-          0000000C   E5A96816 
-        3 00000010   51BE1000         fadd.sss        1.0E-23,r6,r10  ; Immediate form
-          00000014   19416D9A 
-        4 00000018   523EB080         fcmp.sd         -1.0E-23,r8,r10 ; Immediate form
-          0000001C   99416D9A 
-        5 00000020   523EB000         fcmp.ss         0.0,r8,r10      ; Immediate form
-          00000024   00000000 
-        6 00000028   51BE7280         fdiv.sdd        2.0,r6,r10      ; Immediate form
-          0000002C   40000000 
-        7 00000030   51BE7200         fdiv.ssd        0.5,r6,r10      ; Immediate form
-          00000034   3F000000 
-        8 00000038   51BE7000         fdiv.sss        4096.0,r6,r10   ; Immediate form
-          0000003C   45800000 
-        9 00000040   51BE5280         fmpy.sdd        -4096.0,r6,r10  ; Immediate form
-          00000044   C5800000 
-       10 00000048   51BE5200         fmpy.ssd        2.0,r6,r10      ; Immediate form
-          0000004C   40000000 
-       11 00000050   51BE5000         fmpy.sss        2.0,r6,r10      ; Immediate form
-          00000054   40000000 
-       12 00000058   403E9380         frndm.sd        2.0,r8          ; Immediate form
-          0000005C   40000000 
-       13 00000060   403E9580         frndm.si        2.0,r8          ; Immediate form
-          00000064   40000000 
-       14 00000068   403E9180         frndm.ss        2.0,r8          ; Immediate form
-          0000006C   40000000 
-       15 00000070   403E9780         frndm.su        2.0,r8          ; Immediate form
-          00000074   40000000 
-       16 00000078   403E9200         frndn.sd        2.0,r8          ; Immediate form
-          0000007C   40000000 
-       17 00000080   403E9400         frndn.si        2.0,r8          ; Immediate form
-          00000084   40000000 
-       18 00000088   403E9000         frndn.ss        2.0,r8          ; Immediate form
-          0000008C   40000000 
-       19 00000090   403E9600         frndn.su        2.0,r8          ; Immediate form
-          00000094   40000000 
-       20 00000098   403E9300         frndp.sd        2.0,r8          ; Immediate form
-          0000009C   40000000 
-       21 000000A0   403E9500         frndp.si        2.0,r8          ; Immediate form
-          000000A4   40000000 
-       22 000000A8   403E9100         frndp.ss        2.0,r8          ; Immediate form
-          000000AC   40000000 
-       23 000000B0   403E9700         frndp.su        2.0,r8          ; Immediate form
-          000000B4   40000000 
-       24 000000B8   403E9280         frndz.sd        2.0,r8          ; Immediate form
-          000000BC   40000000 
-       25 000000C0   403E9480         frndz.si        2.0,r8          ; Immediate form
-          000000C4   40000000 
-       26 000000C8   403E9080         frndz.ss        2.0,r8          ; Immediate form
-          000000CC   40000000 
-       27 000000D0   403E9680         frndz.su        2.0,r8          ; Immediate form
-          000000D4   40000000 
-       28 000000D8   503EF200         fsqrt.sd        2.0,r10         ; Immediate form
-\fMVP MP Macro Assembler     Version 1.13     Wed Feb 26 22:09:09 1997
-Copyright (c) 1993-1995    Texas Instruments Incorporated 
-
-float.s                                                              PAGE    2
-
-          000000DC   40000000 
-       29 000000E0   503EF000         fsqrt.ss        2.0,r10         ; Immediate form
-          000000E4   40000000 
-       30 000000E8   51BE3280         fsub.sdd        2.0,r6,r10      ; Immediate form
-          000000EC   40000000 
-       31 000000F0   51BE3200         fsub.ssd        2.0,r6,r10      ; Immediate form
-          000000F4   40000000 
-       32 000000F8   51BE3000         fsub.sss        2.0,r6,r10      ; Immediate form
-          000000FC   40000000 
-
- No Errors,  No Warnings
diff --git a/gas/testsuite/gas/tic80/float.s b/gas/testsuite/gas/tic80/float.s
deleted file mode 100644 (file)
index 98a2b7a..0000000
+++ /dev/null
@@ -1,32 +0,0 @@
-       fadd.sdd        0f1.0E23,r6,r10 ; Immediate form
-       fadd.ssd        0f-1.0E23,r6,r10        ; Immediate form
-       fadd.sss        0f1.0E-23,r6,r10        ; Immediate form
-       fcmp.sd         0f-1.0E-23,r8,r10       ; Immediate form
-       fcmp.ss         0f0.0,r8,r10    ; Immediate form
-       fdiv.sdd        0f2.0,r6,r10    ; Immediate form
-       fdiv.ssd        0f0.5,r6,r10    ; Immediate form
-       fdiv.sss        0f4096.0,r6,r10 ; Immediate form
-       fmpy.sdd        0f-4096.0,r6,r10        ; Immediate form
-       fmpy.ssd        0f2.0,r6,r10    ; Immediate form
-       fmpy.sss        0f2.0,r6,r10    ; Immediate form
-       frndm.sd        0f2.0,r8                ; Immediate form
-       frndm.si        0f2.0,r8                ; Immediate form
-       frndm.ss        0f2.0,r8                ; Immediate form
-       frndm.su        0f2.0,r8                ; Immediate form
-       frndn.sd        0f2.0,r8                ; Immediate form
-       frndn.si        0f2.0,r8                ; Immediate form
-       frndn.ss        0f2.0,r8                ; Immediate form
-       frndn.su        0f2.0,r8                ; Immediate form
-       frndp.sd        0f2.0,r8                ; Immediate form
-       frndp.si        0f2.0,r8                ; Immediate form
-       frndp.ss        0f2.0,r8                ; Immediate form
-       frndp.su        0f2.0,r8                ; Immediate form
-       frndz.sd        0f2.0,r8                ; Immediate form
-       frndz.si        0f2.0,r8                ; Immediate form
-       frndz.ss        0f2.0,r8                ; Immediate form
-       frndz.su        0f2.0,r8                ; Immediate form
-       fsqrt.sd        0f2.0,r10               ; Immediate form
-       fsqrt.ss        0f2.0,r10               ; Immediate form
-       fsub.sdd        0f2.0,r6,r10    ; Immediate form
-       fsub.ssd        0f2.0,r6,r10    ; Immediate form
-       fsub.sss        0f2.0,r6,r10    ; Immediate form
diff --git a/gas/testsuite/gas/tic80/regops.d b/gas/testsuite/gas/tic80/regops.d
deleted file mode 100644 (file)
index dd0fa85..0000000
+++ /dev/null
@@ -1,188 +0,0 @@
-#objdump: -d
-#name: TIc80 register operands
-
-.*: +file format .*tic80.*
-
-Disassembly of section .text:
-
-00000000 <.text>:
-   0:  03 00 3b 29.*
-   4:  03 20 3b 29.*
-   8:  05 20 32 11.*
-   c:  05 20 32 11.*
-  10:  0a 00 33 73.*
-  14:  0a 80 32 73.*
-  18:  0a 40 32 73.*
-  1c:  0a 40 39 1a.*
-  20:  0a 60 39 fa.*
-  24:  0a 00 39 22.*
-  28:  0a 20 39 2a.*
-  2c:  04 80 b9 21.*
-  30:  04 a0 b9 21.*
-  34:  06 00 39 00.*
-  38:  06 20 39 00.*
-  3c:  0a 00 03 00.*
-  40:  06 00 38 f8.*
-  44:  06 20 38 f8.*
-  48:  07 40 30 00.*
-  4c:  03 00 3a 29.*
-  50:  08 00 b7 02.*
-  54:  08 00 b7 0a.*
-  58:  04 04 b4 41.*
-  5c:  04 24 b4 41.*
-  60:  04 44 b4 41.*
-  64:  04 64 b4 41.*
-  68:  04 04 b5 41.*
-  6c:  04 24 b5 41.*
-  70:  04 04 b6 41.*
-  74:  04 24 b6 41.*
-  78:  04 44 b6 41.*
-  7c:  04 64 b6 41.*
-  80:  05 20 30 08.*
-  84:  e3 47 71 31.*
-  88:  c2 07 71 49.*
-  8c:  02 00 3e 31.*
-  90:  02 02 3e 31.*
-  94:  82 02 3e 31.*
-  98:  22 02 3e 31.*
-  9c:  a2 02 3e 31.*
-  a0:  04 a0 be 41.*
-  a4:  84 a0 be 41.*
-  a8:  24 a0 be 41.*
-  ac:  a4 a0 be 41.*
-  b0:  02 60 3e 31.*
-  b4:  02 62 3e 31.*
-  b8:  82 62 3e 31.*
-  bc:  22 62 3e 31.*
-  c0:  a2 62 3e 31.*
-  c4:  02 40 3e 31.*
-  c8:  02 42 3e 31.*
-  cc:  82 42 3e 31.*
-  d0:  22 42 3e 31.*
-  d4:  a2 42 3e 31.*
-  d8:  42 45 3e 31.*
-  dc:  e2 47 3e 31.*
-  e0:  84 81 3e 30.*
-  e4:  84 83 3e 30.*
-  e8:  84 85 3e 30.*
-  ec:  84 87 3e 30.*
-  f0:  a2 81 3e 40.*
-  f4:  a2 83 3e 40.*
-  f8:  a2 85 3e 40.*
-  fc:  a2 87 3e 40.*
- 100:  c4 81 3e 30.*
- 104:  c4 83 3e 30.*
- 108:  e2 81 3e 40.*
- 10c:  e2 83 3e 40.*
- 110:  04 80 3e 30.*
- 114:  04 82 3e 30.*
- 118:  04 84 3e 30.*
- 11c:  04 86 3e 30.*
- 120:  22 80 3e 40.*
- 124:  22 82 3e 40.*
- 128:  22 84 3e 40.*
- 12c:  22 86 3e 40.*
- 130:  44 80 3e 30.*
- 134:  44 82 3e 30.*
- 138:  62 80 3e 40.*
- 13c:  62 82 3e 40.*
- 140:  04 81 3e 30.*
- 144:  04 83 3e 30.*
- 148:  04 85 3e 30.*
- 14c:  04 87 3e 30.*
- 150:  22 81 3e 40.*
- 154:  22 83 3e 40.*
- 158:  22 85 3e 40.*
- 15c:  22 87 3e 40.*
- 160:  44 81 3e 30.*
- 164:  44 83 3e 30.*
- 168:  62 81 3e 40.*
- 16c:  62 83 3e 40.*
- 170:  84 80 3e 30.*
- 174:  84 82 3e 30.*
- 178:  84 84 3e 30.*
- 17c:  84 86 3e 30.*
- 180:  a2 80 3e 40.*
- 184:  a2 82 3e 40.*
- 188:  a2 84 3e 40.*
- 18c:  a2 86 3e 40.*
- 190:  c4 80 3e 30.*
- 194:  c4 82 3e 30.*
- 198:  e2 80 3e 40.*
- 19c:  e2 82 3e 40.*
- 1a0:  06 e0 3e 40.*
- 1a4:  06 e2 3e 40.*
- 1a8:  26 e2 3e 40.*
- 1ac:  02 20 3e 31.*
- 1b0:  02 22 3e 31.*
- 1b4:  82 22 3e 31.*
- 1b8:  22 22 3e 31.*
- 1bc:  a2 22 3e 31.*
- 1c0:  e4 e3 31 52.*
- 1c4:  04 80 b8 41.*
- 1c8:  04 a0 b8 41.*
- 1cc:  04 00 b4 41.*
- 1d0:  04 20 b4 41.*
- 1d4:  04 40 b4 41.*
- 1d8:  04 60 b4 41.*
- 1dc:  04 00 b5 41.*
- 1e0:  04 20 b5 41.*
- 1e4:  00 00 ff 41.*
- 1e8:  01 e0 b2 18.*
- 1ec:  01 e0 b2 18.*
- 1f0:  01 c0 b3 18.*
- 1f4:  01 a0 b3 18.*
- 1f8:  01 60 b3 18.*
- 1fc:  06 80 30 20.*
- 200:  00 20 3f 29.*
- 204:  e2 03 31 52.*
- 208:  e8 07 b1 30.*
- 20c:  e4 c3 b1 30.*
- 210:  84 01 71 31.*
- 214:  84 21 71 31.*
- 218:  84 41 71 31.*
- 21c:  84 61 71 31.*
- 220:  84 81 71 31.*
- 224:  84 a1 71 31.*
- 228:  84 c1 71 31.*
- 22c:  84 e1 71 31.*
- 230:  84 09 71 31.*
- 234:  84 29 71 31.*
- 238:  84 49 71 31.*
- 23c:  84 69 71 31.*
- 240:  84 89 71 31.*
- 244:  84 a9 71 31.*
- 248:  84 c9 71 31.*
- 24c:  84 e9 71 31.*
- 250:  84 05 71 31.*
- 254:  84 25 71 31.*
- 258:  84 45 71 31.*
- 25c:  84 65 71 31.*
- 260:  84 85 71 31.*
- 264:  84 a5 71 31.*
- 268:  84 c5 71 31.*
- 26c:  84 e5 71 31.*
- 270:  04 a4 b1 41.*
- 274:  84 0d 71 31.*
- 278:  84 2d 71 31.*
- 27c:  84 4d 71 31.*
- 280:  84 6d 71 31.*
- 284:  84 8d 71 31.*
- 288:  84 ad 71 31.*
- 28c:  84 cd 71 31.*
- 290:  84 ed 71 31.*
- 294:  04 64 b1 41.*
- 298:  04 00 b6 41.*
- 29c:  04 20 b6 41.*
- 2a0:  04 40 b6 41.*
- 2a4:  04 60 b6 41.*
- 2a8:  07 40 3b 4a.*
- 2ac:  07 60 3b 4a.*
- 2b0:  08 a0 b0 21.*
- 2b4:  0a 20 30 00.*
- 2b8:  02 00 3c 01.*
- 2bc:  82 00 bc 01.*
- 2c0:  a2 00 bc 02.*
- 2c4:  06 a0 70 01.*
- 2c8:  05 20 b3 39.*
- 2cc:  07 c0 32 4a.*
diff --git a/gas/testsuite/gas/tic80/regops.lst b/gas/testsuite/gas/tic80/regops.lst
deleted file mode 100644 (file)
index f889dd1..0000000
+++ /dev/null
@@ -1,264 +0,0 @@
-MVP MP Macro Assembler     Version 1.13     Mon Feb 10 17:00:24 1997
-Copyright (c) 1993-1995    Texas Instruments Incorporated 
-
-regops.s                                                             PAGE    1
-
-        1                     ;; Simple register forms
-        2                     ;; Those instructions which also use an immediate just use a constant.
-        3                     
-        4 00000000                    .text
-        5                     
-        6 00000000   293B0003         add             r3,r4,r5
-        7 00000004   293B2003         addu            r3,r4,r5
-        8 00000008   11322005         and             r5,r4,r2
-        9 0000000C   11322005         and.tt          r5,r4,r2
-       10 00000010   7333000A         and.ff          r10,r12,r14
-       11 00000014   7332800A         and.ft          r10,r12,r14
-       12 00000018   7332400A         and.tf          r10,r12,r14
-       13 0000001C   1A39400A         bbo             r10,r8,lo.w
-       14 00000020   FA39600A         bbo.a           r10,r8,eq.b
-       15 00000024   2239000A         bbz             r10,r8,ls.w
-       16 00000028   2A39200A         bbz.a           r10,r8,hi.w
-       17 0000002C   21B98004         bcnd            r4,r6,lt0.b
-       18 00000030   21B9A004         bcnd.a          r4,r6,lt0.b
-       19 00000034   00390006         br              r6
-       20 00000038   00392006         br.a            r6
-       21 0000003C   0003000A         brcr            10
-       22 00000040   F8380006         bsr             r6,r31
-       23 00000044   F8382006         bsr.a           r6,r31
-       24 00000048   00304007         cmnd            r7
-       25 0000004C   293A0003         cmp             r3,r4,r5
-       26 00000050   02B70008         dcachec         r8(r10)
-       27 00000054   0AB70008         dcachef         r8(r10)
-       28 00000058   41B40404         dld.b           r4(r6),r8
-       29 0000005C   41B42404         dld.h           r4(r6),r8
-       30 00000060   41B44404         dld             r4(r6),r8
-       31 00000064   41B46404         dld.d           r4(r6),r8
-       32 00000068   41B50404         dld.ub          r4(r6),r8
-       33 0000006C   41B52404         dld.uh          r4(r6),r8
-       34 00000070   41B60404         dst.b           r4(r6),r8
-       35 00000074   41B62404         dst.h           r4(r6),r8
-       36 00000078   41B64404         dst             r4(r6),r8
-       37 0000007C   41B66404         dst.d           r4(r6),r8
-       38 00000080   08302005         etrap           r5
-       39 00000084   317147E3         exts            r3,31,r5,r6
-       40 00000088   497107C2         extu            r2,30,r5,r9
-       41 0000008C   313E0002         fadd.sss        r2,r4,r6
-       42 00000090   313E0202         fadd.ssd        r2,r4,r6
-       43 00000094   313E0282         fadd.sdd        r2,r4,r6
-       44 00000098   313E0222         fadd.dsd        r2,r4,r6
-       45 0000009C   313E02A2         fadd.ddd        r2,r4,r6
-       46 000000A0   41BEA004         fcmp.ss         r4,r6,r8
-       47 000000A4   41BEA084         fcmp.sd         r4,r6,r8
-       48 000000A8   41BEA024         fcmp.ds         r4,r6,r8
-       49 000000AC   41BEA0A4         fcmp.dd         r4,r6,r8
-       50 000000B0   313E6002         fdiv.sss        r2,r4,r6
-       51 000000B4   313E6202         fdiv.ssd        r2,r4,r6
-       52 000000B8   313E6282         fdiv.sdd        r2,r4,r6
-       53 000000BC   313E6222         fdiv.dsd        r2,r4,r6
-       54 000000C0   313E62A2         fdiv.ddd        r2,r4,r6
-       55 000000C4   313E4002         fmpy.sss        r2,r4,r6
-\fMVP MP Macro Assembler     Version 1.13     Mon Feb 10 17:00:24 1997
-Copyright (c) 1993-1995    Texas Instruments Incorporated 
-
-regops.s                                                             PAGE    2
-
-       56 000000C8   313E4202         fmpy.ssd        r2,r4,r6
-       57 000000CC   313E4282         fmpy.sdd        r2,r4,r6
-       58 000000D0   313E4222         fmpy.dsd        r2,r4,r6
-       59 000000D4   313E42A2         fmpy.ddd        r2,r4,r6
-       60 000000D8   313E4542         fmpy.iii        r2,r4,r6
-       61 000000DC   313E47E2         fmpy.uuu        r2,r4,r6
-       62 000000E0   303E8184         frndm.ss        r4,r6
-       63 000000E4   303E8384         frndm.sd        r4,r6
-       64 000000E8   303E8584         frndm.si        r4,r6
-       65 000000EC   303E8784         frndm.su        r4,r6
-       66 000000F0   403E81A2         frndm.ds        r2,r8
-       67 000000F4   403E83A2         frndm.dd        r2,r8
-       68 000000F8   403E85A2         frndm.di        r2,r8
-       69 000000FC   403E87A2         frndm.du        r2,r8
-       70 00000100   303E81C4         frndm.is        r4,r6
-       71 00000104   303E83C4         frndm.id        r4,r6
-       72 00000108   403E81E2         frndm.us        r2,r8
-       73 0000010C   403E83E2         frndm.ud        r2,r8
-       74 00000110   303E8004         frndn.ss        r4,r6
-       75 00000114   303E8204         frndn.sd        r4,r6
-       76 00000118   303E8404         frndn.si        r4,r6
-       77 0000011C   303E8604         frndn.su        r4,r6
-       78 00000120   403E8022         frndn.ds        r2,r8
-       79 00000124   403E8222         frndn.dd        r2,r8
-       80 00000128   403E8422         frndn.di        r2,r8
-       81 0000012C   403E8622         frndn.du        r2,r8
-       82 00000130   303E8044         frndn.is        r4,r6
-       83 00000134   303E8244         frndn.id        r4,r6
-       84 00000138   403E8062         frndn.us        r2,r8
-       85 0000013C   403E8262         frndn.ud        r2,r8
-       86 00000140   303E8104         frndp.ss        r4,r6
-       87 00000144   303E8304         frndp.sd        r4,r6
-       88 00000148   303E8504         frndp.si        r4,r6
-       89 0000014C   303E8704         frndp.su        r4,r6
-       90 00000150   403E8122         frndp.ds        r2,r8
-       91 00000154   403E8322         frndp.dd        r2,r8
-       92 00000158   403E8522         frndp.di        r2,r8
-       93 0000015C   403E8722         frndp.du        r2,r8
-       94 00000160   303E8144         frndp.is        r4,r6
-       95 00000164   303E8344         frndp.id        r4,r6
-       96 00000168   403E8162         frndp.us        r2,r8
-       97 0000016C   403E8362         frndp.ud        r2,r8
-       98 00000170   303E8084         frndz.ss        r4,r6
-       99 00000174   303E8284         frndz.sd        r4,r6
-      100 00000178   303E8484         frndz.si        r4,r6
-      101 0000017C   303E8684         frndz.su        r4,r6
-      102 00000180   403E80A2         frndz.ds        r2,r8
-      103 00000184   403E82A2         frndz.dd        r2,r8
-      104 00000188   403E84A2         frndz.di        r2,r8
-      105 0000018C   403E86A2         frndz.du        r2,r8
-      106 00000190   303E80C4         frndz.is        r4,r6
-      107 00000194   303E82C4         frndz.id        r4,r6
-      108 00000198   403E80E2         frndz.us        r2,r8
-      109 0000019C   403E82E2         frndz.ud        r2,r8
-      110 000001A0   403EE006         fsqrt.ss        r6,r8
-\fMVP MP Macro Assembler     Version 1.13     Mon Feb 10 17:00:24 1997
-Copyright (c) 1993-1995    Texas Instruments Incorporated 
-
-regops.s                                                             PAGE    3
-
-      111 000001A4   403EE206         fsqrt.sd        r6,r8
-      112 000001A8   403EE226         fsqrt.dd        r6,r8
-      113 000001AC   313E2002         fsub.sss        r2,r4,r6
-      114 000001B0   313E2202         fsub.ssd        r2,r4,r6
-      115 000001B4   313E2282         fsub.sdd        r2,r4,r6
-      116 000001B8   313E2222         fsub.dsd        r2,r4,r6
-      117 000001BC   313E22A2         fsub.ddd        r2,r4,r6
-      118 000001C0   5231E3E4         ins             r4,31,r8,r10
-      119 000001C4   41B88004         jsr             r4(r6),r8
-      120 000001C8   41B8A004         jsr.a           r4(r6),r8
-      121 000001CC   41B40004         ld.b            r4(r6),r8
-      122 000001D0   41B42004         ld.h            r4(r6),r8
-      123 000001D4   41B44004         ld              r4(r6),r8
-      124 000001D8   41B46004         ld.d            r4(r6),r8
-      125 000001DC   41B50004         ld.ub           r4(r6),r8
-      126 000001E0   41B52004         ld.uh           r4(r6),r8
-      127 000001E4   41FF0007         lmo             r7,r8
-      128 000001E8   18B2E001         or              r1,r2,r3
-      129 000001EC   18B2E001         or.tt           r1,r2,r3
-      130 000001F0   18B3C001         or.ff           r1,r2,r3
-      131 000001F4   18B3A001         or.ft           r1,r2,r3
-      132 000001F8   18B36001         or.tf           r1,r2,r3
-      133 000001FC   20308006         rdcr            r6,r4
-      134 00000200   293F2004         rmo             r4,r5
-      135 00000204   523103E2         rotl            r2,31,r8,r10
-      136 00000208   30B107E8         rotr            r8,31,r2,r6
-      137 0000020C   30B1C3E4         shl             r4,31,r2,r6
-      138 00000210   31710184         sl.dz           r4,12,r5,r6
-      139 00000214   31712184         sl.dm           r4,12,r5,r6
-      140 00000218   31714184         sl.ds           r4,12,r5,r6
-      141 0000021C   31716184         sl.ez           r4,12,r5,r6
-      142 00000220   31718184         sl.em           r4,12,r5,r6
-      143 00000224   3171A184         sl.es           r4,12,r5,r6
-      144 00000228   3171C184         sl.iz           r4,12,r5,r6
-      145 0000022C   3171E184         sl.im           r4,12,r5,r6
-      146 00000230   31710984         sli.dz          r4,12,r5,r6
-      147 00000234   31712984         sli.dm          r4,12,r5,r6
-      148 00000238   31714984         sli.ds          r4,12,r5,r6
-      149 0000023C   31716984         sli.ez          r4,12,r5,r6
-      150 00000240   31718984         sli.em          r4,12,r5,r6
-      151 00000244   3171A984         sli.es          r4,12,r5,r6
-      152 00000248   3171C984         sli.iz          r4,12,r5,r6
-      153 0000024C   3171E984         sli.im          r4,12,r5,r6
-      154 00000250   31710584         sr.dz           r4,12,r5,r6
-      155 00000254   31712584         sr.dm           r4,12,r5,r6
-      156 00000258   31714584         sr.ds           r4,12,r5,r6
-      157 0000025C   31716584         sr.ez           r4,12,r5,r6
-      158 00000260   31718584         sr.em           r4,12,r5,r6
-      159 00000264   3171A584         sr.es           r4,12,r5,r6
-      160 00000268   3171C584         sr.iz           r4,12,r5,r6
-      161 0000026C   3171E584         sr.im           r4,12,r5,r6
-      162 00000270   41B1A404         sra             r4,32,r6,r8
-      163 00000274   31710D84         sri.dz          r4,12,r5,r6
-      164 00000278   31712D84         sri.dm          r4,12,r5,r6
-      165 0000027C   31714D84         sri.ds          r4,12,r5,r6
-\fMVP MP Macro Assembler     Version 1.13     Mon Feb 10 17:00:24 1997
-Copyright (c) 1993-1995    Texas Instruments Incorporated 
-
-regops.s                                                             PAGE    4
-
-      166 00000280   31716D84         sri.ez          r4,12,r5,r6
-      167 00000284   31718D84         sri.em          r4,12,r5,r6
-      168 00000288   3171AD84         sri.es          r4,12,r5,r6
-      169 0000028C   3171CD84         sri.iz          r4,12,r5,r6
-      170 00000290   3171ED84         sri.im          r4,12,r5,r6
-      171 00000294   41B16404         srl             r4,32,r6,r8
-      172 00000298   41B60004         st.b            r4(r6),r8
-      173 0000029C   41B62004         st.h            r4(r6),r8
-      174 000002A0   41B64004         st              r4(r6),r8
-      175 000002A4   41B66004         st.d            r4(r6),r8
-      176 000002A8   4A3B4007         sub             r7,r8,r9
-      177 000002AC   4A3B6007         subu            r7,r8,r9
-      178 000002B0   21B0A008         swcr            r8,r6,r4
-      179 000002B4   0030200A         trap            r10
-      180 000002B8   013C0002         vadd.ss         r2,r4,r4
-      181 000002BC   01BC0082         vadd.sd         r2,r6,r6
-      182 000002C0   02BC00A2         vadd.dd         r2,r10,r10
-      183                     ;       vld0.s          r6
-      184                     ;       vld1.s          r7
-      185                     ;       vld0.d          r6
-      186                     ;       vld1.d          r8
-      187                     ;       vmac.sss        r7,r9,0,a3
-      188                     ;       vmac.sss        r7,r9,0,r10
-      189                     ;       vmac.sss        r7,r9,a1,a3
-      190                     ;       vmac.sss        r7,r9,a3,r10
-      191                     ;       vmac.ssd        r7,r9,0,a0
-      192                     ;       vmac.ssd        r7,r9,0,r10
-      193                     ;       vmac.ssd        r7,r9,a1,a2
-      194                     ;       vmac.ssd        r7,r9,a3,r10
-      195                     ;       vmpy.ss         r1,r3,r3
-      196                     ;       vmpy.sd         r5,r6,r6
-      197                     ;       vmpy.dd         r2,r4,r4
-      198                     ;       vmsc.sss        r7,r9,0,a0
-      199                     ;       vmsc.sss        r7,r9,0,r10
-      200                     ;       vmsc.sss        r7,r9,a0,a1
-      201                     ;       vmsc.sss        r7,r9,a3,r10
-      202                     ;       vmsc.ssd        r7,r9,0,a0
-      203                     ;       vmsc.ssd        r7,r9,0,r10
-      204                     ;       vmsc.ssd        r7,r9,a0,a1
-      205                     ;       vmsc.ssd        r7,r9,a3,r10
-      206                     ;       vmsub.ss        r6,a2,a4
-      207                     ;       vmsub.sd        r6,a2,a4
-      208                     ;       vmsub.ss        r4,a4,r6
-      209                     ;       vmsub.sd        r4,a4,r6
-      210                     ;       vrnd.si         r4,r6
-      211                     ;       vrnd.si         r4,a0
-      212                     ;       vrnd.su         r4,r6
-      213                     ;       vrnd.su         r4,a0
-      214                     ;       vrnd.ss         r4,r6
-      215                     ;       vrnd.ss         r4,a0
-      216                     ;       vrnd.sd         r4,r6
-      217                     ;       vrnd.sd         r4,a0
-      218                     ;       vrnd.di         r4,r6
-      219                     ;       vrnd.di         r4,a0
-      220                     ;       vrnd.du         r4,r6
-\fMVP MP Macro Assembler     Version 1.13     Mon Feb 10 17:00:24 1997
-Copyright (c) 1993-1995    Texas Instruments Incorporated 
-
-regops.s                                                             PAGE    5
-
-      221                     ;       vrnd.du         r4,a0
-      222                     ;       vrnd.ds         r4,r6
-      223                     ;       vrnd.ds         r4,a0
-      224                     ;       vrnd.dd         r4,r6
-      225                     ;       vrnd.dd         r4,a0
-      226                     ;       vrnd.is         r4,r6
-      227                     ;       vrnd.id         r4,r6
-      228                     ;       vrnd.us         r4,r6
-      229                     ;       vrnd.ud         r4,r6
-      230                     ;       vst.s           r6
-      231                     ;       vst.d           r6
-      232                     ;       vsub.ss         r2,r4,r6
-      233                     ;       vsub.sd         r2,r4,r6
-      234                     ;       vsub.dd         r2,r4,r6
-      235 000002C4   0170A006         wrcr            r6,r5
-      236 000002C8   39B32005         xnor            r5,r6,r7
-      237 000002CC   4A32C007         xor             r7,r8,r9
-
- No Errors,  No Warnings
diff --git a/gas/testsuite/gas/tic80/regops.s b/gas/testsuite/gas/tic80/regops.s
deleted file mode 100644 (file)
index f4f9352..0000000
+++ /dev/null
@@ -1,237 +0,0 @@
-;; Simple register forms
-;; Those instructions which also use an immediate just use a constant.
-
-       .text
-
-       add             r3,r4,r5
-       addu            r3,r4,r5
-       and             r5,r4,r2
-       and.tt          r5,r4,r2
-       and.ff          r10,r12,r14
-       and.ft          r10,r12,r14
-       and.tf          r10,r12,r14
-       bbo             r10,r8,lo.w
-       bbo.a           r10,r8,eq.b
-       bbz             r10,r8,ls.w
-       bbz.a           r10,r8,hi.w
-       bcnd            r4,r6,lt0.b
-       bcnd.a          r4,r6,lt0.b
-       br              r6
-       br.a            r6
-       brcr            10
-       bsr             r6,r31
-       bsr.a           r6,r31
-       cmnd            r7
-       cmp             r3,r4,r5
-       dcachec         r8(r10)
-       dcachef         r8(r10)
-       dld.b           r4(r6),r8
-       dld.h           r4(r6),r8
-       dld             r4(r6),r8
-       dld.d           r4(r6),r8
-       dld.ub          r4(r6),r8
-       dld.uh          r4(r6),r8
-       dst.b           r4(r6),r8
-       dst.h           r4(r6),r8
-       dst             r4(r6),r8
-       dst.d           r4(r6),r8
-       etrap           r5
-       exts            r3,31,r5,r6
-       extu            r2,30,r5,r9
-       fadd.sss        r2,r4,r6
-       fadd.ssd        r2,r4,r6
-       fadd.sdd        r2,r4,r6
-       fadd.dsd        r2,r4,r6
-       fadd.ddd        r2,r4,r6
-       fcmp.ss         r4,r6,r8
-       fcmp.sd         r4,r6,r8
-       fcmp.ds         r4,r6,r8
-       fcmp.dd         r4,r6,r8
-       fdiv.sss        r2,r4,r6
-       fdiv.ssd        r2,r4,r6
-       fdiv.sdd        r2,r4,r6
-       fdiv.dsd        r2,r4,r6
-       fdiv.ddd        r2,r4,r6
-       fmpy.sss        r2,r4,r6
-       fmpy.ssd        r2,r4,r6
-       fmpy.sdd        r2,r4,r6
-       fmpy.dsd        r2,r4,r6
-       fmpy.ddd        r2,r4,r6
-       fmpy.iii        r2,r4,r6
-       fmpy.uuu        r2,r4,r6
-       frndm.ss        r4,r6
-       frndm.sd        r4,r6
-       frndm.si        r4,r6
-       frndm.su        r4,r6
-       frndm.ds        r2,r8
-       frndm.dd        r2,r8
-       frndm.di        r2,r8
-       frndm.du        r2,r8
-       frndm.is        r4,r6
-       frndm.id        r4,r6
-       frndm.us        r2,r8
-       frndm.ud        r2,r8
-       frndn.ss        r4,r6
-       frndn.sd        r4,r6
-       frndn.si        r4,r6
-       frndn.su        r4,r6
-       frndn.ds        r2,r8
-       frndn.dd        r2,r8
-       frndn.di        r2,r8
-       frndn.du        r2,r8
-       frndn.is        r4,r6
-       frndn.id        r4,r6
-       frndn.us        r2,r8
-       frndn.ud        r2,r8
-       frndp.ss        r4,r6
-       frndp.sd        r4,r6
-       frndp.si        r4,r6
-       frndp.su        r4,r6
-       frndp.ds        r2,r8
-       frndp.dd        r2,r8
-       frndp.di        r2,r8
-       frndp.du        r2,r8
-       frndp.is        r4,r6
-       frndp.id        r4,r6
-       frndp.us        r2,r8
-       frndp.ud        r2,r8
-       frndz.ss        r4,r6
-       frndz.sd        r4,r6
-       frndz.si        r4,r6
-       frndz.su        r4,r6
-       frndz.ds        r2,r8
-       frndz.dd        r2,r8
-       frndz.di        r2,r8
-       frndz.du        r2,r8
-       frndz.is        r4,r6
-       frndz.id        r4,r6
-       frndz.us        r2,r8
-       frndz.ud        r2,r8
-       fsqrt.ss        r6,r8
-       fsqrt.sd        r6,r8
-       fsqrt.dd        r6,r8
-       fsub.sss        r2,r4,r6
-       fsub.ssd        r2,r4,r6
-       fsub.sdd        r2,r4,r6
-       fsub.dsd        r2,r4,r6
-       fsub.ddd        r2,r4,r6
-       ins             r4,31,r8,r10
-       jsr             r4(r6),r8
-       jsr.a           r4(r6),r8
-       ld.b            r4(r6),r8
-       ld.h            r4(r6),r8
-       ld              r4(r6),r8
-       ld.d            r4(r6),r8
-       ld.ub           r4(r6),r8
-       ld.uh           r4(r6),r8
-       lmo             r7,r8
-       or              r1,r2,r3
-       or.tt           r1,r2,r3
-       or.ff           r1,r2,r3
-       or.ft           r1,r2,r3
-       or.tf           r1,r2,r3
-       rdcr            r6,r4
-       rmo             r4,r5
-       rotl            r2,31,r8,r10
-       rotr            r8,31,r2,r6
-       shl             r4,31,r2,r6
-       sl.dz           r4,12,r5,r6
-       sl.dm           r4,12,r5,r6
-       sl.ds           r4,12,r5,r6
-       sl.ez           r4,12,r5,r6
-       sl.em           r4,12,r5,r6
-       sl.es           r4,12,r5,r6
-       sl.iz           r4,12,r5,r6
-       sl.im           r4,12,r5,r6
-       sli.dz          r4,12,r5,r6
-       sli.dm          r4,12,r5,r6
-       sli.ds          r4,12,r5,r6
-       sli.ez          r4,12,r5,r6
-       sli.em          r4,12,r5,r6
-       sli.es          r4,12,r5,r6
-       sli.iz          r4,12,r5,r6
-       sli.im          r4,12,r5,r6
-       sr.dz           r4,12,r5,r6
-       sr.dm           r4,12,r5,r6
-       sr.ds           r4,12,r5,r6
-       sr.ez           r4,12,r5,r6
-       sr.em           r4,12,r5,r6
-       sr.es           r4,12,r5,r6
-       sr.iz           r4,12,r5,r6
-       sr.im           r4,12,r5,r6
-       sra             r4,32,r6,r8
-       sri.dz          r4,12,r5,r6
-       sri.dm          r4,12,r5,r6
-       sri.ds          r4,12,r5,r6
-       sri.ez          r4,12,r5,r6
-       sri.em          r4,12,r5,r6
-       sri.es          r4,12,r5,r6
-       sri.iz          r4,12,r5,r6
-       sri.im          r4,12,r5,r6
-       srl             r4,32,r6,r8
-       st.b            r4(r6),r8
-       st.h            r4(r6),r8
-       st              r4(r6),r8
-       st.d            r4(r6),r8
-       sub             r7,r8,r9
-       subu            r7,r8,r9
-       swcr            r8,r6,r4
-       trap            r10
-       vadd.ss         r2,r4,r4
-       vadd.sd         r2,r6,r6
-       vadd.dd         r2,r10,r10
-;      vld0.s          r6
-;      vld1.s          r7
-;      vld0.d          r6
-;      vld1.d          r8
-;      vmac.sss        r7,r9,0,a3
-;      vmac.sss        r7,r9,0,r10
-;      vmac.sss        r7,r9,a1,a3
-;      vmac.sss        r7,r9,a3,r10
-;      vmac.ssd        r7,r9,0,a0
-;      vmac.ssd        r7,r9,0,r10
-;      vmac.ssd        r7,r9,a1,a2
-;      vmac.ssd        r7,r9,a3,r10
-;      vmpy.ss         r1,r3,r3
-;      vmpy.sd         r5,r6,r6
-;      vmpy.dd         r2,r4,r4
-;      vmsc.sss        r7,r9,0,a0
-;      vmsc.sss        r7,r9,0,r10
-;      vmsc.sss        r7,r9,a0,a1
-;      vmsc.sss        r7,r9,a3,r10
-;      vmsc.ssd        r7,r9,0,a0
-;      vmsc.ssd        r7,r9,0,r10
-;      vmsc.ssd        r7,r9,a0,a1
-;      vmsc.ssd        r7,r9,a3,r10
-;      vmsub.ss        r6,a2,a4
-;      vmsub.sd        r6,a2,a4
-;      vmsub.ss        r4,a4,r6
-;      vmsub.sd        r4,a4,r6
-;      vrnd.si         r4,r6
-;      vrnd.si         r4,a0
-;      vrnd.su         r4,r6
-;      vrnd.su         r4,a0
-;      vrnd.ss         r4,r6
-;      vrnd.ss         r4,a0
-;      vrnd.sd         r4,r6
-;      vrnd.sd         r4,a0
-;      vrnd.di         r4,r6
-;      vrnd.di         r4,a0
-;      vrnd.du         r4,r6
-;      vrnd.du         r4,a0
-;      vrnd.ds         r4,r6
-;      vrnd.ds         r4,a0
-;      vrnd.dd         r4,r6
-;      vrnd.dd         r4,a0
-;      vrnd.is         r4,r6
-;      vrnd.id         r4,r6
-;      vrnd.us         r4,r6
-;      vrnd.ud         r4,r6
-;      vst.s           r6
-;      vst.d           r6
-;      vsub.ss         r2,r4,r6
-;      vsub.sd         r2,r4,r6
-;      vsub.dd         r2,r4,r6
-       wrcr            r6,r5
-       xnor            r5,r6,r7
-       xor             r7,r8,r9
diff --git a/gas/testsuite/gas/tic80/regops2.d b/gas/testsuite/gas/tic80/regops2.d
deleted file mode 100644 (file)
index 0b7f4a1..0000000
+++ /dev/null
@@ -1,68 +0,0 @@
-#objdump: -d
-#name: TIc80 register operands with :m modifier
-
-.*: +file format .*tic80.*
-
-Disassembly of section .text:
-
-00000000 <.text>:
-   0:  08 80 b7 02.*
-   4:  04 00 9e 02.*
-   8:  fc 7f 9e 02.*
-   c:  00 90 b7 02 78 56 34 12.*
-  14:  00 90 b7 02 ef be ad de.*
-  1c:  08 80 b7 0a.*
-  20:  04 00 9e 0a.*
-  24:  fc 7f 9e 0a.*
-  28:  00 90 b7 0a 78 56 34 12.*
-  30:  00 90 b7 0a ef be ad de.*
-  38:  04 84 b4 41.*
-  3c:  04 a4 b4 41.*
-  40:  04 c4 b4 41.*
-  44:  04 e4 b4 41.*
-  48:  00 94 b4 41 00 00 00 e0.*
-  50:  00 b4 b4 41 00 00 00 e0.*
-  58:  00 d4 b4 41 00 00 00 e0.*
-  60:  00 f4 b4 41 00 00 00 e0.*
-  68:  04 84 b5 41.*
-  6c:  04 a4 b5 41.*
-  70:  00 94 b5 41 00 00 00 e0.*
-  78:  00 b4 b5 41 00 00 00 e0.*
-  80:  04 84 b6 41.*
-  84:  04 a4 b6 41.*
-  88:  04 c4 b6 41.*
-  8c:  04 e4 b6 41.*
-  90:  00 94 b6 41 00 00 00 e0.*
-  98:  00 b4 b6 41 00 00 00 e0.*
-  a0:  00 d4 b6 41 00 00 00 e0.*
-  a8:  00 f4 b6 41 00 00 00 e0.*
-  b0:  04 80 b4 41.*
-  b4:  04 a0 b4 41.*
-  b8:  04 c0 b4 41.*
-  bc:  04 e0 b4 41.*
-  c0:  f0 7f 92 41.*
-  c4:  f0 ff 92 41.*
-  c8:  f0 7f 93 41.*
-  cc:  f0 ff 93 41.*
-  d0:  00 90 b4 41 00 00 00 e0.*
-  d8:  00 b0 b4 41 00 00 00 e0.*
-  e0:  00 d0 b4 41 00 00 00 e0.*
-  e8:  00 f0 b4 41 00 00 00 e0.*
-  f0:  04 80 b5 41.*
-  f4:  04 a0 b5 41.*
-  f8:  f0 7f 96 41.*
-  fc:  f0 ff 96 41.*
- 100:  00 90 b5 41 00 00 00 e0.*
- 108:  00 b0 b5 41 00 00 00 e0.*
- 110:  04 80 b6 41.*
- 114:  04 a0 b6 41.*
- 118:  04 c0 b6 41.*
- 11c:  04 e0 b6 41.*
- 120:  00 7f 9a 41.*
- 124:  00 ff 9a 41.*
- 128:  00 7f 9b 41.*
- 12c:  00 ff 9b 41.*
- 130:  00 90 b6 41 00 00 00 e0.*
- 138:  00 b0 b6 41 00 00 00 e0.*
- 140:  00 d0 b6 41 00 00 00 e0.*
- 148:  00 f0 b6 41 00 00 00 e0.*
diff --git a/gas/testsuite/gas/tic80/regops2.lst b/gas/testsuite/gas/tic80/regops2.lst
deleted file mode 100644 (file)
index 651fb97..0000000
+++ /dev/null
@@ -1,96 +0,0 @@
-MVP MP Macro Assembler     Version 1.13     Wed Feb 26 14:32:14 1997
-Copyright (c) 1993-1995    Texas Instruments Incorporated 
-
-regops2.s                                                            PAGE    1
-
-        1 00000000   02B78008         dcachec r8(r10:m)               ; Register form (modified)
-        2 00000004   029E0004         dcachec 4(r10:m)                ; Short Immediate form (positive offset) (modified)
-        3 00000008   029E7FFC         dcachec -4(r10:m)               ; Short Immediate form (negative offset) (modified)
-        4 0000000C   02B79000         dcachec 0x12345678(r10:m)       ; Long Immediate form (positive offset) (modified)
-          00000010   12345678 
-        5 00000014   02B79000         dcachec 0xDEADBEEF(r10:m)       ; Long Immediate form (negative offset) (modified)
-          00000018   DEADBEEF 
-        6 0000001C   0AB78008         dcachef r8(r10:m)               ; Register form (modified)
-        7 00000020   0A9E0004         dcachef 4(r10:m)                ; Short Immediate form (positive offset) (modified)
-        8 00000024   0A9E7FFC         dcachef -4(r10:m)               ; Short Immediate form (negative offset) (modified)
-        9 00000028   0AB79000         dcachef 0x12345678(r10:m)       ; Long Immediate form (positive offset) (modified)
-          0000002C   12345678 
-       10 00000030   0AB79000         dcachef 0xDEADBEEF(r10:m)       ; Long Immediate form (negative offset) (modified)
-          00000034   DEADBEEF 
-       11 00000038   41B48404         dld.b   r4(r6:m),r8             ; Register form
-       12 0000003C   41B4A404         dld.h   r4(r6:m),r8             ; Register form
-       13 00000040   41B4C404         dld     r4(r6:m),r8             ; Register form
-       14 00000044   41B4E404         dld.d   r4(r6:m),r8             ; Register form
-       15 00000048   41B49400         dld.b   0xE0000000(r6:m),r8     ; Long Immediate form
-          0000004C   E0000000 
-       16 00000050   41B4B400         dld.h   0xE0000000(r6:m),r8     ; Long Immediate form
-          00000054   E0000000 
-       17 00000058   41B4D400         dld     0xE0000000(r6:m),r8     ; Long Immediate form
-          0000005C   E0000000 
-       18 00000060   41B4F400         dld.d   0xE0000000(r6:m),r8     ; Long Immediate form
-          00000064   E0000000 
-       19 00000068   41B58404         dld.ub  r4(r6:m),r8             ; Register form
-       20 0000006C   41B5A404         dld.uh  r4(r6:m),r8             ; Register form
-       21 00000070   41B59400         dld.ub  0xE0000000(r6:m),r8     ; Long Immediate form
-          00000074   E0000000 
-       22 00000078   41B5B400         dld.uh  0xE0000000(r6:m),r8     ; Long Immediate form
-          0000007C   E0000000 
-       23 00000080   41B68404         dst.b   r4(r6:m),r8             ; Register form
-       24 00000084   41B6A404         dst.h   r4(r6:m),r8             ; Register form
-       25 00000088   41B6C404         dst     r4(r6:m),r8             ; Register form
-       26 0000008C   41B6E404         dst.d   r4(r6:m),r8             ; Register form
-       27 00000090   41B69400         dst.b   0xE0000000(r6:m),r8     ; Long Immediate form
-          00000094   E0000000 
-       28 00000098   41B6B400         dst.h   0xE0000000(r6:m),r8     ; Long Immediate form
-          0000009C   E0000000 
-       29 000000A0   41B6D400         dst     0xE0000000(r6:m),r8     ; Long Immediate form
-          000000A4   E0000000 
-       30 000000A8   41B6F400         dst.d   0xE0000000(r6:m),r8     ; Long Immediate form
-          000000AC   E0000000 
-       31 000000B0   41B48004         ld.b    r4(r6:m),r8             ; Register form
-       32 000000B4   41B4A004         ld.h    r4(r6:m),r8             ; Register form
-       33 000000B8   41B4C004         ld      r4(r6:m),r8             ; Register form
-       34 000000BC   41B4E004         ld.d    r4(r6:m),r8             ; Register form
-       35 000000C0   41927FF0         ld.b    -16(r6:m),r8            ; Short Immediate form
-       36 000000C4   4192FFF0         ld.h    -16(r6:m),r8            ; Short Immediate form
-       37 000000C8   41937FF0         ld      -16(r6:m),r8            ; Short Immediate form
-       38 000000CC   4193FFF0         ld.d    -16(r6:m),r8            ; Short Immediate form
-       39 000000D0   41B49000         ld.b    0xE0000000(r6:m),r8     ; Long Immediate form
-          000000D4   E0000000 
-       40 000000D8   41B4B000         ld.h    0xE0000000(r6:m),r8     ; Long Immediate form
-\fMVP MP Macro Assembler     Version 1.13     Wed Feb 26 14:32:14 1997
-Copyright (c) 1993-1995    Texas Instruments Incorporated 
-
-regops2.s                                                            PAGE    2
-
-          000000DC   E0000000 
-       41 000000E0   41B4D000         ld      0xE0000000(r6:m),r8     ; Long Immediate form
-          000000E4   E0000000 
-       42 000000E8   41B4F000         ld.d    0xE0000000(r6:m),r8     ; Long Immediate form
-          000000EC   E0000000 
-       43 000000F0   41B58004         ld.ub   r4(r6:m),r8             ; Register form
-       44 000000F4   41B5A004         ld.uh   r4(r6:m),r8             ; Register form
-       45 000000F8   41967FF0         ld.ub   -16(r6:m),r8            ; Short Immediate form
-       46 000000FC   4196FFF0         ld.uh   -16(r6:m),r8            ; Short Immediate form
-       47 00000100   41B59000         ld.ub   0xE0000000(r6:m),r8     ; Long Immediate form
-          00000104   E0000000 
-       48 00000108   41B5B000         ld.uh   0xE0000000(r6:m),r8     ; Long Immediate form
-          0000010C   E0000000 
-       49 00000110   41B68004         st.b    r4(r6:m),r8             ; Register form
-       50 00000114   41B6A004         st.h    r4(r6:m),r8             ; Register form
-       51 00000118   41B6C004         st      r4(r6:m),r8             ; Register form
-       52 0000011C   41B6E004         st.d    r4(r6:m),r8             ; Register form
-       53 00000120   419A7F00         st.b    -256(r6:m),r8           ; Short Immediate form
-       54 00000124   419AFF00         st.h    -256(r6:m),r8           ; Short Immediate form
-       55 00000128   419B7F00         st      -256(r6:m),r8           ; Short Immediate form
-       56 0000012C   419BFF00         st.d    -256(r6:m),r8           ; Short Immediate form
-       57 00000130   41B69000         st.b    0xE0000000(r6:m),r8     ; Long Immediate form
-          00000134   E0000000 
-       58 00000138   41B6B000         st.h    0xE0000000(r6:m),r8     ; Long Immediate form
-          0000013C   E0000000 
-       59 00000140   41B6D000         st      0xE0000000(r6:m),r8     ; Long Immediate form
-          00000144   E0000000 
-       60 00000148   41B6F000         st.d    0xE0000000(r6:m),r8     ; Long Immediate form
-          0000014C   E0000000 
-
- No Errors,  No Warnings
diff --git a/gas/testsuite/gas/tic80/regops2.s b/gas/testsuite/gas/tic80/regops2.s
deleted file mode 100644 (file)
index 18755b3..0000000
+++ /dev/null
@@ -1,60 +0,0 @@
-       dcachec r8(r10:m)               ; Register form (modified)
-       dcachec 4(r10:m)                ; Short Immediate form (positive offset) (modified)
-       dcachec -4(r10:m)               ; Short Immediate form (negative offset) (modified)
-       dcachec 0x12345678(r10:m)       ; Long Immediate form (positive offset) (modified)
-       dcachec 0xDEADBEEF(r10:m)       ; Long Immediate form (negative offset) (modified)
-       dcachef r8(r10:m)               ; Register form (modified)
-       dcachef 4(r10:m)                ; Short Immediate form (positive offset) (modified)
-       dcachef -4(r10:m)               ; Short Immediate form (negative offset) (modified)
-       dcachef 0x12345678(r10:m)       ; Long Immediate form (positive offset) (modified)
-       dcachef 0xDEADBEEF(r10:m)       ; Long Immediate form (negative offset) (modified)
-       dld.b   r4(r6:m),r8             ; Register form
-       dld.h   r4(r6:m),r8             ; Register form
-       dld     r4(r6:m),r8             ; Register form
-       dld.d   r4(r6:m),r8             ; Register form
-       dld.b   0xE0000000(r6:m),r8     ; Long Immediate form
-       dld.h   0xE0000000(r6:m),r8     ; Long Immediate form
-       dld     0xE0000000(r6:m),r8     ; Long Immediate form
-       dld.d   0xE0000000(r6:m),r8     ; Long Immediate form
-       dld.ub  r4(r6:m),r8             ; Register form
-       dld.uh  r4(r6:m),r8             ; Register form
-       dld.ub  0xE0000000(r6:m),r8     ; Long Immediate form
-       dld.uh  0xE0000000(r6:m),r8     ; Long Immediate form
-       dst.b   r4(r6:m),r8             ; Register form
-       dst.h   r4(r6:m),r8             ; Register form
-       dst     r4(r6:m),r8             ; Register form
-       dst.d   r4(r6:m),r8             ; Register form
-       dst.b   0xE0000000(r6:m),r8     ; Long Immediate form
-       dst.h   0xE0000000(r6:m),r8     ; Long Immediate form
-       dst     0xE0000000(r6:m),r8     ; Long Immediate form
-       dst.d   0xE0000000(r6:m),r8     ; Long Immediate form
-       ld.b    r4(r6:m),r8             ; Register form
-       ld.h    r4(r6:m),r8             ; Register form
-       ld      r4(r6:m),r8             ; Register form
-       ld.d    r4(r6:m),r8             ; Register form
-       ld.b    -16(r6:m),r8            ; Short Immediate form
-       ld.h    -16(r6:m),r8            ; Short Immediate form
-       ld      -16(r6:m),r8            ; Short Immediate form
-       ld.d    -16(r6:m),r8            ; Short Immediate form
-       ld.b    0xE0000000(r6:m),r8     ; Long Immediate form
-       ld.h    0xE0000000(r6:m),r8     ; Long Immediate form
-       ld      0xE0000000(r6:m),r8     ; Long Immediate form
-       ld.d    0xE0000000(r6:m),r8     ; Long Immediate form
-       ld.ub   r4(r6:m),r8             ; Register form
-       ld.uh   r4(r6:m),r8             ; Register form
-       ld.ub   -16(r6:m),r8            ; Short Immediate form
-       ld.uh   -16(r6:m),r8            ; Short Immediate form
-       ld.ub   0xE0000000(r6:m),r8     ; Long Immediate form
-       ld.uh   0xE0000000(r6:m),r8     ; Long Immediate form
-       st.b    r4(r6:m),r8             ; Register form
-       st.h    r4(r6:m),r8             ; Register form
-       st      r4(r6:m),r8             ; Register form
-       st.d    r4(r6:m),r8             ; Register form
-       st.b    -256(r6:m),r8           ; Short Immediate form
-       st.h    -256(r6:m),r8           ; Short Immediate form
-       st      -256(r6:m),r8           ; Short Immediate form
-       st.d    -256(r6:m),r8           ; Short Immediate form
-       st.b    0xE0000000(r6:m),r8     ; Long Immediate form
-       st.h    0xE0000000(r6:m),r8     ; Long Immediate form
-       st      0xE0000000(r6:m),r8     ; Long Immediate form
-       st.d    0xE0000000(r6:m),r8     ; Long Immediate form
diff --git a/gas/testsuite/gas/tic80/regops3.d b/gas/testsuite/gas/tic80/regops3.d
deleted file mode 100644 (file)
index 32a3012..0000000
+++ /dev/null
@@ -1,28 +0,0 @@
-#objdump: -d
-#name: TIc80 register operands with :s modifier
-
-.*: +file format .*tic80.*
-
-Disassembly of section .text:
-
-00000000 <.text>:
-   0:  04 0c b4 41.*
-   4:  04 2c b4 41.*
-   8:  04 4c b4 41.*
-   c:  04 6c b4 41.*
-  10:  04 0c b5 41.*
-  14:  04 2c b5 41.*
-  18:  04 0c b6 41.*
-  1c:  04 2c b6 41.*
-  20:  04 4c b6 41.*
-  24:  04 6c b6 41.*
-  28:  04 08 b4 41.*
-  2c:  04 28 b4 41.*
-  30:  04 48 b4 41.*
-  34:  04 68 b4 41.*
-  38:  04 08 b5 41.*
-  3c:  04 28 b5 41.*
-  40:  04 08 b6 41.*
-  44:  04 28 b6 41.*
-  48:  04 48 b6 41.*
-  4c:  04 68 b6 41.*
diff --git a/gas/testsuite/gas/tic80/regops3.lst b/gas/testsuite/gas/tic80/regops3.lst
deleted file mode 100644 (file)
index d65803f..0000000
+++ /dev/null
@@ -1,27 +0,0 @@
-MVP MP Macro Assembler     Version 1.13     Wed Feb 26 14:32:19 1997
-Copyright (c) 1993-1995    Texas Instruments Incorporated 
-
-regops3.s                                                            PAGE    1
-
-        1 00000000   41B40C04         dld.b   r4:s(r6),r8             ; Register form
-        2 00000004   41B42C04         dld.h   r4:s(r6),r8             ; Register form
-        3 00000008   41B44C04         dld     r4:s(r6),r8             ; Register form
-        4 0000000C   41B46C04         dld.d   r4:s(r6),r8             ; Register form
-        5 00000010   41B50C04         dld.ub  r4:s(r6),r8             ; Register form
-        6 00000014   41B52C04         dld.uh  r4:s(r6),r8             ; Register form
-        7 00000018   41B60C04         dst.b   r4:s(r6),r8             ; Register form
-        8 0000001C   41B62C04         dst.h   r4:s(r6),r8             ; Register form
-        9 00000020   41B64C04         dst     r4:s(r6),r8             ; Register form
-       10 00000024   41B66C04         dst.d   r4:s(r6),r8             ; Register form
-       11 00000028   41B40804         ld.b    r4:s(r6),r8             ; Register form
-       12 0000002C   41B42804         ld.h    r4:s(r6),r8             ; Register form
-       13 00000030   41B44804         ld      r4:s(r6),r8             ; Register form
-       14 00000034   41B46804         ld.d    r4:s(r6),r8             ; Register form
-       15 00000038   41B50804         ld.ub   r4:s(r6),r8             ; Register form
-       16 0000003C   41B52804         ld.uh   r4:s(r6),r8             ; Register form
-       17 00000040   41B60804         st.b    r4:s(r6),r8             ; Register form
-       18 00000044   41B62804         st.h    r4:s(r6),r8             ; Register form
-       19 00000048   41B64804         st      r4:s(r6),r8             ; Register form
-       20 0000004C   41B66804         st.d    r4:s(r6),r8             ; Register form
-
- No Errors,  No Warnings
diff --git a/gas/testsuite/gas/tic80/regops3.s b/gas/testsuite/gas/tic80/regops3.s
deleted file mode 100644 (file)
index 5ed87d5..0000000
+++ /dev/null
@@ -1,20 +0,0 @@
-       dld.b   r4:s(r6),r8             ; Register form
-       dld.h   r4:s(r6),r8             ; Register form
-       dld     r4:s(r6),r8             ; Register form
-       dld.d   r4:s(r6),r8             ; Register form
-       dld.ub  r4:s(r6),r8             ; Register form
-       dld.uh  r4:s(r6),r8             ; Register form
-       dst.b   r4:s(r6),r8             ; Register form
-       dst.h   r4:s(r6),r8             ; Register form
-       dst     r4:s(r6),r8             ; Register form
-       dst.d   r4:s(r6),r8             ; Register form
-       ld.b    r4:s(r6),r8             ; Register form
-       ld.h    r4:s(r6),r8             ; Register form
-       ld      r4:s(r6),r8             ; Register form
-       ld.d    r4:s(r6),r8             ; Register form
-       ld.ub   r4:s(r6),r8             ; Register form
-       ld.uh   r4:s(r6),r8             ; Register form
-       st.b    r4:s(r6),r8             ; Register form
-       st.h    r4:s(r6),r8             ; Register form
-       st      r4:s(r6),r8             ; Register form
-       st.d    r4:s(r6),r8             ; Register form
diff --git a/gas/testsuite/gas/tic80/regops4.d b/gas/testsuite/gas/tic80/regops4.d
deleted file mode 100644 (file)
index 33607c9..0000000
+++ /dev/null
@@ -1,28 +0,0 @@
-#objdump: -d
-#name: TIc80 register operands with both :m and :s modifier
-
-.*: +file format .*tic80.*
-
-Disassembly of section .text:
-
-00000000 <.text>:
-   0:  04 8c b4 41.*
-   4:  04 ac b4 41.*
-   8:  04 cc b4 41.*
-   c:  04 ec b4 41.*
-  10:  04 8c b5 41.*
-  14:  04 ac b5 41.*
-  18:  04 8c b6 41.*
-  1c:  04 ac b6 41.*
-  20:  04 cc b6 41.*
-  24:  04 ec b6 41.*
-  28:  04 88 b4 41.*
-  2c:  04 a8 b4 41.*
-  30:  04 c8 b4 41.*
-  34:  04 e8 b4 41.*
-  38:  04 88 b5 41.*
-  3c:  04 a8 b5 41.*
-  40:  04 88 b6 41.*
-  44:  04 a8 b6 41.*
-  48:  04 c8 b6 41.*
-  4c:  04 e8 b6 41.*
diff --git a/gas/testsuite/gas/tic80/regops4.lst b/gas/testsuite/gas/tic80/regops4.lst
deleted file mode 100644 (file)
index 3af3c9a..0000000
+++ /dev/null
@@ -1,27 +0,0 @@
-MVP MP Macro Assembler     Version 1.13     Wed Feb 26 14:32:25 1997
-Copyright (c) 1993-1995    Texas Instruments Incorporated 
-
-regops4.s                                                            PAGE    1
-
-        1 00000000   41B48C04         dld.b   r4:s(r6:m),r8           ; Register form
-        2 00000004   41B4AC04         dld.h   r4:s(r6:m),r8           ; Register form
-        3 00000008   41B4CC04         dld     r4:s(r6:m),r8           ; Register form
-        4 0000000C   41B4EC04         dld.d   r4:s(r6:m),r8           ; Register form
-        5 00000010   41B58C04         dld.ub  r4:s(r6:m),r8           ; Register form
-        6 00000014   41B5AC04         dld.uh  r4:s(r6:m),r8           ; Register form
-        7 00000018   41B68C04         dst.b   r4:s(r6:m),r8           ; Register form
-        8 0000001C   41B6AC04         dst.h   r4:s(r6:m),r8           ; Register form
-        9 00000020   41B6CC04         dst     r4:s(r6:m),r8           ; Register form
-       10 00000024   41B6EC04         dst.d   r4:s(r6:m),r8           ; Register form
-       11 00000028   41B48804         ld.b    r4:s(r6:m),r8           ; Register form
-       12 0000002C   41B4A804         ld.h    r4:s(r6:m),r8           ; Register form
-       13 00000030   41B4C804         ld      r4:s(r6:m),r8           ; Register form
-       14 00000034   41B4E804         ld.d    r4:s(r6:m),r8           ; Register form
-       15 00000038   41B58804         ld.ub   r4:s(r6:m),r8           ; Register form
-       16 0000003C   41B5A804         ld.uh   r4:s(r6:m),r8           ; Register form
-       17 00000040   41B68804         st.b    r4:s(r6:m),r8           ; Register form
-       18 00000044   41B6A804         st.h    r4:s(r6:m),r8           ; Register form
-       19 00000048   41B6C804         st      r4:s(r6:m),r8           ; Register form
-       20 0000004C   41B6E804         st.d    r4:s(r6:m),r8           ; Register form
-
- No Errors,  No Warnings
diff --git a/gas/testsuite/gas/tic80/regops4.s b/gas/testsuite/gas/tic80/regops4.s
deleted file mode 100644 (file)
index 5ba77e9..0000000
+++ /dev/null
@@ -1,20 +0,0 @@
-       dld.b   r4:s(r6:m),r8           ; Register form
-       dld.h   r4:s(r6:m),r8           ; Register form
-       dld     r4:s(r6:m),r8           ; Register form
-       dld.d   r4:s(r6:m),r8           ; Register form
-       dld.ub  r4:s(r6:m),r8           ; Register form
-       dld.uh  r4:s(r6:m),r8           ; Register form
-       dst.b   r4:s(r6:m),r8           ; Register form
-       dst.h   r4:s(r6:m),r8           ; Register form
-       dst     r4:s(r6:m),r8           ; Register form
-       dst.d   r4:s(r6:m),r8           ; Register form
-       ld.b    r4:s(r6:m),r8           ; Register form
-       ld.h    r4:s(r6:m),r8           ; Register form
-       ld      r4:s(r6:m),r8           ; Register form
-       ld.d    r4:s(r6:m),r8           ; Register form
-       ld.ub   r4:s(r6:m),r8           ; Register form
-       ld.uh   r4:s(r6:m),r8           ; Register form
-       st.b    r4:s(r6:m),r8           ; Register form
-       st.h    r4:s(r6:m),r8           ; Register form
-       st      r4:s(r6:m),r8           ; Register form
-       st.d    r4:s(r6:m),r8           ; Register form
diff --git a/gas/testsuite/gas/tic80/relocs1.c b/gas/testsuite/gas/tic80/relocs1.c
deleted file mode 100644 (file)
index 6af04b1..0000000
+++ /dev/null
@@ -1,28 +0,0 @@
-extern int xfunc (int y);
-
-static int sfunc (int y)
-{
-  xfunc (y);
-}
-
-int gfunc (int y)
-{
-  sfunc (y);
-}
-
-int branches (int y)
-{
-  int z;
-
-  for (z = y; z < y + 10; z++)
-    {
-      if (z & 0x1)
-       {
-         gfunc (z);
-       }
-      else
-       {
-         xfunc (z);
-       }
-    }
-}
diff --git a/gas/testsuite/gas/tic80/relocs1.d b/gas/testsuite/gas/tic80/relocs1.d
deleted file mode 100644 (file)
index 14ca6c9..0000000
+++ /dev/null
@@ -1,56 +0,0 @@
-#objdump: -d
-#name: TIc80 simple relocs, global/local funcs & branches (code)
-
-.*: +file format .*tic80.*
-
-Disassembly of section .text:
-
-00000000 <_sfunc>:
-   0:  f0 ff 6c 08.*
-   4:  0c 00 59 f8.*
-   8:  00 00 59 10.*
-   c:  00 90 38 f8 00 00 00 00.*
-  14:  00 00 51 10.*
-  18:  0c 00 51 f8.*
-  1c:  1f 80 38 00.*
-  20:  10 80 6c 08.*
-
-00000024 <_gfunc>:
-  24:  f0 ff 6c 08.*
-  28:  0c 00 59 f8.*
-  2c:  00 00 59 10.*
-  30:  00 90 38 f8 00 00 00 00.*
-  38:  00 00 51 10.*
-  3c:  0c 00 51 f8.*
-  40:  1f 80 38 00.*
-  44:  10 80 6c 08.*
-
-00000048 <_branches>:
-  48:  f0 ff 6c 08.*
-  4c:  0c 00 59 f8.*
-  50:  00 00 59 10.*
-  54:  00 00 51 10.*
-  58:  04 00 59 10.*
-  5c:  00 00 51 10.*
-  60:  04 00 51 18.*
-  64:  0a 80 ac 10.*
-  68:  03 00 ba 10.*
-  6c:  12 80 a5 30.*
-  70:  04 00 51 10.*
-  74:  05 80 a4 f8.*
-  78:  00 90 38 f8 24 00 00 00.*
-  80:  04 00 51 10.*
-  84:  04 80 24 00.*
-  88:  00 90 38 f8 00 00 00 00.*
-  90:  04 00 51 10.*
-  94:  04 00 51 10.*
-  98:  01 80 ac 10.*
-  9c:  04 00 59 10.*
-  a0:  00 00 51 18.*
-  a4:  04 00 51 10.*
-  a8:  0a 80 ec 18.*
-  ac:  02 00 fa 10.*
-  b0:  f0 ff a5 38.*
-  b4:  0c 00 51 f8.*
-  b8:  1f 80 38 00.*
-  bc:  10 80 6c 08.*
diff --git a/gas/testsuite/gas/tic80/relocs1.lst b/gas/testsuite/gas/tic80/relocs1.lst
deleted file mode 100644 (file)
index 9faeb1a..0000000
+++ /dev/null
@@ -1,80 +0,0 @@
-MVP MP Macro Assembler     Version 1.13     Sat Feb 22 13:19:28 1997
-Copyright (c) 1993-1995    Texas Instruments Incorporated 
-
-relocs1.s                                                            PAGE    1
-
-        1                     ;; This is the hand hacked output of the TI C compiler for a simple
-        2                     ;; test program that contains local/global functions, local/global
-        3                     ;; function calls, and an "if" and "for" statement.
-        4                     
-        5                             .global _xfunc
-        6                     
-        7 00000000            _sfunc:
-        8 00000000   086CFFF0          addu      -16,r1,r1
-        9 00000004   F859000C          st        12(r1),r31
-       10 00000008   10590000          st        0(r1),r2
-       11 0000000C   F8389000          jsr       _xfunc(r0),r31
-          00000010   00000000 
-       12 00000014   10510000          ld        0(r1),r2
-       13 00000018   F851000C          ld        12(r1),r31
-       14 0000001C   0038801F          jsr       r31(r0),r0
-       15 00000020   086C8010          addu      16,r1,r1
-       16                     
-       17                             .global _gfunc
-       18                     
-       19 00000024            _gfunc:
-       20 00000024   086CFFF0          addu      -16,r1,r1
-       21 00000028   F859000C          st        12(r1),r31
-       22 0000002C   10590000          st        0(r1),r2
-       23 00000030   F8389000          jsr       _sfunc(r0),r31
-          00000034   00000000 
-       24 00000038   10510000          ld        0(r1),r2
-       25 0000003C   F851000C          ld        12(r1),r31
-       26 00000040   0038801F          jsr       r31(r0),r0
-       27 00000044   086C8010          addu      16,r1,r1
-       28                     
-       29                     
-       30                             .global _branches
-       31                     
-       32 00000048            _branches:
-       33 00000048   086CFFF0          addu      -16,r1,r1
-       34 0000004C   F859000C          st        12(r1),r31
-       35 00000050   10590000          st        0(r1),r2
-       36 00000054   10510000          ld        0(r1),r2
-       37 00000058   10590004          st        4(r1),r2
-       38 0000005C   10510000          ld        0(r1),r2
-       39 00000060   18510004          ld        4(r1),r3
-       40 00000064   10AC800A          addu      10,r2,r2
-       41 00000068   10BA0003          cmp       r3,r2,r2
-       42 0000006C   30A58012          bbo.a     L12,r2,ge.w
-       43 00000070            L8:
-       44 00000070   10510004          ld        4(r1),r2
-       45 00000074   F8A48005          bbz.a     L10,r2,0
-       46 00000078   F8389000          jsr       _gfunc(r0),r31
-          0000007C   00000024 
-       47 00000080   10510004          ld        4(r1),r2
-       48 00000084   00248004          br.a      L11
-       49 00000088            L10:
-       50 00000088   F8389000          jsr       _xfunc(r0),r31
-          0000008C   00000000 
-       51 00000090   10510004          ld        4(r1),r2
-\fMVP MP Macro Assembler     Version 1.13     Sat Feb 22 13:19:28 1997
-Copyright (c) 1993-1995    Texas Instruments Incorporated 
-
-relocs1.s                                                            PAGE    2
-
-       52 00000094            L11:
-       53 00000094   10510004          ld        4(r1),r2
-       54 00000098   10AC8001          addu      1,r2,r2
-       55 0000009C   10590004          st        4(r1),r2
-       56 000000A0   18510000          ld        0(r1),r3
-       57 000000A4   10510004          ld        4(r1),r2
-       58 000000A8   18EC800A          addu      10,r3,r3
-       59 000000AC   10FA0002          cmp       r2,r3,r2
-       60 000000B0   38A5FFF0          bbo.a     L8,r2,lt.w
-       61 000000B4            L12:
-       62 000000B4   F851000C          ld        12(r1),r31
-       63 000000B8   0038801F          jsr       r31(r0),r0
-       64 000000BC   086C8010          addu      16,r1,r1
-
- No Errors,  No Warnings
diff --git a/gas/testsuite/gas/tic80/relocs1.s b/gas/testsuite/gas/tic80/relocs1.s
deleted file mode 100644 (file)
index 149e395..0000000
+++ /dev/null
@@ -1,66 +0,0 @@
-;; This is the hand hacked output of the TI C compiler for a simple
-;; test program that contains local/global functions, local/global
-;; function calls, and an "if" and "for" statement.
-
-       .file      "relocs1.s"
-
-       .global _xfunc
-
-_sfunc:
-         addu      -16,r1,r1
-         st        12(r1),r31
-         st        0(r1),r2
-         jsr       _xfunc(r0),r31
-         ld        0(r1),r2
-         ld        12(r1),r31
-         jsr       r31(r0),r0
-         addu      16,r1,r1
-
-       .global _gfunc
-
-_gfunc:
-         addu      -16,r1,r1
-         st        12(r1),r31
-         st        0(r1),r2
-         jsr       _sfunc(r0),r31
-         ld        0(r1),r2
-         ld        12(r1),r31
-         jsr       r31(r0),r0
-         addu      16,r1,r1
-
-
-       .global _branches
-
-_branches:
-         addu      -16,r1,r1
-         st        12(r1),r31
-         st        0(r1),r2
-         ld        0(r1),r2
-         st        4(r1),r2
-         ld        0(r1),r2
-         ld        4(r1),r3
-         addu      10,r2,r2
-         cmp       r3,r2,r2
-         bbo.a     L12,r2,ge.w
-L8:
-         ld        4(r1),r2
-         bbz.a     L10,r2,0
-         jsr       _gfunc(r0),r31
-         ld        4(r1),r2
-         br.a      L11
-L10:
-         jsr       _xfunc(r0),r31
-         ld        4(r1),r2
-L11:
-         ld        4(r1),r2
-         addu      1,r2,r2
-         st        4(r1),r2
-         ld        0(r1),r3
-         ld        4(r1),r2
-         addu      10,r3,r3
-         cmp       r2,r3,r2
-         bbo.a     L8,r2,lt.w
-L12:
-         ld        12(r1),r31
-         jsr       r31(r0),r0
-         addu      16,r1,r1
diff --git a/gas/testsuite/gas/tic80/relocs1b.d b/gas/testsuite/gas/tic80/relocs1b.d
deleted file mode 100644 (file)
index 4eb3161..0000000
+++ /dev/null
@@ -1,12 +0,0 @@
-#objdump: -r
-#source: relocs1.s
-#name: TIc80 simple relocs, global/local funcs & branches (relocs)
-
-.*: +file format .*tic80.*
-
-RELOCATION RECORDS FOR \[.text\]:
-OFFSET   TYPE              VALUE 
-00000010 32                _xfunc
-00000034 32                .text
-0000007c 32                .text
-0000008c 32                _xfunc
diff --git a/gas/testsuite/gas/tic80/relocs2.c b/gas/testsuite/gas/tic80/relocs2.c
deleted file mode 100644 (file)
index 3f1120c..0000000
+++ /dev/null
@@ -1,41 +0,0 @@
-extern char x_char;
-extern short x_short;
-static int x_int;
-extern long x_long;
-extern float x_float;
-extern double x_double;
-extern char *x_char_p;
-
-static char s_char;
-static short s_short;
-static int s_int;
-static long s_long;
-static float s_float;
-static double s_double;
-static char *s_char_p;
-
-char g_char;
-short g_short;
-int g_int;
-long g_long;
-float g_float;
-double g_double;
-char *g_char_p;
-
-main ()
-{
-  x_char = s_char;
-  g_char = x_char;
-  x_short = s_short;
-  g_short = x_short;
-  x_int = s_int;
-  g_int = x_int;
-  x_long = s_long;
-  g_long = x_long;
-  x_float = s_float;
-  g_float = x_float;
-  x_double = s_double;
-  g_double = x_double;
-  x_char_p = s_char_p;
-  g_char_p = x_char_p;
-}
diff --git a/gas/testsuite/gas/tic80/relocs2.d b/gas/testsuite/gas/tic80/relocs2.d
deleted file mode 100644 (file)
index cf3e87d..0000000
+++ /dev/null
@@ -1,37 +0,0 @@
-#objdump: -d
-#name: TIc80 simple relocs, static and global variables (code)
-
-.*: +file format .*tic80.*
-
-Disassembly of section .text:
-
-00000000 <_main>:
-   0:  00 10 34 10 24 02 00 00.*
-   8:  00 10 36 10 00 00 00 00.*
-  10:  00 10 34 10 00 00 00 00.*
-  18:  00 10 36 10 04 02 00 00.*
-  20:  00 30 34 10 24 03 00 00.*
-  28:  00 30 36 10 00 00 00 00.*
-  30:  00 30 34 10 00 00 00 00.*
-  38:  00 30 36 10 04 03 00 00.*
-  40:  00 50 34 10 34 02 00 00.*
-  48:  00 50 36 10 34 03 00 00.*
-  50:  00 50 34 10 34 03 00 00.*
-  58:  00 50 36 10 14 02 00 00.*
-  60:  00 50 34 10 f4 01 00 00.*
-  68:  00 50 36 10 00 00 00 00.*
-  70:  00 50 34 10 00 00 00 00.*
-  78:  00 50 36 10 f4 00 00 00.*
-  80:  00 50 34 10 f4 02 00 00.*
-  88:  00 50 36 10 00 00 00 00.*
-  90:  00 50 34 10 00 00 00 00.*
-  98:  00 50 36 10 14 03 00 00.*
-  a0:  00 70 34 10 e4 01 00 00.*
-  a8:  00 70 36 10 00 00 00 00.*
-  b0:  00 70 34 10 00 00 00 00.*
-  b8:  00 70 36 10 e4 02 00 00.*
-  c0:  00 50 34 10 44 03 00 00.*
-  c8:  00 50 36 10 00 00 00 00.*
-  d0:  00 50 34 10 00 00 00 00.*
-  d8:  00 50 36 10 e4 00 00 00.*
-  e0:  1f a0 38 00.*
diff --git a/gas/testsuite/gas/tic80/relocs2.lst b/gas/testsuite/gas/tic80/relocs2.lst
deleted file mode 100644 (file)
index 0690a8c..0000000
+++ /dev/null
@@ -1,112 +0,0 @@
-MVP MP Macro Assembler     Version 1.13     Sun Feb 23 12:16:32 1997
-Copyright (c) 1993-1995    Texas Instruments Incorporated 
-
-relocs2.s                                                            PAGE    1
-
-        1                     ;; This is the hand hacked output of the TI C compiler for a simple
-        2                     ;; test program that contains static, global, and extern data variables.
-        3                     
-        4                             .file   "relocs2.s"
-        5                             .global _x_char
-        6                             .global _x_short
-        7                             .global _x_long
-        8                             .global _x_float
-        9                             .global _x_double
-       10                             .global _x_char_p
-       11                             .global _g_char
-       12                             .global _g_short
-       13                             .global _g_int
-       14                             .global _g_long
-       15                             .global _g_float
-       16                             .global _g_double
-       17                             .global _g_char_p
-       18                             .global _main
-       19                     
-       20 00000000            _main:
-       21 00000000   10341000          ld.b      _s_char+0(r0),r2
-          00000004   0000001C 
-       22 00000008   10361000          st.b      _x_char+0(r0),r2
-          0000000C   00000000 
-       23 00000010   10341000          ld.b      _x_char+0(r0),r2
-          00000014   00000000 
-       24 00000018   10361000          st.b      _g_char+0(r0),r2
-          0000001C   00000014 
-       25 00000020   10343000          ld.h      _s_short+0(r0),r2
-          00000024   0000003C 
-       26 00000028   10363000          st.h      _x_short+0(r0),r2
-          0000002C   00000000 
-       27 00000030   10343000          ld.h      _x_short+0(r0),r2
-          00000034   00000000 
-       28 00000038   10363000          st.h      _g_short+0(r0),r2
-          0000003C   00000034 
-       29 00000040   10345000          ld        _s_int+0(r0),r2
-          00000044   00000020 
-       30 00000048   10365000          st        _x_int+0(r0),r2
-          0000004C   00000040 
-       31 00000050   10345000          ld        _x_int+0(r0),r2
-          00000054   00000040 
-       32 00000058   10365000          st        _g_int+0(r0),r2
-          0000005C   00000018 
-       33 00000060   10345000          ld        _s_long+0(r0),r2
-          00000064   00000010 
-       34 00000068   10365000          st        _x_long+0(r0),r2
-          0000006C   00000000 
-       35 00000070   10345000          ld        _x_long+0(r0),r2
-          00000074   00000000 
-       36 00000078   10365000          st        _g_long+0(r0),r2
-          0000007C   00000004 
-       37 00000080   10345000          ld        _s_float+0(r0),r2
-          00000084   00000030 
-       38 00000088   10365000          st        _x_float+0(r0),r2
-\fMVP MP Macro Assembler     Version 1.13     Sun Feb 23 12:16:32 1997
-Copyright (c) 1993-1995    Texas Instruments Incorporated 
-
-relocs2.s                                                            PAGE    2
-
-          0000008C   00000000 
-       39 00000090   10345000          ld        _x_float+0(r0),r2
-          00000094   00000000 
-       40 00000098   10365000          st        _g_float+0(r0),r2
-          0000009C   00000038 
-       41 000000A0   10347000          ld.d      _s_double+0(r0),r2
-          000000A4   00000008 
-       42 000000A8   10367000          st.d      _x_double+0(r0),r2
-          000000AC   00000000 
-       43 000000B0   10347000          ld.d      _x_double+0(r0),r2
-          000000B4   00000000 
-       44 000000B8   10367000          st.d      _g_double+0(r0),r2
-          000000BC   00000028 
-       45 000000C0   10345000          ld        _s_char_p+0(r0),r2
-          000000C4   00000044 
-       46 000000C8   10365000          st        _x_char_p+0(r0),r2
-          000000CC   00000000 
-       47 000000D0   10345000          ld        _x_char_p+0(r0),r2
-          000000D4   00000000 
-       48 000000D8   10365000          st        _g_char_p+0(r0),r2
-          000000DC   00000000 
-       49 000000E0   0038A01F          jsr.a     r31(r0),r0
-       50                     
-       51                             .global _g_char_p
-       52 00000000                    .bss    _g_char_p,4,4
-       53                             .global _g_long
-       54 00000004                    .bss    _g_long,4,4
-       55 00000008                    .bss    _s_double,8,8
-       56 00000010                    .bss    _s_long,4,4
-       57                             .global _g_char
-       58 00000014                    .bss    _g_char,1,4
-       59                             .global _g_int
-       60 00000018                    .bss    _g_int,4,4
-       61 0000001C                    .bss    _s_char,1,4
-       62 00000020                    .bss    _s_int,4,4
-       63                             .global _g_double
-       64 00000028                    .bss    _g_double,8,8
-       65 00000030                    .bss    _s_float,4,4
-       66                             .global _g_short
-       67 00000034                    .bss    _g_short,2,4
-       68                             .global _g_float
-       69 00000038                    .bss    _g_float,4,4
-       70 0000003C                    .bss    _s_short,2,4
-       71 00000040                    .bss    _x_int,4,4
-       72 00000044                    .bss    _s_char_p,4,4
-
- No Errors,  No Warnings
diff --git a/gas/testsuite/gas/tic80/relocs2.s b/gas/testsuite/gas/tic80/relocs2.s
deleted file mode 100644 (file)
index e4257df..0000000
+++ /dev/null
@@ -1,72 +0,0 @@
-;; This is the hand hacked output of the TI C compiler for a simple
-;; test program that contains static, global, and extern data variables.
-
-       .file   "relocs2.s"
-       .global _x_char
-       .global _x_short
-       .global _x_long
-       .global _x_float
-       .global _x_double
-       .global _x_char_p
-       .global _g_char
-       .global _g_short
-       .global _g_int
-       .global _g_long
-       .global _g_float
-       .global _g_double
-       .global _g_char_p
-       .global _main
-
-_main:
-         ld.b      _s_char+0(r0),r2
-         st.b      _x_char+0(r0),r2
-         ld.b      _x_char+0(r0),r2
-         st.b      _g_char+0(r0),r2
-         ld.h      _s_short+0(r0),r2
-         st.h      _x_short+0(r0),r2
-         ld.h      _x_short+0(r0),r2
-         st.h      _g_short+0(r0),r2
-         ld        _s_int+0(r0),r2
-         st        _x_int+0(r0),r2
-         ld        _x_int+0(r0),r2
-         st        _g_int+0(r0),r2
-         ld        _s_long+0(r0),r2
-         st        _x_long+0(r0),r2
-         ld        _x_long+0(r0),r2
-         st        _g_long+0(r0),r2
-         ld        _s_float+0(r0),r2
-         st        _x_float+0(r0),r2
-         ld        _x_float+0(r0),r2
-         st        _g_float+0(r0),r2
-         ld.d      _s_double+0(r0),r2
-         st.d      _x_double+0(r0),r2
-         ld.d      _x_double+0(r0),r2
-         st.d      _g_double+0(r0),r2
-         ld        _s_char_p+0(r0),r2
-         st        _x_char_p+0(r0),r2
-         ld        _x_char_p+0(r0),r2
-         st        _g_char_p+0(r0),r2
-         jsr.a     r31(r0),r0
-
-       .global _g_char_p
-       .bss    _g_char_p,4,4
-       .global _g_long
-       .bss    _g_long,4,4
-       .bss    _s_double,8,8
-       .bss    _s_long,4,4
-       .global _g_char
-       .bss    _g_char,1,4
-       .global _g_int
-       .bss    _g_int,4,4
-       .bss    _s_char,1,4
-       .bss    _s_int,4,4
-       .global _g_double
-       .bss    _g_double,8,8
-       .bss    _s_float,4,4
-       .global _g_short
-       .bss    _g_short,2,4
-       .global _g_float
-       .bss    _g_float,4,4
-       .bss    _s_short,2,4
-       .bss    _x_int,4,4
-       .bss    _s_char_p,4,4
diff --git a/gas/testsuite/gas/tic80/relocs2b.d b/gas/testsuite/gas/tic80/relocs2b.d
deleted file mode 100644 (file)
index 604f99d..0000000
+++ /dev/null
@@ -1,38 +0,0 @@
-#objdump: -r
-#source: relocs2.s
-#name: TIc80 simple relocs, static and global variables (relocs)
-
-.*: +file format .*tic80.*
-
-RELOCATION RECORDS FOR \[.text\]:
-OFFSET   TYPE              VALUE 
-00000004 32                .bss\+0xffffff1c
-0000000c 32                _x_char
-00000014 32                _x_char
-0000001c 32                .bss\+0xffffff1c
-00000024 32                .bss\+0xffffff1c
-0000002c 32                _x_short
-00000034 32                _x_short
-0000003c 32                .bss\+0xffffff1c
-00000044 32                .bss\+0xffffff1c
-0000004c 32                .bss\+0xffffff1c
-00000054 32                .bss\+0xffffff1c
-0000005c 32                .bss\+0xffffff1c
-00000064 32                .bss\+0xffffff1c
-0000006c 32                _x_long
-00000074 32                _x_long
-0000007c 32                .bss\+0xffffff1c
-00000084 32                .bss\+0xffffff1c
-0000008c 32                _x_float
-00000094 32                _x_float
-0000009c 32                .bss\+0xffffff1c
-000000a4 32                .bss\+0xffffff1c
-000000ac 32                _x_double
-000000b4 32                _x_double
-000000bc 32                .bss\+0xffffff1c
-000000c4 32                .bss\+0xffffff1c
-000000cc 32                _x_char_p
-000000d4 32                _x_char_p
-000000dc 32                .bss\+0xffffff1c
-
-
diff --git a/gas/testsuite/gas/tic80/tic80.exp b/gas/testsuite/gas/tic80/tic80.exp
deleted file mode 100644 (file)
index 49c4633..0000000
+++ /dev/null
@@ -1,21 +0,0 @@
-#
-# TI TMS320C80 tests.
-#
-if [istarget tic80*-*-*] then {
-
-    run_dump_test "regops"
-    run_dump_test "regops2"
-    run_dump_test "regops3"
-    run_dump_test "regops4"
-    run_dump_test "cregops"
-    run_dump_test "float"
-    run_dump_test "endmask"
-    run_dump_test "bitnum"
-    run_dump_test "ccode"
-    run_dump_test "add"
-    run_dump_test "relocs1"
-    run_dump_test "relocs1b"
-    run_dump_test "relocs2"
-    run_dump_test "relocs2b"
-    run_dump_test "align"
-}