[PATCH][AArch64] Fix generation of tst (PR87763)

The TST instruction no longer matches in all cases due to changes in
Combine.  The fix is simple, we now need to allow a subreg as well when
selecting the cc_mode.  This fixes the tst_5.c and tst_6.c failures.

AArch64 regress & bootstrap OK.

	PR rtl-optimization/87763
	* config/aarch64/aarch64.c (aarch64_select_cc_mode):
	Allow SUBREG when matching CC_NZmode compare.

From-SVN: r268265

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index cc4f4413f1427b8ad406909a5489e4e08d179d41..87794469c3bf7b855554d4ebe7429b9054c82180 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2019-01-25  Wilco Dijkstra  <wdijkstr@arm.com>
+
+       PR rtl-optimization/87763
+       * config/aarch64/aarch64.c (aarch64_select_cc_mode):
+       Allow SUBREG when matching CC_NZmode compare.
+
 2019-01-25  Richard Biener  <rguenther@suse.de>
 
        PR tree-optimization/89049

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 5df5a8b78439e69705e62845a4d1f86166a01894..8bddff9029bd48fbc245bf275ee3e1b3ffe8b55e 100644 (file)
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -7163,7 +7163,7 @@ aarch64_select_cc_mode (RTX_CODE code, rtx x, rtx y)
 
   /* Equality comparisons of short modes against zero can be performed
      using the TST instruction with the appropriate bitmask.  */
-  if (y == const0_rtx && REG_P (x)
+  if (y == const0_rtx && (REG_P (x) || SUBREG_P (x))
       && (code == EQ || code == NE)
       && (mode_x == HImode || mode_x == QImode))
     return CC_NZmode;