read_aiger to only clean own design

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index e8a355671751f8b44adf7c23facebe64cc9afec9..8d7588f8843b1c274e9073d91ddba36a4f5dba87 100644 (file)
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -722,8 +722,14 @@ void AigerReader::post_process()
     module->fixup_ports();
     design->add(module);
 
+    design->selection_stack.emplace_back(false);
+    RTLIL::Selection& sel = design->selection_stack.back();
+    sel.select(module);
+
     Pass::call(design, "clean");
 
+    design->selection_stack.pop_back();
+
     for (auto cell : module->cells().to_vector()) {
         if (cell->type != "$lut") continue;
         auto y_port = cell->getPort("\\Y").as_bit();