replace some f-strings and str.format calls with % as luke requested

diff --git a/src/openpower/decoder/test/test_decoder_gas.py b/src/openpower/decoder/test/test_decoder_gas.py
index dcedf676b4e3d9e03e58534513b9e124dce46e29..d4e47c08ab8439b205518c4cfb53c01c6247979b 100644 (file)
--- a/src/openpower/decoder/test/test_decoder_gas.py
+++ b/src/openpower/decoder/test/test_decoder_gas.py
@@ -57,10 +57,10 @@ class RegRegOp:
         self.r3 = Register(random.randrange(32))
 
     def generate_instruction(self):
-        string = "{} {}, {}, {}\n".format(self.opcodestr,
-                                          self.r1.num,
-                                          self.r2.num,
-                                          self.r3.num)
+        string = "%s %s, %s, %s\n" % (self.opcodestr,
+                                      self.r1.num,
+                                      self.r2.num,
+                                      self.r3.num)
         return string
 
     def check_results(self, pdecode2):
@@ -108,10 +108,10 @@ class RegImmOp(Checker):
         self.imm = random.randrange(32767)
 
     def generate_instruction(self):
-        string = "{} {}, {}, {}\n".format(self.opcodestr,
-                                          self.r1.num,
-                                          self.r2.num,
-                                          self.imm)
+        string = "%s %s, %s, %s\n" % (self.opcodestr,
+                                      self.r1.num,
+                                      self.r2.num,
+                                      self.imm)
         return string
 
     def check_results(self, pdecode2):
@@ -130,7 +130,7 @@ class RegImmOp(Checker):
         imm = yield pdecode2.e.imm_data.data
         in2_sel = yield pdecode2.dec.op.in2_sel
         imm_expected = self.get_imm(in2_sel)
-        msg = "imm: got {:x}, expected {:x}".format(imm, imm_expected)
+        msg = "imm: got %x, expected %x" % (imm, imm_expected)
         assert imm == imm_expected, msg
 
         rc = yield pdecode2.e.rc.data
@@ -162,10 +162,10 @@ class LdStOp(Checker):
         self.imm = random.randrange(32767)
 
     def generate_instruction(self):
-        string = "{} {}, {}({})\n".format(self.opcodestr,
-                                          self.r1.num,
-                                          self.imm,
-                                          self.r2.num)
+        string = "%s %s, %s(%s)\n" % (self.opcodestr,
+                                      self.r1.num,
+                                      self.imm,
+                                      self.r2.num)
         return string
 
     def check_results(self, pdecode2):
@@ -211,10 +211,10 @@ class CmpRegOp:
         self.cr = Register(random.randrange(8))
 
     def generate_instruction(self):
-        string = "{} {}, 0, {}, {}\n".format(self.opcodestr,
-                                             self.cr.num,
-                                             self.r1.num,
-                                             self.r2.num)
+        string = "%s %s, 0, %s, %s\n" % (self.opcodestr,
+                                         self.cr.num,
+                                         self.r1.num,
+                                         self.r2.num)
         return string
 
     def check_results(self, pdecode2):
@@ -246,12 +246,12 @@ class RotateOp:
         self.me = random.randrange(32)
 
     def generate_instruction(self):
-        string = "{} {},{},{},{},{}\n".format(self.opcodestr,
-                                              self.r1.num,
-                                              self.r2.num,
-                                              self.shift,
-                                              self.mb,
-                                              self.me)
+        string = "%s %s,%s,%s,%s,%s\n" % (self.opcodestr,
+                                          self.r1.num,
+                                          self.r2.num,
+                                          self.shift,
+                                          self.mb,
+                                          self.me)
         return string
 
     def check_results(self, pdecode2):
@@ -292,8 +292,8 @@ class Branch:
         self.addr = random.randrange(2**23) * 4
 
     def generate_instruction(self):
-        string = "{} {}\n".format(self.opcodestr,
-                                  self.addr)
+        string = "%s %s\n" % (self.opcodestr,
+                              self.addr)
         return string
 
     def check_results(self, pdecode2):
@@ -331,10 +331,10 @@ class BranchCond:
         self.bi = random.randrange(32)
 
     def generate_instruction(self):
-        string = "{} {},{},{}\n".format(self.opcodestr,
-                                        self.bo,
-                                        self.bi,
-                                        self.addr)
+        string = "%s %s,%s,%s\n" % (self.opcodestr,
+                                    self.bo,
+                                    self.bi,
+                                    self.addr)
         return string
 
     def check_results(self, pdecode2):
@@ -357,7 +357,7 @@ class BranchCond:
             assert(aa == 0)
 
         cr_sel = yield pdecode2.e.read_cr1.data
-        assert cr_sel == (self.bi//8), f"{cr_sel} {self.bi}"
+        assert cr_sel == (self.bi//8), "%s %s" % (cr_sel, self.bi)
 
 
 
@@ -379,10 +379,10 @@ class BranchRel:
         self.bi = random.randrange(32)
 
     def generate_instruction(self):
-        string = "{} {},{},{}\n".format(self.opcodestr,
-                                        self.bo,
-                                        self.bi,
-                                        self.bh)
+        string = "%s %s,%s,%s\n" % (self.opcodestr,
+                                    self.bo,
+                                    self.bi,
+                                    self.bh)
         return string
 
     def check_results(self, pdecode2):
@@ -418,10 +418,10 @@ class CROp:
         self.bt = random.randrange(32)
 
     def generate_instruction(self):
-        string = "{} {},{},{}\n".format(self.opcodestr,
-                                        self.bt,
-                                        self.ba,
-                                        self.bb)
+        string = "%s %s,%s,%s\n" % (self.opcodestr,
+                                    self.bt,
+                                    self.ba,
+                                    self.bb)
         return string
 
     def check_results(self, pdecode2):

diff --git a/src/openpower/test/runner.py b/src/openpower/test/runner.py
index 00de46914db1a2591212079834ee81cf9fd85bb8..9f89450f9639bffaf8d096b3dce230fef9a443ac 100644 (file)
--- a/src/openpower/test/runner.py
+++ b/src/openpower/test/runner.py
@@ -86,7 +86,8 @@ class SimRunner(StateRunner):
 
             # extra new-line so it's easier to visually separate each
             # instruction in output
-            log(f"\n0x{sim.pc.CIA.value:04X}: {ins % (1 << 32):08X} {code}",
+            log("\n0x%04X: %08X %s" % (sim.pc.CIA.value,
+                                       ins % (1 << 32), code),
                 kind=LogKind.InstrInOuts)
 
             log("sim instr: 0x{:X} pc=0x{:X}".format(ins & 0xffffffff,
@@ -110,7 +111,7 @@ class SimRunner(StateRunner):
             state = yield from TestState("sim", sim, dut, code)
             sim_states.append(state)
 
-        log(f"final pc: 0x{sim.pc.CIA.value:X}", kind=LogKind.InstrInOuts)
+        log("final pc: 0x%X" % (sim.pc.CIA.value,), kind=LogKind.InstrInOuts)
 
         if self.dut.allow_overlap:
             # get last state, at end of run
@@ -257,8 +258,8 @@ class TestRunnerBase(FHDLTestCase):
                                     if signed == "i" and \
                                             value & (1 << (sz - 1)) != 0:
                                         value -= 1 << sz
-                                    values += f" {signed}{sz}:{value}"
-                            out.append(f"r{i} = 0x{v:X} {values}")
+                                    values += " %s%d:%d" % (signed, sz, value)
+                            out.append("r%d = 0x%X %s" % (i, v, values))
                         return "\n".join(out)
                     log("regs:", format_regs(test.regs),
                         kind=LogKind.InstrInOuts)
@@ -272,7 +273,7 @@ class TestRunnerBase(FHDLTestCase):
                         pc = 0
                         out = []
                         for line in assembly.splitlines():
-                            out.append(f"pc=0x{pc:04X}: {line}")
+                            out.append("pc=0x%04X: %s" % (pc, line))
                             if not line.startswith(".set ") and \
                                     line.partition('#')[0].strip() != "":
                                 pc += 4