re PR target/24861 (internal compiler error when building gcc with --with-cpu=ep9312...

	PR target/24861
	* arm.md (split for movsf with immediate): Restrict split to insns
	that set a general register.

From-SVN: r107104

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d0ef8fc110f19896b1ba30a5eb2b7de11bc33013..5c7ce8e91a9ac3a0664a9a48c22c65c7a64cfc32 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2005-11-16  Richard Earnshaw  <richard.earnshaw@arm.com>
+
+       PR target/24861
+       * arm.md (split for movsf with immediate): Restrict split to insns
+       that set a general register.
+
 2005-11-16  Daniel Jacobowitz  <dan@codesourcery.com>
 
        * config/ia64/unwind-ia64.c (uw_advance_context): New.  Call

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 1b671fa1d1ee73a315c4c16cc2f3c6df107a35c3..aa28c3fae77f566fc9bfa73940b07b21451b03e4 100644 (file)
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -5137,11 +5137,12 @@
   "
 )
 
+;; Transform a floating-point move of a constant into a core register into
+;; an SImode operation.
 (define_split
-  [(set (match_operand:SF 0 "nonimmediate_operand" "")
+  [(set (match_operand:SF 0 "arm_general_register_operand" "")
        (match_operand:SF 1 "immediate_operand" ""))]
   "TARGET_ARM
-   && !(TARGET_HARD_FLOAT && TARGET_FPA)
    && reload_completed
    && GET_CODE (operands[1]) == CONST_DOUBLE"
   [(set (match_dup 2) (match_dup 3))]