Fix an issue with "Rearrange MIPS INSN* masks" patch.

This fixes an issue with Mark Shinwell's "Rearrange MIPS INSN* masks" patch
(https://sourceware.org/ml/binutils/2007-11/msg00231.html).  In the patch
the pref instruction had its membership flags changed from I4|I32|G3 to
I4_32|G3.  Unfortunately G3 was defined as being I4, which made the actual
expanded flags as: I4|I32|I4 and therefore the membership flags should have
been I4_32.  Since the patch was committed G3 was redefined to be I4|EE.  This
fix just removes I4 from G3 making the expanded membership flags for pref as
I4_32|EE.

ChangeLog:

opcodes/
	* mips-opc.c (G3): Remove I4.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 47555e6b262c31ddf2e8dc4f6a523e86017489e9..08c69624dd8dc6e6b43d461deb533049db9d7af4 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2014-05-07  Andrew Bennett  <andrew.bennett@imgtec.com>
+
+       * mips-opc.c (G3): Remove I4.
+
 2014-05-05  H.J. Lu  <hongjiu.lu@intel.com>
 
        PR binutils/16893

diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 9181c3f54444e3dc320c8a452b9f1e56cb055769..ba89622ff903b4c4010cf01cead051fd893039f7 100644 (file)
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -296,9 +296,7 @@ decode_mips_operand (const char *p)
 #define G2      (T3             \
                  )
 
-#define G3      (I4             \
-                 |EE            \
-                 )
+#define G3      EE
 
 /* 64 bit CPU with 32 bit FPU (single float). */
 #define SF     EE