It looks like this was meant to facilitate unfenced access to textures/
color/renderbuffers. It's totally incomplete and fundamentally broken
on a few levels:
- broken: The kernel needs to about every tiled bo to fix up bit17
swizzling on swap-in.
- unflexible: fenced/unfenced relocs from execbuffer2 do the same, much
simpler.
- unneeded: with relaxed fencing tiled gem bos are as memory-efficient
as this trick.
Hence kill it.
Reviewed-by: Jakob Bornecrantz <wallbraker@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Jakob Bornecrantz <wallbraker@gmail.com>
unsigned depth_stride; /* per-image on i945? */
unsigned total_nblocksy;
- unsigned sw_tiled; /**< tiled with software flags */
unsigned hw_tiled; /**< tiled with hardware fences */
unsigned nr_images[I915_MAX_TEXTURE_2D_LEVELS];
/* setup any hw fences */
if (tex->hw_tiled) {
- assert(tex->sw_tiled == I915_TILE_NONE);
iws->buffer_set_fence_reg(iws, tex->buffer, tex->stride, tex->hw_tiled);
}
struct i915_texture *tex = i915_texture(cbuf_surface->texture);
assert(tex);
- if (tex && tex->sw_tiled) {
- ctile = BUF_3D_TILED_SURFACE;
- }
-
OUT_BATCH(_3DSTATE_BUF_INFO_CMD);
OUT_BATCH(BUF_3D_ID_COLOR_BACK |
struct i915_texture *tex = i915_texture(depth_surface->texture);
assert(tex);
- if (tex && tex->sw_tiled) {
- ztile = BUF_3D_TILED_SURFACE;
- }
-
OUT_BATCH(_3DSTATE_BUF_INFO_CMD);
assert(tex);
assert(format);
assert(pitch);
- if (tex->sw_tiled) {
- assert(!((pitch - 1) & pitch));
- tiled = MS3_TILED_SURFACE;
- }
-
/* MS3 state */
state[0] =
(((height - 1) << MS3_HEIGHT_SHIFT)